JP2010147032A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device avoiding heat load exerted at the gate insulating film forming process or the like to achieve a depth-direction doping profile reduced in impurity concentration on the uppermost surface of a channel, thereby improving ON-state current. <P>SOLUTION: After formation of a gate electrode, a channel impurity is ion-implanted at an angle of 10° or less using the gate electrode as a mask. Then, the channel impurity is activated by annealing using RTA (Rapid Thermal Anneal) such that the concentration of the channel impurity in a predetermined depth from the surface of a substrate is made constant in a gate length direction. After subsequent extension/halo implantation and deep S/D (source/drain) implantation, activation is performed by diffusionless annealing. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a high on-current can be obtained by reducing the impurity concentration of a channel near the surface of a substrate.

  2. Description of the Related Art In recent years, a technique for improving an on-current using strain due to a stopper nitride film or the like has been studied as the miniaturization of a CMOS (Complementary Metal Oxide Semiconductor) transistor proceeds. However, the on-current improvement technology by distortion is premised on the good characteristics of the transistor. If the intrinsic performance of the transistor is not good, the on-current improvement technology by distortion cannot be fully utilized. For these reasons, it is still important to increase the on-current (on-current before applying distortion) as the intrinsic performance of the transistor.

  One such technique is to reduce the ion concentration near the top surface of the channel, as seen in retrograde channels, to suppress ionized impurity scattering and improve on-current. As such an attempt, for example, as shown in Patent Document 1, the doping profile in the depth direction of the channel is controlled by ion implantation, and as shown in Patent Document 2, low epitaxial growth of silicon is used. There is an example of trying to create an (intrinsic) channel with an impurity concentration.

  On the other hand, as to the timing of introducing the impurity into the channel, as in Patent Documents 1 and 2, it is common to perform ion implantation before forming the gate insulating film, but the impurity is ion implanted into the channel after forming the gate electrode. There are also examples. For example, Patent Documents 3 to 6 are examples. In these, channel impurities are obliquely ion-implanted after the gate electrode is formed.

In Patent Document 3, in order to increase the channel impurity concentration below the center of the gate, As of 100 keV energy is implanted through the gate electrode at 30 to 45 degrees in a p-type MOS transistor. In Patent Document 4, in place of the long-time heat treatment for diffusing channel impurities under the gate, B having an energy of 150 to 200 keV is ion-implanted at 45 degrees in an n-type MOS transistor. In Patent Document 5, in order to prevent a threshold voltage drop due to a short channel effect in a fine gate transistor, an example in which B of 50 keV energy is implanted at 50 degrees in an n-type MOS transistor so as to cause a reverse short channel effect. Is described. In Patent Document 6, P of an energy of 300 keV is ion-implanted at an angle of 40 degrees in a p-type MOS transistor.
JP-A-11-214686 JP 2006-49897 A JP 2000-340671 A JP-A-10-32330 JP-A-7-226508 Japanese Patent Laid-Open No. 10-173071

  In the method of manufacturing a semiconductor device disclosed in Patent Documents 1 and 2, a step of forming a gate insulating film is performed after forming a doping profile in the depth direction by reducing the impurity concentration on the uppermost surface of the channel. . For this reason, channel impurities are subjected to a large thermal load (thermal budget) in the gate insulating film forming step, and diffuse and redistribute above the substrate. As a result, the intended impurity distribution could not be obtained by the methods of Patent Documents 1 and 2. Alternatively, the effect (improvement of on-current by reducing the impurity concentration on the surface) could not be obtained sufficiently.

  In Patent Documents 3 to 6, there is a method in which ion implantation of channel impurities is performed after the formation of the gate electrode for the purpose other than forming the doping profile in the depth direction by reducing the impurity concentration on the uppermost surface of the channel. It is disclosed. When such a method is used, the thermal load in the gate insulating film forming step can be avoided. However, in the methods of Patent Documents 3 to 6, it is difficult to form a doping profile in the depth direction in which the impurity concentration on the uppermost surface of the channel is reduced. This is because, since the angle of ion implantation is large, a considerable amount of impurities are already distributed near the substrate surface in the impurity distribution immediately after channel implantation. As a result, the on-current cannot be improved.

  An object of the present invention is to manufacture a semiconductor device that achieves a doping profile in the depth direction by reducing the impurity concentration on the uppermost surface of the channel while avoiding a large thermal load in the gate insulating film forming process, and improving the on-current Is to provide a method.

[Features of the invention]
The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a MOS transistor having a gate length that is not more than twice the distance of diffusion when channel impurities are activated by RTA (Rapid Thermal Annealing). Thereafter, ion implantation of a channel impurity is performed at an angle of 10 degrees or less using the gate electrode as a mask, and then the activation of the impurity introduced by this ion implantation is performed with the channel impurity concentration at a predetermined depth from the substrate surface being the gate length. In order to be constant in the direction, for example, annealing using RTA (for example, spike annealing, annealing for which the temperature is raised to a target temperature, then maintained at that temperature for 0 second, and lowered), and further extension / Activation after halo implantation, deep S / D (source / drain) implantation, diffusionless annealing (eg, Laser annealing or flash lamp annealing), or diffusion is very small anneal (e.g., and performing at a low temperature annealing).

[Action]
In the method of manufacturing a semiconductor device according to the present invention, channel impurity ions are implanted at an angle of 10 degrees or less using a gate electrode as a mask. In this impurity distribution, a considerable amount of impurities is never located near the substrate surface under the gate electrode. However, since channel impurities are not introduced deeply under the gate electrode, in order to prevent this, diffusion is performed by RTA (spike annealing) with a small thermal load. Since the semiconductor device which is the subject of the present invention is a MOS transistor having a gate length that is not more than twice the distance at which the channel impurity is diffused by the activation annealing at this time, when RTA is performed, the channel impurity is immediately after ion implantation. A channel impurity is introduced deep in the gate electrode, which did not exist. If the channel impurity concentration is too high, the threshold voltage rises and no on-current can be obtained, so that the channel impurity concentration at a predetermined depth from the substrate surface becomes constant in the gate length direction. As a guide. By performing such a process, a doping profile in the depth direction in which the impurity concentration on the uppermost surface of the channel is reduced can be realized after the gate insulating film manufacturing step. Further, after this profile is produced, the gate insulating film production process is not performed, and even after activation after extension / halo implantation and deep S / D (source / drain) implantation, almost no diffusion is caused. A MOS transistor can be manufactured while maintaining the profile.

  According to the present invention, it is possible to improve the on-current (on-current before applying distortion) as the intrinsic performance of the MOS transistor.

[First Embodiment of the Invention]
Next, the manufacturing method of the first embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 to FIG. 4 are cross-sectional views showing the state of each stage of the manufacturing process of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) of the present invention. Each cross-sectional view shows a cross section in the gate length direction (direction perpendicular to the gate electrode) of the MISFET. In each cross-sectional view, two MISFETs are shown. The left side is an n-type MISFET and the right side is a p-type MISFET. The first embodiment of the present invention is an example in which a manufacturing method characteristic of the present invention is used for a MISFET formed by a normal S / D process (a process in which formation of deep S / D is performed after extension / halo formation). It is.

First, as shown in FIG. 1A, an element isolation structure 2 is formed on a Si substrate 1. In this case, an STI (Shallow Trench Isolation) method, which is a general method for producing element isolation of the MISFET, is used. Alternatively, a LOCOS (Local Oxidation of Silicon) method may be used. In the present invention, it is normally assumed that the Si (100) plane is used. However, the present invention is not limited to the plane orientation of the substrate. Therefore, even if a Si substrate having a different plane such as the Si (110) plane is used. Good. Also, an SOI (Silicon on Insulator) substrate or an SGOI (Silicon Germanium on Insulator) substrate may be used. Further, it is not limited to the channel direction of the transistor. After the element isolation structure is fabricated, lithography is performed, and p-well implantation is performed in a region that becomes an n-type FET (Field Effect Transistor). For example, as p-well implantation, monovalent B ions are implanted at 8 × 10 ¹² cm ⁻² at an energy of 150 keV. After the implantation, the resist is peeled off, and lithography is performed again, and an n-well implantation is performed in a region that becomes a p-type FET. For example, monovalent P ions are implanted at 1.5 × 10 ¹³ cm ⁻² at an energy of 350 keV. Thereafter, when the resist is peeled off, the cross-sectional shape of FIG.

Next, as shown in FIG. 1B, a gate insulating film 5 and a gate electrode layer 6 are formed on the silicon substrate 1. For example, an oxynitride film having a thickness of 1.2 nm is formed as the gate insulating film. As the gate insulating film 5, an oxide film, Ta ₂ O ₅ , Al ₂ O ₃ , HfO ₂ , ZrO ₂ , ZrON, HfON, HfAlON, HfSiON, or other so-called High-k film may be used. Good. Moreover, these laminated films may be used. In the present embodiment, the following description will be made assuming that the gate insulating film 5 is an oxynitride film. After the formation of the gate insulating film 5, a gate electrode material is deposited. For example, polysilicon 130 nm is deposited using a CVD (Chemical Vapor Deposition) method. As a material for the gate electrode layer 6, in addition to poly-Si, metals such as poly-SiGe, TaN, TiN, W, WN, full silicide using NiSi, or the like can be used. Alternatively, a stacked structure of these materials may be used. In the present embodiment, the following description will be made assuming that the gate electrode material is poly-Si.

Thereafter, as shown in FIGS. 1C and 1D, the gate electrode material is pre-doped. First, as shown in FIG. 1C, lithography is performed, and pre-doping is performed on a region that becomes a gate electrode of an n-type FET. Pre-doping is performed, for example, by implanting monovalent P ions at an energy of 6 keV at 4 × 10 ¹⁵ cm ⁻² . Thereafter, the resist 18 is removed, and lithography is performed again, and as shown in FIG. 1D, pre-doping is performed on a region that becomes a gate electrode of the p-type FET. This pre-doping is performed, for example, by implanting monovalent B ions at an energy of 2 keV and 4 × 10 ¹⁵ cm ⁻² . After the implantation, the resist 18 is peeled off.

After pre-doping, lithography is performed, and the gate electrode layer 6 is etched using an HBr / O ₂ gas with a resist as a mask. After etching, the resist is peeled off. Then, as shown in FIG. 1E, the n-type FET gate electrode 7 and the p-type FET gate electrode 8 are formed.

  Thereafter, the impurity pre-doped in the gate is activated by RTA. For example, activation is performed by spike annealing at 1030 ° C. This RTA is for causing sufficient impurities to prevent gate depletion at the interface between the gate electrode and the gate insulating film. As will be described later, RTA annealing is performed in a later process in order to activate the channel impurities. Conditions for controlling the channel impurity concentration under the gate electrode are set in this annealing, and the gate electrode Since this impurity may not be sufficient for diffusing the impurity to the vicinity of the gate insulating film interface, annealing is performed at this stage. Ideally, the amount of impurities sufficient to prevent gate depletion at the interface between the gate electrode and the gate insulating film with a thermal load combined with RTA for activating the channel impurities performed in a later process. This annealing is preferably set so that If necessary, an offset spacer may be formed (not shown) in order to prevent escape of impurities doped in the gate before annealing.

Next, an impurity is introduced into the channel portion, and a channel profile in the depth direction is produced by reducing the impurity concentration in the vicinity of the uppermost portion of the channel by a technique characteristic of the present invention.
First, as shown in FIG. 2F, lithography is performed to form a resist mask 18 so that ions can be implanted only into a region to be an n-type FET. Then, ion implantation is performed to introduce channel impurities of the n-type FET using the resist 18 and the gate electrode 7 of the n-type FET as a mask. For example, monovalent B ions are implanted at 8 × 10 ¹² cm ⁻² at an energy of 10 keV. Thereafter, the resist 18 is peeled off.

Next, as shown in FIG. 2G, lithography is performed to form a resist mask 18 so that ions can be implanted only into a region that becomes a p-type FET. Then, ion implantation is performed to introduce channel impurities of the n-type FET using the resist 18 and the gate electrode 8 of the p-type FET as a mask. For example, monovalent As ions are implanted at 3 × 10 ¹² cm ⁻² at an energy of 70 keV. Thereafter, the resist 18 is peeled off.

  Then, as shown in FIG. 2 (h), these impurities are activated by spike annealing at 1000 ° C. Also, during this spike annealing, impurities diffuse into the channel region under the gate electrode.

  In the present invention, as shown in FIGS. 2F to 2H, the channel profile in the depth direction is formed after the gate insulating film is formed. In addition, as will be described later, it is a principle to use diffusion-less annealing (or annealing with small diffusion) so that the profile is not broken after the profile is produced. Therefore, as in Patent Documents 1 and 2, it is possible to avoid the intended channel profile from being damaged by a large thermal load in the subsequent process.

  In the present invention, when channel impurities of n-type FET and p-type FET are introduced, unlike in Patent Documents 3 to 6, the ion implantation angle is set to 10 degrees or less, and the ion implantation is performed at an angle close to or perpendicular to the ion implantation. To do. The reason for this is schematically shown in FIGS. 5A to 5C (FIG. 5 shows an n-type FET as an example). If only the angle of ion implantation is changed from vertical to oblique, even when ion implantation is performed using the gate electrode 7 as a mask, channel impurities are introduced into the region under the gate electrode 7 and the depth thereof is increased. It becomes shallower. An object of the present invention is to reduce the impurity concentration near the uppermost surface of the channel region in order to improve the on-current. When ion implantation with a large angle is performed, a considerable amount of impurities already exists in the vicinity of the uppermost surface of the channel region in the impurity distribution immediately after the implantation, so that a target doping profile in the depth direction cannot be produced. Therefore, in the present invention, the ion implantation angle when introducing the channel impurity is set to 10 degrees or less. However, in the impurity distribution immediately after the ion implantation at an angle of 10 degrees or less, as shown in FIG. 5A, the region under the gate electrode 7 is formed at a shallow portion or a deep portion (for forming a p-well). In the state where impurities are not present (except for the impurity introduced by (1)), the short channel effect appears remarkably and the fine MOS transistor does not operate. For this reason, it is necessary to introduce an impurity deep in the region under the gate electrode 7.

  For this purpose, spike annealing is performed in FIG. 2H to activate and diffuse the impurities. As a result, in the present invention, the channel impurity distribution as shown in FIG.

  FIG. 6A schematically shows the impurity profile after FIG. 2H, taking an n-type FET as an example. Each point of A, B, C, and D in the cross-sectional view of FIG. 6A corresponds to the position of each graph indicating the impurity concentration in FIG. Each point of A and B indicates a point where the channel impurity concentration becomes maximum in the depth direction in the source side or drain side region. A point C indicates a portion in contact with the gate insulating film 5 in the channel region immediately below the center of the gate electrode 7, and a point D indicates a deep portion in the channel region immediately below the center of the gate 7.

  In the present invention, by performing annealing with an appropriate thermal load in FIG. 2 (h), as shown in FIG. 6 (a), the impurity concentration deep under the gate electrode 7 is changed in the gate length direction (from point A to B). Impurity distribution that is substantially constant in the direction of the point is realized (in our experiments, for example, when the impurity concentration is increased by 50% below the center of the gate electrode 7 in the direction from the A point to the B point in the pMOS. Since the absolute value of the threshold voltage is increased by 0.05 V or more and the effect of improving the on-current which the present invention is aimed for cannot be obtained, the change in the impurity concentration from the point A to the point B is at least + − It is preferable that the impurity distribution be within 30% and be as close to the impurity distribution as possible. At this time, the channel profile in the depth direction (from the point C to the point D) under the gate electrode 7 is a profile in which the impurity concentration near the uppermost surface of the channel region is reduced. By producing such a profile and performing the process described later, an improvement in on-current which is the object of the present invention is realized.

  In the present invention, the relationship between the diffusion distance of the annealing performed in FIG.

  When the diffusion distance of the annealing performed in FIG. 2 (h) is much smaller than 1/2 of the gate length, it becomes as shown in FIG. 6 (b) (FIG. 6 (b) increases the gate length, (The correlation between the diffusion distance by annealing and the gate length is shown.) In this case, no impurity is present in the region under the gate electrode 7, the short channel effect becomes remarkable, and the threshold voltage is significantly reduced.

  On the other hand, when the diffusion distance of annealing performed in FIG. 2 (h) is much longer than ½ of the gate length, the impurity distribution is as shown in FIG. 6 (c) (FIG. The correlation between the diffusion distance by annealing and the gate length is illustrated. In this case, the impurity concentration in the vicinity of the uppermost surface of the channel region under the gate electrode becomes too high, the threshold voltage rises, and the on-current when the voltage applied to the gate electrode 7 is the same voltage as the predetermined power supply voltage Will fall. Therefore, it is important to realize the situation as shown in FIG.

  Japanese Patent Application Laid-Open No. 60-058673 describes a method of diffusing channel impurities under the gate electrode 7 by annealing. In Japanese Patent Laid-Open No. 60-058673, it is described in FIG. 3 that the impurity distribution corresponding to FIG. 6C of the present invention is realized, and that a decrease in threshold voltage due to the short channel effect can be suppressed. It has been. However, in the case of JP-A-60-058673, as described above, the impurity concentration in the vicinity of the uppermost surface of the channel region under the gate becomes high, and the on-current cannot be improved as in the present invention. In the present invention, the threshold voltage drop due to the short channel effect is suppressed by lowering the energy of extension implantation in the process described later, or adopting halo implantation, and the distribution of channel impurities is disclosed in JP-A-60-058673. The profile shown in FIG. 6 (a) of the present invention is not the profile as shown in FIG. 3 (FIG. 6 (c) of the present invention). The effect which cannot be obtained by the gazette is realized.

  As inferred from the above description, when there are MOS transistors having different gate lengths in the same chip, the method of the present invention cannot be applied to all of them. In general, an integrated circuit chip has two types of transistors, a core transistor and an I / O transistor, each having the same gate length in the chip and constituting the main part of the circuit. The gate length of the core transistor is smaller. In such a case, the present invention is applied to this core transistor. For the I / O transistor, the channel impurity implantation is performed simultaneously with the well implantation in FIGS. 1C and 1D, as in the conventional fabrication method.

  In a CMOS integrated circuit, there are an n-type FET and a p-type FET, and impurities used for these channels are different. Therefore, the distance diffused by spike annealing in FIG. 2 (h) differs between the impurity used for the channel of the n-type FET and the impurity used for the channel of the p-type FET. Therefore, the profile immediately after the ion implantation shown in FIGS. 2F and 2G is adjusted by the following method. As an example, consider the case where the impurity used for the channel of the n-type FET is B and the impurity used for the channel of the p-type FET is As.

  First, the first method is to change the angle of ion implantation in FIGS. 2 (f) and 2 (g). For B and As, the diffusion constant is larger for B. For example, the ion implantation of As in FIG. 2 (f) is an oblique implantation of 5 degrees, and the ion implantation of B in FIG. 2 (g) is a vertical implantation. . The second method is to change the RTA (spike annealing) conditions depending on the impurity used for the channel of the n-type FET and the impurity used for the channel of the p-type FET. For this purpose, as shown in FIG. 2F, channel impurity As used for the channel of the p-type FET is implanted first, and then RTA (spike annealing) is performed once (not shown). Next, as shown in FIG. 2G, channel impurity B used for the channel of the n-type FET is implanted, and RTA (spike annealing) is performed. In accordance with the RTA (spike annealing) condition of B, the diffusion distance of As is insufficient. Therefore, the diffusion corresponding to this shortage is performed in advance by RTA (injection of channel impurity As used for the channel of the p-type FET). Complement with spike annealing). The third method is to change the thickness of the offset spacer of the n-type FET and the p-type FET. For example, in FIG. 2F, after channel implantation of p-type FET channel impurities and resist stripping, an offset spacer having a film thickness of 4 nm is fabricated. By doing so, when the channel impurity (As) ion implantation of the p-type FET is implanted, the offset spacer is implanted at 0 nm, and when the channel impurity (B) ion implantation of the n-type FET is implanted, the offset spacer is implanted at 4 nm. be able to. However, the offset spacer is an important parameter used also in the extension design. Since the conditions of the offset spacer at the time of channel injection of the present invention and the conditions of the offset spacer at the time of extension design do not necessarily match, in these three methods, either the first method or the second method, or A combination of the first and second methods is preferred.

  As shown in FIGS. 2 (f) to 2 (h), an impurity is introduced into the channel portion, and the channel profile in the depth direction is obtained by reducing the impurity concentration near the top of the channel by a technique characteristic of the present invention. After fabrication, the MOS transistor process is advanced by a normal method. In FIG. 3 and FIG. 4 below, the channel impurity distribution shown in FIG.

First, as shown in FIG. 3I, lithography is performed to form a resist mask 18 so that ions can be implanted only into a region to be an n-type FET. Then, ion implantation is performed to form the S / D extension electrode region 12 of the n-type FET using the resist 18 and the gate electrode 7 of the n-type FET as a mask. For example, monovalent As ions are implanted at 5 × 10 ¹⁴ cm ⁻² at an energy of 2 keV. Thereafter, the resist 18 is peeled off. Although not shown in FIG. 3 (n), ion implantation for forming a pocket region may be performed before or after ion implantation for forming the S / D extension electrode region 12 of the n-type FET. . For example, monovalent BF 2 ions are implanted by 2 × 10 ¹³ cm ⁻² ions.

Next, as shown in FIG. 3J, lithography is performed to form a resist mask 18 so that ions can be implanted only into a region that becomes a p-type FET. Then, ion implantation is performed to form the S / D extension electrode region 13 of the p-type FET using the resist 18 and the gate electrode 8 of the p-type FET as a mask. For example, monovalent B ions are implanted at an energy of 0.5 keV at 5 × 10 ¹⁴ cm ⁻² . Thereafter, the resist 18 is peeled off. Although not shown in FIG. 3 (o), ion implantation for forming the pocket region may be performed before or after the ion implantation for forming the S / D extension electrode region 13 of the p-type FET. . For example, 2 × 10 ¹³ cm ⁻² ions are implanted with monovalent As ions.

  Then, as shown in FIG. 3 (k), the impurities introduced in FIGS. 3 (i) and (j) are activated by laser annealing. For example, activation is performed at a temperature of 1330 ° C. using a carbon dioxide laser with a wavelength of 10.6 μm.

  Thereafter, as shown in FIG. 3L, the sidewall 9 is produced. For this purpose, first, an insulating film to be a gate sidewall is deposited. For example, an oxide film of 50 nm is deposited using a CVD method. Thereafter, the material deposited as the sidewall insulating film is etched back to form the gate sidewall 9. Note that a nitride film may be used as the sidewall insulating film, or a stacked film of an oxide film and a nitride film may be used. Note that when the sidewall insulating film is deposited, the temperature is set to 750 ° C. or lower, preferably 650 ° C. or lower, and more preferably 550 ° C. or lower. This is to prevent inactivation of impurities highly activated by laser annealing.

Thereafter, as shown in FIG. 4M, lithography is performed to form a resist mask 18 so that ions can be implanted only into a region to be an n-type FET. Then, ion implantation is performed to form a deep S / D electrode region 10 of the n-type FET using the resist 18, the gate electrode 7 of the n-type FET, and the gate sidewall 9 as a mask. For example, monovalent As ions are implanted at 3 × 10 ¹⁵ cm ⁻² at an energy of 12 keV. Thereafter, the resist 18 is peeled off.

Next, as shown in FIG. 4N, lithography is performed to form a resist mask 18 so that ions can be implanted only into a region that becomes a p-type FET. Then, ion implantation is performed to form a deep S / D electrode region 11 of the p-type FET using the resist 18, the gate electrode 8 of the p-type FET, and the gate sidewall 9 as a mask. For example, monovalent B ions are implanted at an energy of 2 keV at 3 × 10 ¹⁵ cm ⁻² . Thereafter, the resist 18 is peeled off.

  Then, as shown in FIG. 4 (o), the impurities introduced in FIGS. 7 (m) and (n) are activated by laser annealing. For example, activation is performed at a temperature of 1330 ° C. using a carbon dioxide laser with a wavelength of 10.6 μm.

  Finally, as shown in FIG. 4 (p), silicide is formed in the deep S / D electrode region. For example, Ni silicide having a thickness of 20 nm is formed. The silicide is not limited to Ni silicide, but may be Ti silicide, Co silicide, Pd silicide, Pt silicide, or Er silicide. Further, a metal alloy silicide (for example, NiPt silicide) may be used. Thereafter, a stopper insulating film and an interlayer insulating film are deposited, lithography and etching are performed, contact holes are formed, and metal is embedded to form contacts (not shown). As the metal used for the contact, W, Al, TiN, Ti, Cu, or a laminated film of these metals is used. Thereafter, the wiring process is performed at a temperature of 400 ° C. or lower to complete the device.

  The on-current of the MOS transistor formed in this way was increased by about 5 to 10% compared to a MOS transistor having a uniform impurity channel concentration when channel injection was performed before the gate insulating film was formed.

Note that the technique of the present invention is not limited by the type of impurities. For example, in the above description, B has been described as an example of an impurity to be introduced into the channel region of the n-type FET. However, In can be used, and both B and In impurities can be used simultaneously. Further, a cluster such as B ₁₀ H ₁₄ or B ₁₈ H ₂₂ may be ion-implanted.

  In the above description, an example in which laser annealing by a carbon dioxide gas laser is used as the annealing in FIGS. 3K and 4O has been described, but the type of annealing is not limited thereto. For example, laser annealing using a semiconductor laser having a wavelength of 810 nm, laser annealing using a YAG laser having a wavelength of 1064 nm, flash lamp annealing, and low temperature annealing using RTA (for example, 600 ° C. for 30 seconds) are also possible. Further, a combination of these annealings (for example, annealing treatment in which laser annealing is performed after low-temperature annealing is performed) may be used. Further, it is not necessary to use the same type of annealing in FIGS. 3 (k) and 4 (o). What is important is that in the annealing shown in FIGS. 3 (k) and 4 (o), a diffusion-less annealing or an annealing with a very small diffusion is used so as not to destroy the profile produced in FIG.

  By producing a CMOS transistor through the above-described process, it is 5% or more compared to the conventional manufacturing method (when channel implantation is performed before forming the gate insulating film and the channel has a uniform channel impurity density). Improved on-current can be obtained.

[Second Embodiment of the Invention]
Next, a manufacturing method according to the second embodiment of the present invention will be described in detail with reference to the drawings.

  7 to 8 are cross-sectional views showing the state of each stage of the manufacturing process of the MISFET of the present invention. Each cross-sectional view shows a cross section in the gate length direction (direction perpendicular to the gate electrode) of the MISFET. In each cross-sectional view, two MISFETs are shown. The left side is an n-type MISFET and the right side is a p-type MISFET. In the second embodiment of the present invention, a manufacturing method characteristic of the present invention is used for a MISFET formed by a reverse S / D process (a process in which deep S / D is formed before extension / halo formation). It is an example.

  In the manufacturing method of this embodiment, first, the steps from FIG. 1A to FIG. 1E of the first embodiment are performed.

  Next, as shown in FIG. 7F, a gate sidewall is fabricated. For this purpose, first, an insulating film to be a gate sidewall is deposited. For example, a 50 nm nitride film is deposited. Thereafter, the material deposited as the sidewall insulating film is etched back to form the gate sidewall 9. Note that as the sidewall insulating film, an oxide film may be used, or a stacked film of an oxide film and a nitride film may be used.

Thereafter, as shown in FIGS. 7G to 7I, formation and activation of a deep S / D electrode region are performed.
First, as shown in FIG. 7G, lithography is performed to form a resist mask 18 so that ions can be implanted only into a region to be an n-type FET. Then, ion implantation is performed to form a deep S / D electrode region 10 of the n-type FET using the resist 18, the gate electrode 7 of the n-type FET, and the gate sidewall 9 as a mask. For example, monovalent As ions are implanted at 3 × 10 ¹⁵ cm ⁻² at an energy of 8 keV. Thereafter, the resist 18 is peeled off.

Next, as shown in FIG. 7H, lithography is performed to form a resist mask 18 so that ions can be implanted only into a region that becomes a p-type FET. Then, ion implantation is performed to form a deep S / D electrode region 11 of the p-type FET using the resist 18, the gate electrode 8 of the p-type FET, and the gate sidewall 9 as a mask. For example, monovalent B ions are implanted at 3 × 10 ¹⁵ cm ⁻² at an energy of 1.2 keV. Thereafter, the resist 18 is peeled off.

  After the deep S / D electrode region is formed, the sidewall insulating film 9 is removed as shown in FIG. If a nitride film is used as the sidewall insulating film 9, it is removed using phosphoric acid.

  Thereafter, as in FIGS. 2 (f) to 2 (h) of the first embodiment, an impurity is introduced into the channel portion, and the impurity concentration in the vicinity of the top of the channel is set by a technique characteristic of the present invention. Create a thin, depth channel profile. If necessary, an offset spacer may be formed before FIG. In FIG. 2H, the channel impurity is activated in the first embodiment, but in this embodiment, the deep S / D electrode impurity is also activated by this annealing.

  Then, as shown in FIGS. 8J to 8L, extension electrode regions are formed and activated.

First, as shown in FIG. 8J, lithography is performed to form a resist mask 18 so that ions can be implanted only into a region to be an n-type FET. Then, ion implantation is performed to form the S / D extension electrode region 12 of the n-type FET using the resist 18 and the gate electrode 7 of the n-type FET as a mask. For example, monovalent As ions are implanted at 5 × 10 ¹⁴ cm ⁻² at an energy of 2 keV. Thereafter, the resist 18 is peeled off. Although not shown in FIG. 8J, ion implantation for forming a pocket region may be performed before or after ion implantation for forming the S / D extension electrode region 12 of the n-type FET. . For example, 1 × 10 ¹³ cm ⁻² ions are implanted with monovalent BF 2 ions.

Next, as shown in FIG. 8K, lithography is performed to form a resist mask 18 so that ions can be implanted only into a region that becomes a p-type FET. Then, ion implantation is performed to form the S / D extension electrode region 13 of the p-type FET using the resist 18 and the gate electrode 8 of the p-type FET as a mask. For example, monovalent B ions are implanted at an energy of 0.5 keV at 5 × 10 ¹⁴ cm ⁻² . Thereafter, the resist 18 is peeled off. Although not shown in FIG. 8K, ion implantation for forming a pocket region may be performed before or after ion implantation for forming the S / D extension electrode region 13 of the p-type FET. . For example, 1 × 10 ¹³ cm ⁻² ions are implanted with monovalent As ions.

  Thereafter, as shown in FIG. 8L, the impurities introduced in FIGS. 8J and 8K are activated by laser annealing. For example, activation is performed at a temperature of 1330 ° C. using a carbon dioxide laser with a wavelength of 10.6 μm.

  Thereafter, as shown in FIG. 8 (m), a second sidewall 14 is produced. For this purpose, first, an insulating film to be a gate sidewall is deposited. For example, an oxide film of 50 nm is deposited. Thereafter, the material deposited as the sidewall insulating film is etched back to form the gate sidewall 14. Note that a nitride film may be used as the sidewall insulating film, or a stacked film of an oxide film and a nitride film may be used. Note that when the sidewall insulating film is deposited, the temperature is set to 750 ° C. or lower, preferably 650 ° C. or lower, and more preferably 550 ° C. or lower. This is to prevent inactivation of impurities highly activated by laser annealing.

  Finally, as shown in FIG. 8 (n), silicide is formed in the deep S / D electrode region. For example, Ni silicide having a thickness of 20 nm is formed. The silicide is not limited to Ni silicide, but may be Ti silicide, Co silicide, Pd silicide, Pt silicide, Er silicide, or silicide of these metal alloys such as NiPt silicide. It doesn't matter. Thereafter, a stopper insulating film and an interlayer insulating film are deposited, lithography and etching are performed, contact holes are formed, and metal is embedded to form contacts (not shown). As the metal used for the contact, W, Al, TiN, Ti, Cu, or a laminated film of these metals is used. Thereafter, the wiring process is performed at a temperature of 400 ° C. or lower to complete the device.

  In this embodiment, since the reverse process is used, the number of steps is slightly increased. However, the insulating film for forming the second sidewall 14 can be deposited at a low temperature. The profile is not prone to deepening and the short channel effect is easily suppressed. For the same reason, the channel profile is not easily broken, and a high on-state current is possible.

FIG. 5 is a process chart showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a process chart showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a process chart showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 5 is a process chart showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a schematic diagram showing a difference in impurity distribution depending on an implantation angle when ion-implanting a channel impurity in the semiconductor device manufacturing method according to the first embodiment of the present invention. FIG. 5 is a schematic diagram showing a difference in impurity distribution after ion implantation of channel impurities and activation in the semiconductor device manufacturing method according to the first embodiment of the present invention. Process drawing which shows the manufacturing method of the semiconductor device of the 2nd Embodiment of this invention. Process drawing which shows the manufacturing method of the semiconductor device of the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation insulating film 3 P well 4 N well 5 Gate insulating film 6 Gate electrode layer 7 Gate electrode 8 of n-type FET Gate electrode 9 of p-type FET Side wall insulating film (first side wall insulating film)
10 n-type FET deep S / D electrode 11 p-type FET deep S / D electrode 12 n-type FET S / D extension electrode 13 p-type FET S / D extension electrode 14 side wall insulating film (second Side wall insulation film)
15 Silicide 16 Lamp light 17 Laser light 18 Resist

Claims (8)

  A method of manufacturing a MIS transistor formed on a semiconductor substrate and having a channel region formed immediately below a gate electrode, wherein the channel region is formed at an angle of 10 degrees or less using the gate electrode as a mask after the gate electrode is formed. After that, channel impurities are ion-implanted, and then channel impurity activation is performed by annealing with RTA so that the channel impurity concentration at a predetermined depth from the substrate surface is constant in the gate length direction, and then introduced. A method for manufacturing a semiconductor device, wherein the activated impurities are activated by diffusion-less annealing.   A method of manufacturing a MIS transistor formed on a semiconductor substrate and having a channel region formed immediately below a gate electrode, wherein the channel region is formed at an angle of 10 degrees or less using the gate electrode as a mask after the gate electrode is formed. After that, channel impurities are ion-implanted, and then the channel impurities are activated by RTA so that the channel impurity concentration at a predetermined depth from the substrate surface falls within a range of plus or minus 30% in the gate length direction. A method for manufacturing a semiconductor device, characterized in that the annealing is performed, and the impurities introduced thereafter are activated by diffusion-less annealing.   3. A method of manufacturing a CMOS transistor according to claim 1, wherein an angle for ion-implanting the channel impurity of the n-type FET is different from an angle for ion-implanting the channel impurity of the p-type FET. .   A method of manufacturing a CMOS transistor, in which channel impurities of a p-type FET are ion-implanted before channel impurities of an n-type FET, and after ion implantation of channel impurities of a p-type FET and ion implantation of channel impurities of an n-type FET 3. The method of manufacturing a semiconductor device according to claim 1, wherein annealing by RTA is performed twice later.   5. The method of manufacturing a semiconductor device according to claim 1, wherein spike annealing at 950 ° C. or higher is used as the annealing by RTA.   5. The method of manufacturing a semiconductor device according to claim 1, wherein any one of laser annealing using a carbon dioxide laser, laser annealing using a semiconductor laser, and flash lamp annealing is used as the diffusion-less annealing. .   In the process of manufacturing the MISFET, the S / D extension electrode region is manufactured first, and then the deep S / D electrode region is manufactured (usually the S / D process). A method for manufacturing a semiconductor device according to claim 1.   In the process of manufacturing a deep S / D electrode region in the MISFET manufacturing process first, and then manufacturing the S / D extension electrode region (reversed S / D process), it is applied to the formation of the channel region. A method for manufacturing a semiconductor device according to claim 1.

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