JP2010141174A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent electrostatic discharge breakdown of a circuit element and which uses a through electrode, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device including a stack of semiconductor substrates 40 and 50 includes the through electrode 61 penetrating the semiconductor substrate 40, a circuit including a potential interconnect 13 expected to be connected to a first potential, a circuit including a potential interconnect 23 to be connected to the first potential, and an electrostatic discharge protection circuit 30, wherein the circuit 10 is provided to the semiconductor substrate 40, the circuit 20 is provided to the semiconductor substrate 50, and the potential interconnect 13 of the circuit 10 and the potential interconnect 23 of the circuit 20 are electrically connected to each other through the through electrode 61 and electrostatic discharge protection circuit 30. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and the like.

  Due to the downsizing of electronic devices, the mounting space for electronic components such as semiconductor devices mounted inside the electronic devices is being limited. For this reason, downsizing of electronic components such as semiconductor devices is required.

  As a method for reducing the size of a semiconductor device, a method for forming a semiconductor device by stacking semiconductor substrates (semiconductor chips) has been proposed. In this method, semiconductor chips having similar functions or semiconductor chips having different functions are stacked, and the semiconductor chips are interconnected to achieve high-density mounting of the semiconductor chips.

As a method for wiring connection between semiconductor chips, a method has been proposed in which a through-electrode (wiring electrode penetrating through a semiconductor chip) is provided in a semiconductor chip, thereby wiring-connecting between the semiconductor chips.
JP 2007-49103 A

  When electrically separating wirings connected to the power supply potential in order to supply different power supply voltages to multiple circuits, or electrically connecting the wirings connected to the ground potential to suppress the influence of noise and the like between the circuits. May be separated.

  Similarly, when a semiconductor device is configured by stacking a plurality of semiconductor substrates, the wiring connected to the power supply potential and the wiring connected to the ground potential are electrically separated for each semiconductor substrate, For example, the wiring connected to the power supply potential and the wiring connected to the ground potential may be electrically separated for each circuit.

  In such a case, there is no discharge path when an electrostatic voltage is applied between the external terminals connected to the electrically isolated potential wiring, so that the circuit element may be destroyed.

  The present invention has been made in view of the above technical problems. According to some aspects of the present invention, it is possible to provide a semiconductor device using a through electrode and a method for manufacturing the semiconductor device, which can suppress electrostatic discharge destruction of a circuit element.

(1) A semiconductor device according to the present invention includes:
A semiconductor device including a plurality of stacked semiconductor substrates,
A through electrode penetrating a given semiconductor substrate among the plurality of semiconductor substrates; and
A plurality of circuits including a potential wiring to be connected to the first potential;
Including an electrostatic discharge protection circuit,
The plurality of circuits are provided on different semiconductor substrates,
The potential wiring of one circuit of the plurality of circuits and the potential wiring of another circuit of the plurality of circuits are electrically connected to each other via the through electrode and the electrostatic discharge protection circuit. It is characterized by being connected.

  According to the present invention, when an electrostatic voltage is applied between electrically separated potential wirings, the through electrode and the electrostatic discharge protection circuit serve as a discharge path. Thereby, the electrostatic discharge destruction of a circuit element can be suppressed.

(2) This semiconductor device
The electrostatic discharge protection circuit that is a part of an electrical path between the potential wiring of one circuit of the plurality of circuits and the potential wiring of another circuit of the plurality of circuits is the plurality of May be provided on the semiconductor substrate on which one of the circuits is provided.

(3) A semiconductor device according to the present invention includes:
A semiconductor device including a plurality of stacked semiconductor substrates,
A through electrode penetrating a given semiconductor substrate among the plurality of semiconductor substrates; and
A plurality of circuits including a potential wiring to be connected to the first potential;
Including an electrostatic discharge protection circuit,
The plurality of circuits and the electrostatic discharge protection circuit are provided on the different semiconductor substrates,
The potential wiring of one circuit of the plurality of circuits and the potential wiring of another circuit of the plurality of circuits are electrically connected to each other via the through electrode and the electrostatic discharge protection circuit. It is characterized by being connected.

(4) This semiconductor device
The electrostatic discharge protection circuit may be provided on a semiconductor substrate manufactured by a manufacturing process that is least refined among the plurality of semiconductor substrates.

(5) This semiconductor device
Including a plurality of through electrodes,
The potential wiring of one circuit of the plurality of circuits and the potential wiring of another circuit of the plurality of circuits are different from circuit elements that are part of the electrostatic discharge protection circuit, respectively. You may be connected by the some electrical path | route via the penetration electrode.

(6) This semiconductor device
Each of the plurality of electrical paths may be a part of the electrostatic discharge protection circuit, and may include circuit elements provided on different semiconductor substrates.

(7) This semiconductor device
Including three or more circuits including a potential wiring connected to the first potential;
The three or more circuits are provided on the different semiconductor substrates,
The potential wiring of each of the three or more circuits may be electrically connected to the through electrode via the electrostatic discharge protection circuit corresponding to each of the three or more circuits.

(8) This semiconductor device
The electrostatic discharge protection circuit may include parallel diodes having different directions.

(9) This semiconductor device
The first potential may be a ground potential.

(10) A method for manufacturing a semiconductor device according to the present invention includes:
Laminating multiple semiconductor substrates,
A through electrode penetrating a given semiconductor substrate among the plurality of semiconductor substrates; and
A plurality of circuits including a potential wiring to be connected to the first potential;
A method of manufacturing a semiconductor device including an electrostatic discharge protection circuit,
The plurality of circuits are provided on the different semiconductor substrates, and the potential wiring of one circuit of the plurality of circuits and the potential wiring of another circuit of the plurality of circuits are connected to the through electrode. And the electrostatic discharge protection circuit are electrically connected to each other.

(11) A method for manufacturing a semiconductor device according to the present invention includes:
Laminating multiple semiconductor substrates,
A through electrode penetrating a given semiconductor substrate among the plurality of semiconductor substrates; and
A plurality of circuits including a potential wiring to be connected to the first potential;
A method of manufacturing a semiconductor device including an electrostatic discharge protection circuit,
The plurality of circuits and the electrostatic discharge protection circuit are provided on the different semiconductor substrates, the potential wiring of one circuit of the plurality of circuits, and another circuit of the plurality of circuits The potential wiring is electrically connected to each other through the through electrode and the electrostatic discharge protection circuit.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments. Moreover, this invention shall include what combined the following content freely.

1. First Embodiment FIG. 1 is a circuit diagram of a semiconductor device according to a first embodiment.

  The semiconductor device 1 according to the first embodiment includes a circuit 10, a circuit 20, and an electrostatic discharge protection circuit 30. Further, the semiconductor device 1 is scheduled to receive a power supply potential from the external terminal VDD1 and the external terminal VDD2 and a ground potential from the external terminal VSS1 and the external terminal VSS2.

  The circuit 10 includes an internal circuit 11. The internal circuit 11 includes a circuit element such as a transistor, and functions during normal operation upon receiving a power supply voltage.

  The circuit 10 may include an electrostatic discharge protection circuit 12. The electrostatic discharge protection circuit 12 is a protection circuit that serves as a discharge path for electric charges due to input static electricity between the external terminal VDD1 and the external terminal VSS1, and protects the circuit elements included in the internal circuit 11 from electrostatic discharge destruction. It is provided for protection.

  The circuit 10 includes a potential wiring 13 that is to be connected to the first potential. In the example shown in FIG. 1, the first potential is a ground potential supplied from the external terminal VSS1.

  The circuit 20 includes an internal circuit 21. The internal circuit 21 includes a circuit element such as a transistor and functions during normal operation upon receiving a power supply voltage.

  The circuit 20 may include an electrostatic discharge protection circuit 22. The electrostatic discharge protection circuit 22 is a protection circuit that serves as a discharge path for electric charges due to input static electricity between the external terminal VDD2 and the external terminal VSS2, and the circuit elements included in the internal circuit 21 are protected from electrostatic discharge destruction. It is provided for protection.

  The circuit 20 includes a potential wiring 23 that is to be connected to the first potential. In the example shown in FIG. 1, the first potential is a ground potential supplied from the external terminal VSS2.

  The electrostatic discharge protection circuit 30 is a protection circuit that serves as a discharge path of charges due to input static electricity between, for example, the external terminal VSS1 and the external terminal VSS2, and includes circuit elements included in the internal circuit 11 and the internal circuit 21. It is provided to protect against electrostatic discharge breakdown. That is, when the circuit 10 and the circuit 20 are operating normally, it can be considered that the potential wiring 13 and the potential wiring 23 are electrically separated.

  In the example illustrated in FIG. 1, the electrostatic discharge protection circuit 30 includes a diode 31 and a diode 32 having different directions in parallel. One or a plurality of diodes may be further provided in series on the diode 31 side path and the diode 32 side path, respectively.

  FIG. 2 is a schematic diagram for explaining a cross-sectional structure of the semiconductor device according to the first embodiment. Of the circuit elements shown in the circuit diagram of FIG. 1, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the external terminal VDD1, and the external terminal VDD2 are not shown. Yes. FIG. 2 shows a cross-sectional structure of the stacked body 100 that is a part of the semiconductor device 1 according to the first embodiment.

  The semiconductor device 1 according to the first embodiment includes a semiconductor substrate 40 and a semiconductor substrate 50 that are stacked. The semiconductor substrate 40 electrically connects a semiconductor layer 41 in which circuit elements (transistors, diodes, etc.) included in the circuit 10 and the electrostatic discharge protection circuit 30 are formed, and circuit elements and through electrodes (details will be described later). For example, the wiring layer 42 is formed. The semiconductor substrate 50 includes a semiconductor layer 51 in which circuit elements (transistors, diodes, etc.) included in the circuit 20 are formed, and a wiring layer 52 in which wiring is formed. The wiring is formed of a metal such as aluminum or copper. Further, the wiring may be formed in a plurality of layers and electrically connected to each other through via holes.

  In the example shown in FIG. 2, the electrostatic discharge protection circuit 30 and circuit elements of the circuit 10 (not shown) are formed on the semiconductor layer 41 of the semiconductor substrate 40, and the potential wiring 13 and the wiring 60 are formed on the wiring layer 42. Yes. Further, circuit elements of the circuit 20 (not shown) are formed in the semiconductor layer 51 of the semiconductor substrate 50, and the potential wiring 23 is formed in the wiring layer 52.

  In the example illustrated in FIG. 2, the semiconductor device 1 includes an electrode 71 and an electrode 72 configured as a through electrode. The potential wiring 13 is electrically connected to the external terminal VSS1 through the electrode 71. The potential wiring 23 is electrically connected to the external terminal VSS2 through the electrode 72.

  The semiconductor device 1 according to the first embodiment includes a through electrode 61. The through electrode 61 penetrates the semiconductor substrate 40 and functions as a part of an electrical path.

  The through electrode may be formed after stacking the semiconductor substrates. Further, as illustrated in a schematic diagram for explaining an example of the configuration of the through electrode shown in FIG. 3, the through electrode is formed separately for each semiconductor substrate as 61a and 61b, and the semiconductor substrates are stacked. You may comprise so that it may be electrically connected.

  The wiring layer 52 of the semiconductor substrate 50 and the semiconductor layer 41 of the semiconductor substrate 40 may be bonded with an adhesive 70.

  In the semiconductor device 1 according to the first embodiment, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are electrically connected to each other via the through electrode 61 and the electrostatic discharge protection circuit 30. ing. In the example shown in FIG. 2, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are electrically connected to each other via the electrostatic discharge protection circuit 30, the wiring 60, and the through electrode 61. .

  According to the semiconductor device 1 according to the first embodiment, when an electrostatic voltage is applied between the electrically isolated potential wiring 13 and the potential wiring 23, the through electrode 61 and the electrostatic discharge protection circuit 30 is a discharge path. Thereby, the electrostatic discharge destruction of the circuit element contained in the circuit 10 or the circuit 20 can be suppressed.

  In the semiconductor device 1 according to the first embodiment, the electrostatic discharge protection circuit 30 that is a part of the electrical path between the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 is provided with the circuit 10. The semiconductor substrate 40 is provided.

  The circuit elements constituting the electrostatic discharge protection circuit 30 are difficult to miniaturize. Therefore, even if manufactured by a miniaturized manufacturing process, the influence on the area of the circuit element is small. Therefore, when the semiconductor substrate 40 is a semiconductor substrate manufactured by a manufacturing process that is least refined among the plurality of semiconductor substrates constituting the semiconductor device 1, the electrostatic discharge protection circuit 30 is provided on the semiconductor substrate 40. By providing the manufacturing cost can be reduced.

  Further, the electrostatic discharge protection circuit 30 can be provided on the semiconductor substrate 40 even when the semiconductor substrate 40 has a larger area than the semiconductor substrate 50.

  4A and 4B are schematic views for explaining a cross-sectional structure of the semiconductor device according to the first embodiment. FIG. 4A shows an example of a configuration in which the stacked body 100 described with reference to FIG. 1 is placed face up on the package substrate 80 and molded with a mold resin 81. FIG. 4B shows an example of a configuration in which the stacked body 100 described with reference to FIG. 2 is placed face down on the package substrate 80 and molded with a mold resin 81.

  4A and 4B, as in FIG. 2, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the external terminal VDD1, and the external terminal Illustration of VDD2 is omitted.

  In the example shown in FIG. 4A, the package substrate 80 is provided with external terminals VDD1 and VSS2, and the electrode 71 and the external terminals VSS1 and 72 are connected to the outside through wiring and bonding wires inside the package substrate 80. The terminals VSS2 are electrically connected to each other.

  In the example shown in FIG. 4B, the package substrate 80 is provided with external terminals VSS1 and VSS2, and the electrode 71 and the external terminal VSS1, and the electrode 72 and the external terminal VSS2 are connected via wiring inside the package substrate 80. Are electrically connected to each other.

2. Second Embodiment FIG. 5 is a schematic diagram for explaining a cross-sectional structure of a semiconductor device according to a second embodiment. The circuit diagram of the semiconductor device according to the second embodiment is the same as the circuit diagram shown in FIG. 1 as the semiconductor device according to the first embodiment. Of the circuit elements shown in the circuit diagram of FIG. 1, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the external terminal VDD1, and the external terminal VDD2 are not shown. Yes. FIG. 5 shows a cross-sectional structure of the stacked body 200 that is a part of the semiconductor device 2 according to the second embodiment.

  The semiconductor device 2 according to the second embodiment includes a semiconductor substrate 40 and a semiconductor substrate 50 that are stacked. The semiconductor substrate 40 includes a semiconductor layer 41 in which circuit elements (transistors, diodes, etc.) included in the circuit 10 and the circuit 20 are formed, and a wiring layer in which wiring for electrically connecting the circuit elements and the through electrodes is formed. 42 is comprised. The semiconductor substrate 50 includes a semiconductor layer 51 in which circuit elements (transistors, diodes, etc.) included in the electrostatic discharge protection circuit 30 are formed, and a wiring layer 52 in which wiring is formed.

  In the example shown in FIG. 5, circuit elements of the circuit 10 and the circuit 20 (both not shown) are formed in the semiconductor layer 41 of the semiconductor substrate 40, and the potential wiring 13 and the potential wiring 23 are formed in the wiring layer 42. Further, the circuit element of the electrostatic discharge protection circuit 30 is formed on the semiconductor layer 51 of the semiconductor substrate 50, and the wiring 60-1 and the wiring 60-2 are formed on the wiring layer 52.

  In the example shown in FIG. 5, the semiconductor device 2 includes electrodes 71 and 72. The potential wiring 13 is electrically connected to the external terminal VSS1 through the electrode 71. The potential wiring 23 is electrically connected to the external terminal VSS2 through the electrode 72.

  The semiconductor device 2 according to the second embodiment is configured to include through electrodes 61 and 62. The through electrodes 61 and 62 penetrate the semiconductor substrate 40 and function as part of an electrical path.

  In the semiconductor device 2 according to the second embodiment, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are electrically connected to each other via the through electrodes 61 and 62 and the electrostatic discharge protection circuit 30. It is connected. In the example shown in FIG. 5, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are connected through the through electrode 61, the wiring 60-1, the electrostatic discharge protection circuit 30, the wiring 60-2, and the through electrode 62. Are electrically connected to each other.

  According to the semiconductor device 2 of the second embodiment, when an electrostatic voltage is applied between the electrically isolated potential wiring 13 and the potential wiring 23, the through electrodes 61 and 62 and the electrostatic discharge The protection circuit 30 serves as a discharge path. Thereby, the electrostatic discharge destruction of the circuit element contained in the circuit 10 or the circuit 20 can be suppressed.

  In the semiconductor device 2 according to the second embodiment, the electrostatic discharge protection circuit 30 that is a part of the electrical path between the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 is the circuit 10 or circuit 20. Is provided on the semiconductor substrate 50 not provided with.

  When the semiconductor substrate 50 is a semiconductor substrate manufactured by a manufacturing process that is least refined among a plurality of semiconductor substrates constituting the semiconductor device 2, the electrostatic discharge protection circuit 30 is provided on the semiconductor substrate 50. As a result, the manufacturing cost can be reduced.

  Further, the electrostatic discharge protection circuit 30 can be provided on the semiconductor substrate 50 even when the semiconductor substrate 50 has a larger area than the semiconductor substrate 40.

  Note that the semiconductor device 2 according to the second embodiment has a configuration in which the stacked body 100 is replaced with the stacked body 200 in FIGS. 4A and 4B.

3. Third Embodiment FIG. 6 is a schematic view for explaining a cross-sectional structure of a semiconductor device according to a third embodiment. The circuit diagram of the semiconductor device according to the third embodiment is the same as the circuit diagram shown in FIG. 1 as the semiconductor device according to the first embodiment. Of the circuit elements shown in the circuit diagram of FIG. 1, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the external terminal VDD1, and the external terminal VDD2 are not shown. Yes. FIG. 6 shows a cross-sectional structure of the stacked body 300 that is a part of the semiconductor device 3 according to the third embodiment.

  The semiconductor device 3 according to the third embodiment includes a semiconductor substrate 40 and a semiconductor substrate 50 that are stacked. The semiconductor substrate 40 includes a semiconductor layer 41 on which circuit elements (transistors, diodes, and the like) included in the circuit 10 and the electrostatic discharge protection circuit 30 are formed, and wiring for electrically connecting the circuit elements and the through electrodes. The wiring layer 42 is configured to be included. The semiconductor substrate 50 includes a semiconductor layer 51 in which circuit elements (transistors, diodes, etc.) included in the circuit 20 and the electrostatic discharge protection circuit 30 are formed, and a wiring layer 52 in which wiring is formed.

  In the example shown in FIG. 6, a circuit element of the circuit 10 (not shown) and a diode 31 which is a circuit element that becomes a part of the electrostatic discharge protection circuit 30 are formed on the semiconductor layer 41 of the semiconductor substrate 40. A potential wiring 13 and a wiring 60-4 are formed at 42. In addition, a circuit element of the circuit 20 (not shown) and a diode 32 which is a part of the electrostatic discharge protection circuit 30 are formed on the semiconductor layer 51 of the semiconductor substrate 50, and the potential wiring 23 is formed on the wiring layer 52. Wiring 60-3 is formed.

  In the example illustrated in FIG. 6, the semiconductor device 3 includes an electrode 71 and an electrode 72 configured as a through electrode. The potential wiring 13 is electrically connected to the external terminal VSS1 through the electrode 71. The potential wiring 23 is electrically connected to the external terminal VSS2 through the electrode 72. In the example shown in FIG. 6, the electrode 71 and the electrode 72 are shifted in a direction perpendicular to the plane of FIG. 6 (the electrode 71 is relatively on the near side and the electrode 72 is relatively on the far side). Are electrically separated.

  The semiconductor device 3 according to the third embodiment is configured to include through electrodes 61 and 62. The through electrodes 61 and 62 penetrate the semiconductor substrate 40 and function as part of an electrical path.

  In the semiconductor device 3 according to the third embodiment, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are a diode 31 and a through electrode 61 that are circuit elements that are part of the electrostatic discharge protection circuit 30. Are electrically connected to each other by an electrical path via a diode 32 and a through electrode 62 which are circuit elements that are part of the electrostatic discharge protection circuit 30. In the example shown in FIG. 6, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are electrically connected to the diode 31, the wiring 60-4, the through electrode 61, the through electrode 62, and the wiring 60 −. 3. They are electrically connected to each other through an electrical path via the diode 32.

  According to the semiconductor device 3 according to the third embodiment, when an electrostatic voltage is applied between the electrically isolated potential wiring 13 and the potential wiring 23, the through electrodes 61 and 62 and the electrostatic discharge The diodes 31 and 32 that are part of the protection circuit 30 serve as a discharge path. Thereby, the electrostatic discharge destruction of the circuit element contained in the circuit 10 or the circuit 20 can be suppressed.

  Note that the semiconductor device 3 according to the third embodiment has a configuration in which the stacked body 100 is replaced with the stacked body 300 in FIGS. 4A and 4B.

4). Fourth Embodiment FIG. 7 is a circuit diagram of a semiconductor device according to a fourth embodiment. Compared to the circuit diagram of the semiconductor device according to the first embodiment shown in FIG. 1, only the configuration of the electrostatic discharge protection circuit 30 is different. In the circuit diagram shown in FIG. 7, the electrostatic discharge protection circuit 30 is configured by connecting a series connection group of diodes 31 and 33 and a series connection group of diodes 32 and 34 in parallel with each other in different directions. Yes.

  FIG. 8 is a schematic view for explaining a cross-sectional structure of the semiconductor device according to the fourth embodiment. Of the circuit elements shown in the circuit diagram of FIG. 7, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the external terminal VDD1, and the external terminal VDD2 are not shown. Yes. FIG. 8 shows a cross-sectional structure of the stacked body 400 that is a part of the semiconductor device 4 according to the fourth embodiment.

  The semiconductor device 4 according to the fourth embodiment is configured to include a semiconductor substrate 40 and a semiconductor substrate 50 which are stacked. The semiconductor substrate 40 includes a semiconductor layer 41 on which circuit elements (transistors, diodes, and the like) included in the circuit 10 and the electrostatic discharge protection circuit 30 are formed, and wiring for electrically connecting the circuit elements and the through electrodes. The wiring layer 42 is configured to be included. The semiconductor substrate 50 includes a semiconductor layer 51 in which circuit elements (transistors, diodes, etc.) included in the circuit 20 and the electrostatic discharge protection circuit 30 are formed, and a wiring layer 52 in which wiring is formed.

  In the example shown in FIG. 8, circuit elements of the circuit 10 (not shown) and diodes 31 and 34 that are part of the electrostatic discharge protection circuit 30 are formed on the semiconductor layer 41 of the semiconductor substrate 40. In the wiring layer 42, the potential wiring 13 and the wirings 60-5 and 60-7 are formed. Further, circuit elements of the circuit 20 (not shown) and diodes 32 and 33 which are part of the electrostatic discharge protection circuit 30 are formed on the semiconductor layer 51 of the semiconductor substrate 50, and the potential is applied to the wiring layer 52. A wiring 23 and wirings 60-6 and 60-8 are formed.

  In the example illustrated in FIG. 8, the semiconductor device 4 includes an electrode 71 and an electrode 72 configured as a through electrode. The potential wiring 13 is electrically connected to the external terminal VSS1 through the electrode 71. The potential wiring 23 is electrically connected to the external terminal VSS2 through the electrode 72. In the example shown in FIG. 8, the electrode 71 and the electrode 72 are provided so as to be shifted in a direction perpendicular to the plane of FIG. 8 (the electrode 71 is relatively on the near side and the electrode 72 is relatively on the far side). Are electrically separated.

  The semiconductor device 4 according to the fourth embodiment is configured to include through electrodes 61 and 62. The through electrodes 61 and 62 penetrate the semiconductor substrate 40 and function as part of an electrical path.

  In the semiconductor device 4 according to the fourth embodiment, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 and the diodes 31 and 33 that are part of the electrostatic discharge protection circuit 30 and the through-holes are penetrated. The electrical path through the electrode 61 and the electrical path through the diodes 32 and 34 that are part of the electrostatic discharge protection circuit 30 and the through electrode 62 are electrically connected to each other. ing. Each electrical path includes a circuit element that is a part of the electrostatic discharge protection circuit 30 and is provided on a different semiconductor substrate.

  In the example shown in FIG. 8, the potential wiring 13 of the circuit 10 and the potential wiring 23 of the circuit 20 are electrically connected via the diode 31, the wiring 60-5, the through electrode 61, the wiring 60-6, and the diode 33 ( The first electrical path) and the electrical path (second electrical path) via the diode 34, the wiring 60-7, the through electrode 62, the wiring 60-8, and the diode 32 are electrically connected to each other. Has been.

  The first electrical path includes diodes 31 and 34 that are part of the electrostatic discharge protection circuit 30 and are provided on different semiconductor substrates. The second electrical path is an electrostatic discharge circuit. It comprises diodes 32 and 33 which are part of the discharge protection circuit 30 and are circuit elements provided on different semiconductor substrates.

  According to the semiconductor device 4 according to the fourth embodiment, when an electrostatic voltage is applied between the electrically isolated potential wiring 13 and the potential wiring 23, the through electrodes 61 and 62 and the electrostatic discharge The diodes 31, 32, 33, and 34, which are part of the protection circuit 30, serve as a discharge path. Thereby, the electrostatic discharge destruction of the circuit element contained in the circuit 10 or the circuit 20 can be suppressed.

  In addition, the semiconductor substrate 40 and the semiconductor substrate 50 can share the layout of the diodes 31, 32, 33, and 34 that are part of the electrostatic discharge protection circuit 30.

  Note that the semiconductor device 4 according to the fourth embodiment has a configuration in which the stacked body 100 is replaced with the stacked body 400 in FIGS. 4A and 4B.

5). Fifth Embodiment FIG. 9 is a circuit diagram of a semiconductor device according to a fifth embodiment.

  A semiconductor device 5 according to the fifth embodiment includes circuits 10, 20, 90 and electrostatic discharge protection circuits 110, 120, 130. In addition, the semiconductor device 5 is scheduled to receive a power supply potential from the external terminals VDD1, VDD2, and VDD3 and a ground potential from the external terminals VSS1, VSS2, and VSS3.

  The circuit 10 includes an internal circuit 11. The internal circuit 11 includes a circuit element such as a transistor, and functions during normal operation upon receiving a power supply voltage.

  The circuit 10 may include an electrostatic discharge protection circuit 12. The electrostatic discharge protection circuit 12 is a protection circuit that serves as a discharge path for electric charges due to input static electricity between the external terminal VDD1 and the external terminal VSS1, and protects the circuit elements included in the internal circuit 11 from electrostatic discharge destruction. It is provided for protection.

  The circuit 10 includes a potential wiring 13 that is to be connected to the first potential. In the example shown in FIG. 9, the first potential is a ground potential supplied from the external terminal VSS1.

  The circuit 20 includes an internal circuit 21. The internal circuit 21 includes a circuit element such as a transistor and functions during normal operation upon receiving a power supply voltage.

  The circuit 20 may include an electrostatic discharge protection circuit 22. The electrostatic discharge protection circuit 22 is a protection circuit that serves as a discharge path for electric charges due to input static electricity between the external terminal VDD2 and the external terminal VSS2, and the circuit elements included in the internal circuit 21 are protected from electrostatic discharge destruction. It is provided for protection.

  The circuit 20 includes a potential wiring 23 that is to be connected to the first potential. In the example shown in FIG. 9, the first potential is a ground potential supplied from the external terminal VSS2.

  The circuit 90 includes an internal circuit 91. The internal circuit 91 is configured to include circuit elements such as transistors, and functions during normal operation upon receiving power supply voltage.

  The circuit 90 may include an electrostatic discharge protection circuit 92. The electrostatic discharge protection circuit 92 is a protection circuit that serves as a discharge path for charges caused by static electricity inputted between the external terminal VDD3 and the external terminal VSS3. The circuit element included in the internal circuit 91 is protected from electrostatic discharge destruction. It is provided for protection.

  The circuit 90 includes a potential wiring 93 that is to be connected to the first potential. In the example shown in FIG. 9, the first potential is the ground potential supplied from the external terminal VSS3.

  The electrostatic discharge protection circuits 110, 120, and 130 are input, for example, between the external terminal VSS1 and the external terminal VSS2, between the external terminal VSS1 and the external terminal VSS3, between the external terminal VSS2 and the external terminal VSS3, and the like. This is a protection circuit serving as a discharge path for charges due to static electricity, and is provided to protect circuit elements included in the internal circuits 11, 21, 91 from electrostatic discharge breakdown. That is, when the circuits 10, 20, and 90 are operating normally, it can be considered that the potential wirings 13, 23, and 93 are electrically separated from each other.

  In the example illustrated in FIG. 9, the electrostatic discharge protection circuit 110 includes a diode 111 and a diode 112 having different directions in parallel. Similarly, the electrostatic discharge protection circuit 120 includes a diode 121 and a diode 122 having different directions in parallel, and the electrostatic discharge protection circuit 130 has a diode 131 and a diode 132 having different directions in parallel. It is configured to include.

  One end of the electrostatic discharge protection circuit 110 is connected to the potential wiring 13, one end of the electrostatic discharge protection circuit 120 is connected to the potential wiring 23, and one end of the electrostatic discharge protection circuit 130 is connected to the potential wiring 93. Yes. Further, the other ends of the electrostatic discharge protection circuits 110, 120, and 130 are connected to each other through a common wiring 140.

  Note that one or more diodes may be further provided in series on the diode 111 side path and the diode 112 side path, respectively. Similarly, one or more diodes may be further provided in series in the diode 121 side path and the diode 122 side path, respectively, and one or more diodes may be provided in the diode 131 side path and the diode 132 side path, respectively. A diode may be further provided in series.

  FIG. 10 is a schematic diagram for explaining a cross-sectional structure of a semiconductor device according to the fifth embodiment. Among the circuit elements shown in the circuit diagram of FIG. 9, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the internal circuit 91, the electrostatic discharge protection circuit 92, and the external terminal VDD1 The external terminal VDD2 and the external terminal VDD3 are not shown. FIG. 10 shows a cross-sectional structure of the stacked body 500 that is a part of the semiconductor device 5 according to the fifth embodiment.

  The semiconductor device 5 according to the fifth embodiment includes a semiconductor substrate 40, a semiconductor substrate 50, and a semiconductor substrate 150 that are stacked. The semiconductor substrate 40 includes a semiconductor layer 41 on which circuit elements (transistors, diodes, etc.) included in the circuit 10 and the electrostatic discharge protection circuit 110 are formed, and wiring for electrically connecting the circuit elements and the through electrodes. The wiring layer 42 is configured to be included. The semiconductor substrate 50 includes a semiconductor layer 51 in which circuit elements (transistors, diodes, etc.) included in the circuit 20 and the electrostatic discharge protection circuit 120 are formed, and a wiring layer 52 in which wiring is formed. The semiconductor substrate 150 includes a semiconductor layer 151 in which circuit elements (transistors, diodes, etc.) included in the circuit 90 and the electrostatic discharge protection circuit 130 are formed, and a wiring layer 152 in which wiring is formed.

  In the example shown in FIG. 10, the circuit 10 (not shown) and circuit elements of the electrostatic discharge protection circuit 110 are formed in the semiconductor layer 41 of the semiconductor substrate 40, and the potential wiring 13 and the wiring 60-9 are formed in the wiring layer 42. Has been. Further, a circuit 20 (not shown) and circuit elements of the electrostatic discharge protection circuit 120 are formed on the semiconductor layer 51 of the semiconductor substrate 50, and a potential wiring 23 and a wiring 60-10 are formed on the wiring layer 52. Further, a circuit 90 (not shown) and circuit elements of the electrostatic discharge protection circuit 130 are formed on the semiconductor layer 151 of the semiconductor substrate 150, and a potential wiring 93 and a wiring 60-11 are formed on the wiring layer 152.

  In the example shown in FIG. 10, the semiconductor device 5 includes an electrode 71 and electrodes 72 and 73 configured as through electrodes. The potential wiring 13 is electrically connected to the external terminal VSS1 through the electrode 71. The potential wiring 23 is electrically connected to the external terminal VSS2 through the electrode 72. The potential wiring 93 is electrically connected to the external terminal VSS3 through the electrode 73.

  The semiconductor device 5 according to the fifth embodiment includes a through electrode 61. The through electrode 61 penetrates the semiconductor substrate 40 and functions as a part of an electrical path. Further, the through electrode 61 functions as a part of the common wiring 140 in the circuit diagram of FIG.

  In the semiconductor device 5 according to the fifth embodiment, the potential wiring 13 of the circuit 10 is connected to the potential of the circuit 90 via the electrostatic discharge protection circuit 110, and the potential wiring 23 of the circuit 20 is connected to the potential of the circuit 90 via the electrostatic discharge protection circuit 120. The wiring 93 is electrically connected to the through electrode 61 via the electrostatic discharge protection circuit 130.

  In the example shown in FIG. 10, the potential wiring 13 of the circuit 10 is connected to the electrostatic discharge protection circuit 110 and the wiring 60-9, and the potential wiring 23 of the circuit 20 is connected to the electrostatic discharge protection circuit 120 and the wiring 60-10. Accordingly, the potential wiring 93 of the circuit 90 is electrically connected to the through electrode 61 via the electrostatic discharge protection circuit 130 and the wiring 60-11.

  According to the semiconductor device 5 according to the fifth embodiment, when an electrostatic voltage is applied between any two of the electrically separated potential wiring 13, the potential wiring 23, and the potential wiring 93, The electrostatic discharge protection circuit corresponding to each potential wiring and the through electrode 61 serve as a discharge path. Thereby, the electrostatic discharge destruction of the circuit element contained in the circuits 10, 20, 90 can be suppressed.

  Further, according to the semiconductor device 5 of the fifth embodiment, even if the number of electrically separated circuits increases, it is only necessary to prepare the same number of electrostatic discharge protection circuits as the number of circuits. Electric discharge breakdown can be suppressed.

  FIG. 11A and FIG. 11B are schematic views for explaining a cross-sectional structure of a semiconductor device according to the fifth embodiment. FIG. 11A shows an example of a configuration in which the stacked body 500 described with reference to FIG. 10 is placed face up on the package substrate 80 and molded with a mold resin 81. FIG. 4B shows an example of a configuration in which the stacked body 500 described with reference to FIG. 10 is placed face down on the package substrate 80 and molded with the mold resin 81.

  11A and 11B, as in FIG. 10, the internal circuit 11, the electrostatic discharge protection circuit 12, the internal circuit 21, the electrostatic discharge protection circuit 22, the internal circuit 91, the electrostatic circuit The discharge protection circuit 92, the external terminal VDD1, the external terminal VDD2, and the external terminal VDD3 are not shown.

  In the example shown in FIG. 4A, the package substrate 80 is provided with external terminals VSS1, VSS2, and VSS3. The electrode 71, the external terminal VSS1, and the electrode 72 are provided via wiring and bonding wires inside the package substrate 80. And the external terminal VSS2, the electrode 73 and the external terminal VSS3 are electrically connected to each other.

  In the example shown in FIG. 4B, the package substrate 80 is provided with external terminals VSS1, VSS2, and VSS3. The electrode 71, the external terminal VSS1, the electrode 72, and the external terminal are provided via wiring inside the package substrate 80. VSS2, the electrode 73, and the external terminal VSS3 are electrically connected to each other.

  In addition, this invention is not limited to this Embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

  For example, in the description of each embodiment, only the external terminals connected to each potential wiring have been described, but other input terminals, output terminals, control terminals, and other external terminals may be included.

  In each embodiment, three or more semiconductor substrates can be stacked.

1 is a circuit diagram of a semiconductor device according to a first embodiment. FIG. 3 is a schematic diagram for explaining a cross-sectional structure of the semiconductor device according to the first embodiment. The schematic diagram for demonstrating an example of a structure of a penetration electrode. 4A and 4B are schematic views for explaining a cross-sectional structure of the semiconductor device according to the first embodiment. The schematic diagram for demonstrating the cross-section of the semiconductor device which concerns on 2nd Embodiment. The schematic diagram for demonstrating the cross-section of the semiconductor device which concerns on 3rd Embodiment. The circuit diagram of the semiconductor device concerning a 4th embodiment. The schematic diagram for demonstrating the cross-section of the semiconductor device which concerns on 4th Embodiment. The circuit diagram of the semiconductor device concerning a 5th embodiment. The schematic diagram for demonstrating the cross-section of the semiconductor device which concerns on 5th Embodiment. FIG. 11A and FIG. 11B are schematic views for explaining a cross-sectional structure of a semiconductor device according to the fifth embodiment.

Explanation of symbols

1, 2 Semiconductor device, 10 circuit, 11 internal circuit, 12 electrostatic discharge protection circuit, 13 potential wiring, 20 circuit, 21 internal circuit, 22 electrostatic discharge protection circuit, 23 potential wiring, 30 electrostatic discharge protection circuit, 31 , 32, 33, 34 Diode, 40 Semiconductor substrate, 41 Semiconductor layer, 42 Wiring layer, 50 Semiconductor substrate, 51 Semiconductor layer, 52 Wiring layer, 60, 60-1, 60-2, 60-3, 60-4, 60-5, 60-6, 60-7, 60-8 wiring, 61, 62 through electrode, 70 adhesive, 71, 72, 73 electrode, 80 package substrate, 81 mold resin, 90 circuit, 91 internal circuit, 92 Electrostatic discharge protection circuit, 93 potential wiring, 100 laminated body, 110 electrostatic discharge protection circuit, 111, 112 diode, 120 electrostatic discharge protection circuit, 121, 122 da Iode, 130 ESD protection circuit, 131, 132 diode, 140 common wiring, 151 semiconductor layer, 152 wiring layer, 200, 300, 400, 500 laminate, VDD1, VDD2, VDD3, VSS1, VSS2, VSS3 External terminal

Claims (11)

A semiconductor device including a plurality of stacked semiconductor substrates,
A through electrode penetrating a given semiconductor substrate among the plurality of semiconductor substrates; and
A plurality of circuits including a potential wiring to be connected to the first potential;
Including an electrostatic discharge protection circuit,
The plurality of circuits are provided on different semiconductor substrates,
The potential wiring of one circuit of the plurality of circuits and the potential wiring of another circuit of the plurality of circuits are electrically connected to each other via the through electrode and the electrostatic discharge protection circuit. A semiconductor device characterized by being connected to each other. The semiconductor device according to claim 1,
The electrostatic discharge protection circuit that is a part of an electrical path between the potential wiring of one circuit of the plurality of circuits and the potential wiring of another circuit of the plurality of circuits is the plurality of A semiconductor device provided on the semiconductor substrate on which one of the circuits is provided. A semiconductor device including a plurality of stacked semiconductor substrates,
A through electrode penetrating a given semiconductor substrate among the plurality of semiconductor substrates; and
A plurality of circuits including a potential wiring to be connected to the first potential;
Including an electrostatic discharge protection circuit,
The plurality of circuits and the electrostatic discharge protection circuit are provided on the different semiconductor substrates,
The potential wiring of one circuit of the plurality of circuits and the potential wiring of another circuit of the plurality of circuits are electrically connected to each other via the through electrode and the electrostatic discharge protection circuit. A semiconductor device characterized by being connected to each other. The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the electrostatic discharge protection circuit is provided on a semiconductor substrate manufactured by a manufacturing process that is least refined among the plurality of semiconductor substrates. The semiconductor device according to claim 1,
Including a plurality of through electrodes,
The potential wiring of one circuit of the plurality of circuits and the potential wiring of another circuit of the plurality of circuits are different from circuit elements that are part of the electrostatic discharge protection circuit, respectively. A semiconductor device characterized by being connected by a plurality of electrical paths through a through electrode. The semiconductor device according to claim 5,
Each of the plurality of electrical paths is a part of the electrostatic discharge protection circuit, and includes a circuit element provided on each of the different semiconductor substrates. The semiconductor device according to claim 1,
Including three or more circuits including a potential wiring connected to the first potential;
The three or more circuits are provided on the different semiconductor substrates,
The potential wiring of each of the three or more circuits is electrically connected to the through electrode via the electrostatic discharge protection circuit corresponding to each of the three or more circuits. apparatus. The semiconductor device according to claim 1,
The electrostatic discharge protection circuit is configured to include parallel diodes having different directions. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first potential is a ground potential. Laminating multiple semiconductor substrates,
A through electrode penetrating a given semiconductor substrate among the plurality of semiconductor substrates; and
A plurality of circuits including a potential wiring to be connected to the first potential;
A method of manufacturing a semiconductor device including an electrostatic discharge protection circuit,
The plurality of circuits are provided on the different semiconductor substrates, and the potential wiring of one circuit of the plurality of circuits and the potential wiring of another circuit of the plurality of circuits are connected to the through electrode. And a method for manufacturing a semiconductor device, wherein the electrostatic discharge protection circuit is electrically connected to each other. Laminating multiple semiconductor substrates,
A through electrode penetrating a given semiconductor substrate among the plurality of semiconductor substrates; and
A plurality of circuits including a potential wiring to be connected to the first potential;
A method of manufacturing a semiconductor device including an electrostatic discharge protection circuit,
The plurality of circuits and the electrostatic discharge protection circuit are provided on the different semiconductor substrates, the potential wiring of one circuit of the plurality of circuits, and another circuit of the plurality of circuits A method of manufacturing a semiconductor device, wherein the potential wiring is electrically connected to each other through the through electrode and the electrostatic discharge protection circuit.

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