JP2008182285A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2008182285A
JP2008182285A JP2008113107A JP2008113107A JP2008182285A JP 2008182285 A JP2008182285 A JP 2008182285A JP 2008113107 A JP2008113107 A JP 2008113107A JP 2008113107 A JP2008113107 A JP 2008113107A JP 2008182285 A JP2008182285 A JP 2008182285A
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circuit board
semiconductor device
connection
semiconductor
semiconductor element
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JP4652428B2 (en
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Tomoyo Maruyama
朋代 丸山
Yuji Yano
祐司 矢野
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Sharp Corp
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
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    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a small and low-profile semiconductor device having less restrictions on an arrangement of external connection terminals used for connecting the semiconductor device and electronic component stacked on an upper stage, capable of improving packaging density, and having an excellent heat dissipation property. <P>SOLUTION: On a circuit substrate 12, a semiconductor element 11 is mounted via a bonding agent 13. On the upper face of the semiconductor element 11, a circuit substrate 15 for connection having external terminal connection parts 17 is mounted via a bonding agent 16 and the lower face of the circuit substrate 15 for connection and upper face of the circuit substrate 12 are connected with conductor terminals 18. Between the circuit substrate 12 and circuit substrate 15 for connection, sealing is performed by sealing resin 19. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体素子を搭載した半導体装置、複数の半導体装置を積層してなる半導体装置の積層体、および、その製造方法に関するものである。   The present invention relates to a semiconductor device on which a semiconductor element is mounted, a stacked body of semiconductor devices formed by stacking a plurality of semiconductor devices, and a method for manufacturing the same.

電子機器の小型化、軽量化かつ高機能化が進むに伴い、半導体装置の高密度実装化が要求されている。これらの要求に応えるため、１つの半導体装置に複数の半導体素子を搭載した半導体装置が発明されている。これにより、実装基板単位面積あたりの半導体素子実装密度が増加される。   As electronic devices become smaller, lighter, and more advanced, semiconductor devices are required to be mounted at higher density. In order to meet these requirements, a semiconductor device in which a plurality of semiconductor elements are mounted on one semiconductor device has been invented. Thereby, the semiconductor element mounting density per mounting board unit area is increased.

しかしながら、１つの半導体装置に半導体素子を多数個搭載するには、製造技術上または製品信頼性上の限界がある。   However, in order to mount a large number of semiconductor elements in one semiconductor device, there is a limit on manufacturing technology or product reliability.

多数個または多品種の半導体素子を１つの半導体装置に搭載するためには、回路基板における配線密度の増加といった問題がある。具体的には、回路基板の多層配線化や、ワイヤボンドやフリップチップボンドなどの半導体素子と回路基板との接続部の高密度化などを必要とし、電気的な接続が複雑になる。   In order to mount a large number or variety of semiconductor elements in one semiconductor device, there is a problem that the wiring density in the circuit board increases. Specifically, it is necessary to make the circuit board a multi-layered wiring and to increase the density of the connection part between the semiconductor element such as wire bond and flip chip bond and the circuit board, and the electrical connection becomes complicated.

また、１つの半導体装置に複数種類の半導体素子を搭載する場合には、該半導体装置が専用性の高いものとなり、半導体装置の汎用性が低くなるという問題もある。   In addition, when a plurality of types of semiconductor elements are mounted on one semiconductor device, the semiconductor device has a high degree of specialization, and there is a problem that versatility of the semiconductor device is reduced.

これらの問題を解決するために、特許文献１には、必要な全ての半導体素子を１つの半導体装置に搭載するのではなく、いくつかの半導体素子を１つの半導体装置に搭載し、その上に、同じもしくは別の半導体装置を積層し、その積層体を１つの半導体装置とする技術が開示されている。これにより、要求される実装密度を保ったまま、製造上および信頼性上の問題を解決し、また半導体装置の汎用性を確保できるようになった。   In order to solve these problems, Patent Document 1 discloses that not all necessary semiconductor elements are mounted in one semiconductor device, but several semiconductor elements are mounted in one semiconductor device, on which A technique is disclosed in which the same or different semiconductor devices are stacked and the stacked body is used as one semiconductor device. As a result, the manufacturing and reliability problems can be solved while maintaining the required mounting density, and the versatility of the semiconductor device can be secured.

図１０に、特許文献１による半導体装置の断面図を示す。特許文献１における従来技術では、半導体素子１０１を搭載している回路基板１０２にスルーホール１０３を設けることにより、回路基板１０２の表裏で導通をとれるようにしている。また、回路基板１０２の上面側（半導体素子１０１の搭載側）では、半導体素子１０１が回路基板１０２における接続用パッドの一部にワイヤボンディングによって接続され、半導体素子１０１およびボンディングワイヤが封止樹脂１０５にて封止されている。また、封止樹脂１０５は、回路基板１０２の上面全体を封止しておらず、外部端子接続部１０４を露出している。   FIG. 10 is a cross-sectional view of a semiconductor device according to Patent Document 1. In the prior art in Patent Document 1, the through-hole 103 is provided in the circuit board 102 on which the semiconductor element 101 is mounted, so that conduction can be established between the front and back of the circuit board 102. In addition, on the upper surface side of the circuit board 102 (the side on which the semiconductor element 101 is mounted), the semiconductor element 101 is connected to a part of the connection pad in the circuit board 102 by wire bonding, and the semiconductor element 101 and the bonding wire are sealed resin 105. It is sealed with. Further, the sealing resin 105 does not seal the entire upper surface of the circuit board 102 and exposes the external terminal connection portion 104.

図１１に、図１０に示す半導体装置を積層してなる積層体の断面図を示す。この積層体においては、図１０に示す半導体装置同士を積層し、回路基板１０２間を導電体１０６によって接続している。すなわち、導電体１０６は、下側の半導体装置において上面に露出された外部端子接続部１０４と、上側の半導体装置において下面で露出された裏面電極パッドとを接続することによって、積層した複数の半導体装置を電気的に接続している。上記裏面電極パッドは、外部端子接続部１０４とスルーホール１０３によって導通されている。   FIG. 11 is a cross-sectional view of a stacked body in which the semiconductor devices illustrated in FIG. 10 are stacked. In this stacked body, the semiconductor devices shown in FIG. 10 are stacked, and the circuit boards 102 are connected by a conductor 106. That is, the conductor 106 is formed by connecting a plurality of stacked semiconductors by connecting the external terminal connection portion 104 exposed on the upper surface of the lower semiconductor device and the back electrode pad exposed on the lower surface of the upper semiconductor device. The device is electrically connected. The back electrode pad is electrically connected to the external terminal connection portion 104 and the through hole 103.

特許文献１における発明では、半導体素子１０１と外部接続端子１０４とをつなぐ配線以外に、上下に積層される半導体装置同士を電気的に接続するための配線も必要となる。このため、回路基板１０２における配線が複雑になり、回路基板１０２が大きくなり、半導体装置の平面的な寸法が半導体素子１０１よりもかなり大きくなってしまうという問題があった。   In the invention in Patent Document 1, in addition to the wiring connecting the semiconductor element 101 and the external connection terminal 104, wiring for electrically connecting the semiconductor devices stacked one above the other is also required. For this reason, wiring on the circuit board 102 becomes complicated, the circuit board 102 becomes large, and the planar dimensions of the semiconductor device become considerably larger than the semiconductor element 101.

この問題を回避するものとして、特許文献２に示す従来技術が挙げられる。図１２に、特許文献２による半導体装置の断面図を示す。   As a technique for avoiding this problem, there is a conventional technique shown in Patent Document 2. FIG. 12 is a cross-sectional view of a semiconductor device according to Patent Document 2.

特許文献２における従来技術では、回路基板１１２上に半導体素子１１１を搭載して、これらをワイヤ１１３にて接続し、さらに、半導体素子１１１上に接続用回路基板１１４を接着材１１５を介して設けている。この接続用回路基板１１４は、図１２に示す半導体装置の上段に他の半導体装置を積層する場合に、上段に積層される半導体装置との電気的接続に用いられるものであり、接続用回路基板１１４には外部端子接続部１１６が設けられている。接続用回路基板１１４は、ワイヤ１１７によって回路基板１１２と接続される。   In the prior art in Patent Document 2, a semiconductor element 111 is mounted on a circuit board 112, these are connected by a wire 113, and a connection circuit board 114 is provided on the semiconductor element 111 via an adhesive 115. ing. This connection circuit board 114 is used for electrical connection with a semiconductor device stacked on the upper stage when another semiconductor device is stacked on the upper stage of the semiconductor device shown in FIG. 114 is provided with an external terminal connecting portion 116. The connection circuit board 114 is connected to the circuit board 112 by a wire 117.

また、ワイヤ１１３および１１７は、封止樹脂１１８によって封止されている。さらに、回路基板１１２の下面には外部接続端子１１９が設けられている。   The wires 113 and 117 are sealed with a sealing resin 118. Further, external connection terminals 119 are provided on the lower surface of the circuit board 112.

図１２に示す半導体装置では、上段に積層される半導体装置を電気的に接続するための配線を、回路基板１１２ではなく接続用回路基板１１４に設けることができる。このため、回路基板１１２および接続用回路基板１１４の両方における配線が複雑化することを防止でき、これによって両基板の平面的な寸法の増加を抑制し、半導体装置を小型化できる、という利点がある。
特開平４−２８０６９５号公報（公開日平成４年１０月６日） 特開２００４−１７２１５７号公報（公開日平成１６年６月１７日） In the semiconductor device illustrated in FIG. 12, wiring for electrically connecting the semiconductor devices stacked in the upper stage can be provided not on the circuit board 112 but on the connection circuit board 114. For this reason, it is possible to prevent the wiring on both the circuit board 112 and the connection circuit board 114 from becoming complicated, thereby suppressing an increase in planar dimensions of both the boards and reducing the size of the semiconductor device. is there.
JP-A-4-280695 (publication date: October 6, 1992) JP 2004-172157 A (publication date June 17, 2004)

しかしながら、特許文献２における従来技術では、接続用回路基板１１４と回路基板１１２との接続方法はワイヤ１１７によるワイヤボンディングとなっている。このため、接続用回路基板１１４上に、ワイヤ１１７のループ高さと、それを封止する封止樹脂１１８の高さとが必要になり、半導体装置の合計高さ、すなわち半導体装置の厚みが大きくなるといった問題がある。   However, in the prior art in Patent Document 2, the connection method between the circuit board for connection 114 and the circuit board 112 is wire bonding using a wire 117. For this reason, the loop height of the wire 117 and the height of the sealing resin 118 for sealing the wire 117 are required on the connection circuit board 114, and the total height of the semiconductor device, that is, the thickness of the semiconductor device is increased. There is a problem.

また、図１２に示す半導体装置では、半導体素子１１１と回路基板１１２との接続がワイヤボンディングであるため、接続用回路基板１１４はその下に位置する半導体素子１１１よりも平面寸法が小さいものに限定される。   Further, in the semiconductor device shown in FIG. 12, since the connection between the semiconductor element 111 and the circuit board 112 is wire bonding, the connection circuit board 114 is limited to a plane dimension smaller than that of the semiconductor element 111 located therebelow. Is done.

このことと、接続用回路基板１１４と回路基板１１２との接続方法はワイヤ１１７によるものであることとから、接続用回路基板１１４において外部端子接続部１１６を配置することができる平面的な領域が小さくなる。このため、接続用回路基板１１４上に配置できる外部端子接続部１１６の数や配置間隔に制限が生じ、実装密度を大きくできない、という問題がある。   Since the connection method between the circuit board 114 for connection and the circuit board 112 is based on the wire 117, there is a planar area in which the external terminal connection part 116 can be disposed on the circuit board 114 for connection. Get smaller. For this reason, there is a problem that the number of external terminal connection portions 116 that can be arranged on the connection circuit board 114 and the arrangement interval are limited, and the mounting density cannot be increased.

また、特許文献２に示す半導体装置では、回路基板１１２上に複数の半導体素子を積層して搭載することも可能とされているが、その際、上段の半導体素子は下段の半導体素子よりもその平面寸法が小さいものに限定される。このため、回路基板１１２上に複数の半導体素子を積層する場合には、その積層数が増えるほど、接続用回路基板１１４の面積が小さくなり、上記実装密度の問題が大となる。   In addition, in the semiconductor device disclosed in Patent Document 2, it is possible to stack and mount a plurality of semiconductor elements on the circuit board 112. At that time, the upper semiconductor element is lower than the lower semiconductor element. It is limited to a thing with a small plane dimension. For this reason, when a plurality of semiconductor elements are stacked on the circuit board 112, the area of the connection circuit board 114 decreases as the number of stacked layers increases, and the problem of the mounting density increases.

また、接続用回路基板１１４上に他の半導体装置を搭載して積層体とした場合、上段に配置される半導体装置の動作によって発生する熱は、主に、接続用回路基板１１４および接着材１１５を介して半導体素子１１１に伝わり、さらに半導体素子１１１から回路基板１１２および外部接続端子１１９を介して、実装基板へと伝わって放熱される。   In addition, when another semiconductor device is mounted on the connection circuit board 114 to form a stacked body, heat generated by the operation of the semiconductor device disposed in the upper stage mainly includes the connection circuit board 114 and the adhesive 115. The heat is transmitted to the semiconductor element 111 through the semiconductor device 111 and further transferred from the semiconductor device 111 to the mounting substrate through the circuit board 112 and the external connection terminal 119 to be dissipated.

接着材１１５はその厚さが薄いため、接続用回路基板１１４の熱を半導体素子１１１へと伝えやすく、半導体素子１１１と回路基板１１２との間も接着材等を介しているため、接続用回路基板１１４の熱は実装基板に比較的伝わりやすい。   Since the adhesive 115 is thin, it is easy to transfer the heat of the connection circuit board 114 to the semiconductor element 111, and the connection between the semiconductor element 111 and the circuit board 112 is also via an adhesive or the like. The heat of the substrate 114 is relatively easily transmitted to the mounting substrate.

しかしながら、半導体素子１１１の動作によっても発熱がある場合には、接続用回路基板１１４上に積層されている半導体装置の動作による熱は、接続用回路基板１１４に伝わりにくくなる。これは、熱の移動しやすさは、温度差の大きさに比例するという熱の性質による。   However, in the case where heat is also generated by the operation of the semiconductor element 111, heat due to the operation of the semiconductor device stacked on the connection circuit board 114 is not easily transmitted to the connection circuit board 114. This is due to the nature of heat that the ease of heat transfer is proportional to the magnitude of the temperature difference.

また、接続用回路基板１１４と回路基板１１２とを接続しているもう１つの経路である導電体はワイヤ１１７であるため、伝えることのできる熱量は少なく、放熱への寄与は少ない。   Further, since the conductor, which is another path connecting the circuit board 114 for connection and the circuit board 112, is the wire 117, the amount of heat that can be transferred is small, and the contribution to heat radiation is small.

これらのことから、特許文献２における半導体装置上に他の半導体装置が積層されており、何れの半導体装置においても半導体素子の動作による発熱がある場合には、上段に積層されている半導体装置の放熱性が低下する、という問題がある。   For these reasons, when another semiconductor device is stacked on the semiconductor device in Patent Document 2 and any of the semiconductor devices generates heat due to the operation of the semiconductor element, the semiconductor device stacked in the upper stage is used. There is a problem that heat dissipation decreases.

本発明は、上記の問題点に鑑みてなされたものであり、その目的は、上段に積層する半導体装置や電子部品との接続に用いられる外部接続用端子の配置に制約が少なく、実装密度の向上が可能であり、かつ、放熱性に優れた、小型および薄型な半導体装置を実現することにある。   The present invention has been made in view of the above problems, and its purpose is that there are few restrictions on the arrangement of external connection terminals used for connection with semiconductor devices and electronic components stacked in the upper stage, and the mounting density is low. An object of the present invention is to realize a small and thin semiconductor device that can be improved and has excellent heat dissipation.

本発明に係る半導体装置は、上記課題を解決するために、回路基板上に少なくとも一つの半導体素子を搭載してなる半導体装置において、最上層にある半導体素子の上面に、外部端子接続部を備えた接続用回路基板が搭載され、上記接続用回路基板の下面と上記回路基板の上面とが導電体端子にて接続され、上記回路基板と上記接続用回路基板との間は、封止樹脂によって封止されていることを特徴としている。   In order to solve the above problems, a semiconductor device according to the present invention includes an external terminal connection portion on the upper surface of a semiconductor element in the uppermost layer in a semiconductor device in which at least one semiconductor element is mounted on a circuit board. The connection circuit board is mounted, the lower surface of the connection circuit board and the upper surface of the circuit board are connected by a conductor terminal, and a sealing resin is used between the circuit board and the connection circuit board. It is characterized by being sealed.

上記の構成によれば、外部端子接続部を備えた接続用回路基板が、半導体素子上に搭載され、接続用回路基板の下面と回路基板の上面とは導電体端子によって接続される。これにより、上段に積層される半導体装置を電気的に接続するための配線を、回路基板ではなく接続用回路基板に設けることができる。このため、回路基板および接続用回路基板の両方における配線が複雑化することを防止でき、これによって両基板の平面的な寸法の増加を抑制できる。   According to said structure, the circuit board for a connection provided with the external terminal connection part is mounted on a semiconductor element, and the lower surface of the circuit board for a connection and the upper surface of a circuit board are connected by a conductor terminal. Thus, wiring for electrically connecting the semiconductor devices stacked in the upper stage can be provided on the connection circuit board instead of the circuit board. For this reason, it can prevent that the wiring in both a circuit board and the circuit board for a connection is complicated, and, thereby, can suppress the increase in the planar dimension of both boards.

また、接続用回路基板の下面と回路基板の上面とをワイヤボンドではなく、端子形状の導電体端子を用いて接続することにより、ワイヤボンドで接続した場合に必要な、接続用回路基板上のワイヤループ高さと、ワイヤボンドを封止する封止樹脂分の高さが必要なくなる。このため、上記半導体装置では、小型化および薄型化を実現することができる。   In addition, by connecting the lower surface of the circuit board for connection and the upper surface of the circuit board using a terminal-shaped conductor terminal instead of wire bonding, it is necessary on the circuit board for connection necessary for connection by wire bonding. The height of the wire loop and the height of the sealing resin for sealing the wire bond are not necessary. For this reason, in the said semiconductor device, size reduction and thickness reduction are realizable.

さらに、上記半導体装置では、接続用回路基板の下面と回路基板の上面とが導電体端子によって接続されるため、接続用回路基板はその下に位置する半導体素子よりも平面寸法が小さいものに限定されることはない。したがって、接続用回路基板は、回路基板とほぼ等しい面積を有する基板として具備することが可能となり、接続用回路基板において外部端子接続部を配置することができる平面的な領域を大きくすることができる。   Further, in the semiconductor device, since the lower surface of the connection circuit board and the upper surface of the circuit board are connected by the conductor terminals, the connection circuit board is limited to one having a smaller planar dimension than the semiconductor element located therebelow. It will never be done. Therefore, the circuit board for connection can be provided as a board having an area substantially equal to the circuit board, and a planar area where the external terminal connection portion can be arranged on the circuit board for connection can be increased. .

また、上記半導体装置では、上記導電体端子は、核の外側に導電層を有する端子であることを特徴としている。   In the semiconductor device, the conductor terminal is a terminal having a conductive layer outside the nucleus.

上記の構成によれば、導電体端子が核を持つことで、導電体端子の高さを一定に保ちやすく、接続用回路基板と回路基板との接続安定性を保つことができる。   According to said structure, when a conductor terminal has a nucleus, it is easy to keep the height of a conductor terminal constant, and can maintain the connection stability of the circuit board for a connection and a circuit board.

また、上記半導体装置では、上記導電体端子は、半導体装置の厚さ方向に複数個の略球形形状の導電体端子を積層してなることを特徴としている。   In the semiconductor device, the conductor terminal is formed by laminating a plurality of substantially spherical conductor terminals in the thickness direction of the semiconductor device.

上記の構成によれば、回路基板と接続用回路基板との間の距離が大きくなるような場合に、回路基板と接続用回路基板とを接続する導電体の高さを調整しやすくなる。   According to said structure, when the distance between a circuit board and a circuit board for a connection becomes large, it becomes easy to adjust the height of the conductor which connects a circuit board and a circuit board for a connection.

また、上記半導体装置は、上記回路基板上に複数の半導体素子を有することを特徴としている。   The semiconductor device has a plurality of semiconductor elements on the circuit board.

上記の構成によれば、一つの半導体装置内に、複数の半導体素子を積層して搭載することで、半導体装置の実装密度をより向上することができる。   According to said structure, the mounting density of a semiconductor device can be improved more by laminating | stacking and mounting a several semiconductor element in one semiconductor device.

また、本発明に係る半導体装置の積層体は、上記に記載の半導体装置上に、他の半導体装置もしくは他の電子部品が積層配置され、上記半導体装置の上記外部端子接続部と、その上段の他の半導体装置もしくは他の電子部品とが導電体によって接続されていることを特徴としている。   Further, in the stacked body of the semiconductor device according to the present invention, another semiconductor device or another electronic component is stacked on the semiconductor device described above, and the external terminal connection portion of the semiconductor device and the upper stage thereof are arranged. Another semiconductor device or another electronic component is connected by a conductor.

上記の構成によれば、半導体装置上に、他の半導体装置もしくは他の電子部品を積層配置することで、要求される実装密度を保ったまま、製造上および信頼性上の問題を解決し、また半導体装置の汎用性を確保できる。   According to the above configuration, by stacking other semiconductor devices or other electronic components on the semiconductor device, the manufacturing and reliability problems can be solved while maintaining the required mounting density. Moreover, the versatility of the semiconductor device can be ensured.

また、上段に配置される半導体装置（または電子部品）の動作による熱は、下段の半導体装置における接続用回路基板、導電体端子、回路基板、外部接続用端子を介した経路によっても実装基板に伝達される。これにより、上段に積層された半導体装置や電子部品の放熱特性の向上が可能となる。   The heat generated by the operation of the semiconductor device (or electronic component) disposed in the upper stage is also transferred to the mounting board by a route through the connection circuit board, conductor terminal, circuit board, and external connection terminal in the lower semiconductor device. Communicated. This makes it possible to improve the heat dissipation characteristics of the semiconductor devices and electronic components stacked in the upper stage.

また、本発明に係る半導体装置の製造方法は、回路基板上に半導体素子を搭載し、該半導体素子と該回路基板とを電気的に接続する工程と、上記回路基板上に導電体端子を搭載する工程と、外部端子接続部を備えた接続用回路基板を、上記半導体素子上に搭載すると共に、上記接続用回路基板の下面と上記回路基板上に搭載された導電体端子とを接続する工程と、上記回路基板と上記接続用回路基板との間を樹脂封止する工程と、上記回路基板の下面に外部接続端子を搭載する工程を有することを特徴としている。   The method of manufacturing a semiconductor device according to the present invention includes a step of mounting a semiconductor element on a circuit board, electrically connecting the semiconductor element and the circuit board, and mounting a conductor terminal on the circuit board. And a step of mounting a connection circuit board having an external terminal connection portion on the semiconductor element and connecting a lower surface of the connection circuit board and a conductor terminal mounted on the circuit board. And a step of resin-sealing between the circuit board and the circuit board for connection, and a step of mounting external connection terminals on the lower surface of the circuit board.

また、本発明に係る半導体装置の他の製造方法は、フレーム状の回路基板上に半導体素子を搭載し、該半導体素子と該回路基板とを電気的に接続する工程と、上記回路基板上に導電体端子を搭載する工程と、外部端子接続部を備えたフレーム状の接続用回路基板を、上記半導体素子上に搭載すると共に、上記接続用回路基板の下面と上記回路基板上に搭載された導電体端子とを接続する工程と、上記回路基板と上記接続用回路基板との間を樹脂封止する工程と、上記回路基板の下面に外部接続端子を搭載する工程と、フレームから個別の半導体装置を切り出す工程を有することを特徴としている。   Another method of manufacturing a semiconductor device according to the present invention includes a step of mounting a semiconductor element on a frame-shaped circuit board, electrically connecting the semiconductor element and the circuit board, and the circuit board. A step of mounting a conductor terminal and a frame-like connection circuit board having an external terminal connection portion are mounted on the semiconductor element, and are mounted on the lower surface of the connection circuit board and the circuit board. A step of connecting a conductor terminal, a step of resin-sealing between the circuit board and the circuit board for connection, a step of mounting an external connection terminal on the lower surface of the circuit board, and an individual semiconductor from the frame It has the process of cutting out an apparatus.

上記の構成によれば、上述したような特徴を有する半導体装置を製造可能となる。
また、複数個分の半導体装置に対応したフレーム状の回路基板とフレーム状の接続用回路基板を用いて、複数個分の半導体装置を同時に形成し、最後に半導体装置各個片に切り出す工程によって半導体装置を製造する方法では、樹脂封止する際の金型が必要なく、任意のサイズの半導体装置の製造に対応でき、コスト低減を図ることができる。 According to said structure, the semiconductor device which has the above characteristics can be manufactured.
Also, by using a frame-shaped circuit board and a frame-shaped connection circuit board corresponding to a plurality of semiconductor devices, a plurality of semiconductor devices are simultaneously formed, and finally the semiconductor device is cut into individual pieces of semiconductor devices. The method for manufacturing the device does not require a metal mold for resin sealing, can cope with the manufacture of a semiconductor device of any size, and can reduce the cost.

本発明に係る半導体装置は、以上のように、最上層にある半導体素子の上面に、外部端子接続部を備えた接続用回路基板が接着材を介して搭載され、上記接続用回路基板の下面と上記回路基板の上面とが導電体端子にて接続され、上記回路基板と上記接続用回路基板との間は、封止樹脂によって封止されている構成である。   As described above, in the semiconductor device according to the present invention, the connection circuit board having the external terminal connection portion is mounted on the upper surface of the semiconductor element in the uppermost layer via the adhesive, and the lower surface of the connection circuit board. And the upper surface of the circuit board are connected by a conductor terminal, and the circuit board and the circuit board for connection are sealed with a sealing resin.

それゆえ、上段に積層される半導体装置を電気的に接続するための配線を、回路基板ではなく接続用回路基板に設けることができ、回路基板および接続用回路基板の両方における配線が複雑化することを防止できるため、両基板の平面的な寸法の増加を抑制できるといった効果を奏する。   Therefore, the wiring for electrically connecting the semiconductor devices stacked in the upper stage can be provided not on the circuit board but on the connection circuit board, and the wiring on both the circuit board and the connection circuit board becomes complicated. Since this can be prevented, an increase in the planar dimensions of both substrates can be suppressed.

また、接続用回路基板の下面と回路基板の上面とをワイヤボンドではなく、端子形状の導電体端子を用いて接続することにより、ワイヤボンドで接続した場合に必要な、接続用回路基板上のワイヤループ高さと、ワイヤボンドを封止する封止樹脂分の高さが必要なくなり、半導体装置における小型化および薄型化を実現することができるといった効果を奏する。   In addition, by connecting the lower surface of the circuit board for connection and the upper surface of the circuit board using a terminal-shaped conductor terminal instead of wire bonding, it is necessary on the circuit board for connection necessary for connection by wire bonding. The height of the wire loop and the height of the sealing resin for sealing the wire bond are not required, and the semiconductor device can be reduced in size and thickness.

さらに、上記半導体装置では、接続用回路基板の下面と回路基板の上面とが導電体端子によって接続されるため、接続用回路基板は、回路基板とほぼ等しい面積を有する基板として具備することが可能となり、接続用回路基板において外部端子接続部を配置することができる平面的な領域を大きくすることができるといった効果を奏する。   Further, in the above semiconductor device, the lower surface of the connection circuit board and the upper surface of the circuit board are connected by the conductor terminals, so that the connection circuit board can be provided as a substrate having an area substantially equal to the circuit board. Thus, there is an effect that the planar area where the external terminal connection portion can be arranged on the circuit board for connection can be enlarged.

本発明の一実施形態について図１ないし図９に基づいて説明すると以下の通りである。
尚、以下に示す各実施の形態は、本発明を具体化した例示であって、本発明の技術的範囲を限定するものではない。 An embodiment of the present invention will be described with reference to FIGS. 1 to 9 as follows.
In addition, each embodiment shown below is the illustration which actualized this invention, Comprising: The technical scope of this invention is not limited.

〔実施の形態１〕
本発明の実施の形態１に係る半導体装置の構成を図１に示す。 [Embodiment 1]
FIG. 1 shows the configuration of the semiconductor device according to the first embodiment of the present invention.

上記半導体装置は、図１に示すように、回路基板１２に接着材１３を介して半導体素子１１が接続されており、半導体素子１１と回路基板１２とはワイヤ１４にて電気的に接続されている。   In the semiconductor device, as shown in FIG. 1, a semiconductor element 11 is connected to a circuit board 12 via an adhesive 13, and the semiconductor element 11 and the circuit board 12 are electrically connected by a wire 14. Yes.

また、外部端子接続部１７を有する接続用回路基板１５が接着材１６を介して半導体素子１１上に接続されており、接続用回路基板１５下面と回路基板１２上面とは導電体端子１８で電気的に接続されている。導電体端子１８には、はんだ端子、金属バンプ、導電性ペースト、導電性樹脂などを用いることができる。導電性ペースト、導電性樹脂は、回路基板１２上にマスク印刷する方法や、ディスペンサーを用いてノズルから出して塗布する方法等により形成可能である。   A connection circuit board 15 having an external terminal connection portion 17 is connected to the semiconductor element 11 via an adhesive 16, and the lower surface of the connection circuit board 15 and the upper surface of the circuit board 12 are electrically connected by a conductor terminal 18. Connected. For the conductor terminal 18, a solder terminal, a metal bump, a conductive paste, a conductive resin, or the like can be used. The conductive paste and the conductive resin can be formed by a method of mask printing on the circuit board 12, a method of applying from a nozzle using a dispenser, or the like.

導電体端子１８に、はんだ端子や金属バンプを用いた場合には、その高い弾性ゆえに、高さを一定に保ちやすいという性質かある。一方、導電体端子１８に、導電性ペーストや導電性樹脂を用いた場合には、これらの材料は硬化させる前は柔らかいので、回路基板１２に搭載もしくは塗布した後、接続用回路基板１５を半導体素子１１上に搭載する際の圧力によって、容易に潰しやすく、目標の高さ・形状を得やすいといった性質がある。   When a solder terminal or a metal bump is used for the conductor terminal 18, the height is easily maintained because of its high elasticity. On the other hand, when a conductive paste or conductive resin is used for the conductor terminal 18, these materials are soft before being cured. Therefore, after being mounted on or applied to the circuit board 12, the connection circuit board 15 is connected to the semiconductor terminal 18. Depending on the pressure when mounted on the element 11, it is easily crushed and has a property of easily obtaining a target height and shape.

上記半導体装置では、回路基板１２と接続用回路基板１５との間が、すなわち回路基板１２と接続用回路基板１５との間に配置される半導体素子１１、ワイヤ１４および導電体端子１８が、封止樹脂１９によって封止されている。また、封止樹脂１９は外部端子接続部１７と接続用回路基板１５の一部とが露出するように該半導体装置を封止している。回路基板１２の下面には、導電体からなる外部接続端子２０が設けられている。外部接続端子２０は、上記半導体装置を実装基板に接続するために用いられる。   In the semiconductor device, the semiconductor element 11, the wires 14, and the conductor terminals 18 disposed between the circuit board 12 and the connection circuit board 15, that is, between the circuit board 12 and the connection circuit board 15, are sealed. Sealed with a stop resin 19. The sealing resin 19 seals the semiconductor device so that the external terminal connection portion 17 and a part of the connection circuit board 15 are exposed. An external connection terminal 20 made of a conductor is provided on the lower surface of the circuit board 12. The external connection terminal 20 is used for connecting the semiconductor device to a mounting substrate.

上記構成の半導体装置においては、外部端子接続部１７を備えた接続用回路基板１５が、半導体素子１１上に接着材１６を介して搭載され、接続用回路基板１５の下面と回路基板１２の上面とは導電体端子１８によって接続される。これにより、上段に積層される半導体装置を電気的に接続するための配線を、回路基板１２ではなく接続用回路基板１５に設けることができる。このため、回路基板１２および接続用回路基板１５の両方における配線が複雑化することを防止でき、これによって両基板の平面的な寸法の増加を抑制できる。   In the semiconductor device having the above configuration, the connection circuit board 15 including the external terminal connection portion 17 is mounted on the semiconductor element 11 via the adhesive 16, and the lower surface of the connection circuit board 15 and the upper surface of the circuit board 12 are mounted. Are connected by a conductor terminal 18. Accordingly, wiring for electrically connecting the semiconductor devices stacked in the upper stage can be provided not on the circuit board 12 but on the connection circuit board 15. For this reason, it can prevent that the wiring in both the circuit board 12 and the circuit board 15 for a connection is complicated, and can suppress the increase in the planar dimension of both board | substrates by this.

また、接続用回路基板１５の下面と回路基板１２の上面とをワイヤボンドではなく、端子形状の導電体端子１８を用いて接続することにより、ワイヤボンドで接続した場合に必要な、接続用回路基板１５上のワイヤループ高さと、ワイヤボンドを封止する封止樹脂分の高さが必要なくなる。このため、上記半導体装置では、小型化および薄型化を実現することができる。   Further, the connection circuit required when the connection is made by the wire bond by connecting the lower surface of the connection circuit board 15 and the upper surface of the circuit board 12 by using the terminal-shaped conductor terminal 18 instead of the wire bond. The height of the wire loop on the substrate 15 and the height of the sealing resin for sealing the wire bond are not necessary. For this reason, in the said semiconductor device, size reduction and thickness reduction are realizable.

さらに、上記半導体装置では、接続用回路基板１５の下面と回路基板１２の上面とが導電体端子１８によって接続されるため、接続用回路基板１５はその下に位置する半導体素子１１よりも平面寸法が小さいものに限定されることはない。したがって、接続用回路基板１５は、回路基板１２とほぼ等しい面積を有する基板として具備することが可能となり、接続用回路基板１５において外部端子接続部１７を配置することができる平面的な領域を大きくできる。   Further, in the semiconductor device, since the lower surface of the connection circuit board 15 and the upper surface of the circuit board 12 are connected by the conductor terminals 18, the connection circuit board 15 has a plan dimension larger than that of the semiconductor element 11 located therebelow. Is not limited to a small one. Therefore, the connection circuit board 15 can be provided as a board having an area substantially equal to the circuit board 12, and a large planar area in which the external terminal connection portion 17 can be arranged in the connection circuit board 15 is large. it can.

また、本実施の形態１に半導体装置の変形例を、図２ないし図４を用いて説明する。   Further, a modification of the semiconductor device according to the first embodiment will be described with reference to FIGS.

図１に示す半導体装置では、封止樹脂１９は接続用回路基板１５の上面の一部を覆うように形成されていたが、本発明はこれに限らず、図２に示すように、封止樹脂１９は接続用回路基板１５の下面および側面のみを覆うようにし、接続用回路基板１５の上面はその全面が封止樹脂１９から露出する構成であってもよい。あるいは、図３に示すように、接続用回路基板１５の上面全面と側面の少なくとも一部が露出してもよい。接続用回路基板１５の上面を全面が露出するようにすることで、外部端子接続部１７を接続用回路基板１５上の全面に配置することが可能となる。   In the semiconductor device shown in FIG. 1, the sealing resin 19 is formed so as to cover a part of the upper surface of the connection circuit board 15. However, the present invention is not limited to this, and as shown in FIG. The resin 19 may be configured to cover only the lower surface and side surfaces of the connection circuit board 15, and the entire upper surface of the connection circuit board 15 may be exposed from the sealing resin 19. Alternatively, as shown in FIG. 3, the entire upper surface and at least part of the side surfaces of the connection circuit board 15 may be exposed. By exposing the entire upper surface of the connection circuit board 15, the external terminal connection portion 17 can be disposed on the entire surface of the connection circuit board 15.

また、図１に示す半導体装置では、半導体素子１１と回路基板１２との接続はワイヤボンドであったが、本発明はこれに限らず、図２に示すようなフリップチップ接続や、導電性樹脂での接続であってもよい。半導体素子１１と回路基板１２との接続にフリップチップ接続を用いる場合、パッケージ高さを低くできるといったメリットがある。   In the semiconductor device shown in FIG. 1, the connection between the semiconductor element 11 and the circuit board 12 is a wire bond. However, the present invention is not limited to this, and flip-chip connection as shown in FIG. It may be a connection. When flip chip connection is used for connection between the semiconductor element 11 and the circuit board 12, there is an advantage that the package height can be reduced.

また、図１に示す半導体装置では、接着材１６は半導体素子１１上だけに形成されていたが、本発明はこれに限らず、図３に示すように、接着材１６は接続用基板１５の下面全域に形成されていてもよい。この場合、ワイヤ１４は、接着材１６に一部を覆われていてもよい。   In the semiconductor device shown in FIG. 1, the adhesive 16 is formed only on the semiconductor element 11. However, the present invention is not limited to this, and the adhesive 16 is formed on the connection substrate 15 as shown in FIG. 3. You may form in the whole lower surface. In this case, the wire 14 may be partially covered with the adhesive 16.

また、図４に示す半導体装置は、図１に示す半導体装置において、導電体端子１８に代えて導電体端子２１を用いた構成となっている。導電体端子２１は、中に核２１Ａを持っており、核２１Ａの外側に導電層２１Ｂを有する端子である。核２１Ａは、導電体であっても絶縁体であっても良く、金属や樹脂からなっている。   Further, the semiconductor device shown in FIG. 4 has a configuration in which the conductor terminal 21 is used instead of the conductor terminal 18 in the semiconductor device shown in FIG. The conductor terminal 21 is a terminal having a nucleus 21A therein and a conductive layer 21B outside the nucleus 21A. The core 21A may be a conductor or an insulator, and is made of metal or resin.

上記半導体装置では、導電体端子２１が核２１Ａを持つことで、導電体端子２１の高さを一定に保ちやすく、接続用回路基板１５と回路基板１２との接続安定性を保つことができる。特に、核２１Ａがその外側に存在する導電層２１Ｂよりも硬ければ、本半導体装置を製造する工程中で高温での処理が行われる時に、より導電体端子２１の高さを一定に保ちやすくなる効果が大きい。尚、ここでの硬さとは、硬度またはヤング率または弾性率などで表される。   In the semiconductor device, since the conductor terminal 21 has the nucleus 21A, the height of the conductor terminal 21 can be easily kept constant, and the connection stability between the connection circuit board 15 and the circuit board 12 can be maintained. In particular, if the core 21A is harder than the conductive layer 21B existing on the outside, it is easier to keep the height of the conductor terminal 21 constant when processing at a high temperature is performed in the process of manufacturing the semiconductor device. The effect is great. Here, the hardness is represented by hardness, Young's modulus, elastic modulus, or the like.

〔実施の形態２〕
本発明の実施の形態２に係る半導体装置の構成を図５に示す。 [Embodiment 2]
FIG. 5 shows the configuration of the semiconductor device according to the second embodiment of the present invention.

本実施の形態２に係る半導体装置は、図５に示すように、回路基板１２上に複数の半導体素子２２および２３を有した構成となっている。接続用回路基板１５は、最上層にある半導体素子、すなわち回路基板１２から最も離れて搭載される上段の半導体素子２３のさらに上面に、接着材１６を介して搭載される。また、下段に配置される半導体素子２２と上段に配置される半導体素子２３とは、接着材２４によって接続される。このように、一つの半導体装置内に、複数の半導体素子を積層して搭載することで、半導体装置の実装密度をより向上することができる。もちろん、半導体装置内に搭載される半導体素子の数は３つ以上であっても良い。   As shown in FIG. 5, the semiconductor device according to the second embodiment has a configuration having a plurality of semiconductor elements 22 and 23 on a circuit board 12. The connection circuit board 15 is mounted via an adhesive 16 on the upper surface of the uppermost semiconductor element 23 mounted on the uppermost layer, that is, the uppermost semiconductor element 23 mounted on the circuit board 12. Further, the semiconductor element 22 arranged in the lower stage and the semiconductor element 23 arranged in the upper stage are connected by an adhesive material 24. As described above, by mounting a plurality of semiconductor elements in a single semiconductor device, the mounting density of the semiconductor devices can be further improved. Of course, the number of semiconductor elements mounted in the semiconductor device may be three or more.

尚、図１に示す半導体装置では、上段に配置される半導体素子２３よりも下段に配置される半導体素子２２をより寸法の大きな半導体素子としているが、本発明はこれに限定されるものではない。すなわち、上段の半導体素子と下段の半導体素子とを同じ寸法としても良く、あるいは上段よりも下段により寸法の大きな半導体素子を搭載したものであっても良い。全く同じ半導体素子を複数段積み重ねて搭載することも可能である。尚、半導体素子の組合せを制限するものには、半導体素子のサイズや、半導体素子のワイヤボンドパッド位置関係などがある。   In the semiconductor device shown in FIG. 1, the semiconductor element 22 disposed in the lower stage is a semiconductor element having a larger dimension than the semiconductor element 23 disposed in the upper stage, but the present invention is not limited to this. . That is, the upper semiconductor element and the lower semiconductor element may have the same dimensions, or a semiconductor element having a larger dimension in the lower stage than the upper stage may be mounted. It is also possible to mount the same semiconductor elements stacked in multiple stages. In addition, what restrict | limits the combination of a semiconductor element has the size of a semiconductor element, the wire bond pad positional relationship of a semiconductor element, etc.

図６は、下段に配置される半導体素子２２よりも上段に配置される半導体素子２３をより寸法の大きな半導体素子とした場合の構成例である。このとき、下段の半導体素子２２と回路基板１２とを接続しているワイヤ１４の一部は、接着材２４に覆われており、上段の半導体素子２３との絶縁が保たれるような構造をとってもよい。また、図６ではそのような構成とはなっていないが、他方の半導体素子２２においても、ワイヤ１４が接着材１６に一部覆われる構造をとることができる。   FIG. 6 is a configuration example in the case where the semiconductor element 23 arranged in the upper stage than the semiconductor element 22 arranged in the lower stage is a semiconductor element having a larger size. At this time, a part of the wire 14 that connects the lower semiconductor element 22 and the circuit board 12 is covered with the adhesive 24 so that the insulation with the upper semiconductor element 23 is maintained. It may be taken. Although not configured as shown in FIG. 6, the other semiconductor element 22 can also have a structure in which the wire 14 is partially covered by the adhesive 16.

ワイヤ１４が接着材２４または１６に一部覆われる構造をとることにより、本半導体装置に搭載する半導体素子の組合せに制限がなくなり、種々の半導体素子をひとつの半導体装置に搭載することが可能となる。これにより、より高機能で、より薄型・小型な半導体装置を実現できる。   By adopting a structure in which the wire 14 is partially covered by the adhesive 24 or 16, there is no restriction on the combination of semiconductor elements mounted on the semiconductor device, and various semiconductor elements can be mounted on one semiconductor device. Become. As a result, it is possible to realize a semiconductor device with higher functionality, thinner and smaller.

また、同一の半導体装置内に複数の半導体素子を積層して搭載する場合、一つの半導体素子を搭載する場合に比べて、回路基板１２と接続用回路基板１５との間の距離が大きくなる。このような場合、回路基板１２と接続用回路基板１５とを接続する導電体端子は、図６に示すように、複数個の略球形形状の導電体端子２５を積層した構造をとることもできる。このように、複数個の略球形形状の導電体端子２５を積層した構造では、回路基板１２と接続用回路基板１５とを接続する導電体の高さを調整しやすくなる。   Further, when a plurality of semiconductor elements are stacked and mounted in the same semiconductor device, the distance between the circuit board 12 and the connection circuit board 15 is larger than when a single semiconductor element is mounted. In such a case, the conductor terminal that connects the circuit board 12 and the connection circuit board 15 may have a structure in which a plurality of substantially spherical conductor terminals 25 are stacked as shown in FIG. . As described above, in the structure in which the plurality of substantially spherical conductor terminals 25 are stacked, the height of the conductor connecting the circuit board 12 and the connection circuit board 15 can be easily adjusted.

すなわち、図５に示すように、半導体装置の厚さ方向（基板や素子の積層方向）に一つの導電体端子１８を配して回路基板１２と接続用回路基板１５との接続を図る方法では、導電体端子１８が楕円形状のような長手方向を有する形状となる。このため、該導電体端子１８の長手方向が基板法線に垂直となるように搭載しなければならず、導電体端子１８の高さ調整が困難となる。   That is, as shown in FIG. 5, in the method of arranging one conductor terminal 18 in the thickness direction of the semiconductor device (in the direction in which the substrates and elements are stacked), the circuit board 12 and the connection circuit board 15 are connected. The conductor terminal 18 has a shape having a longitudinal direction such as an elliptical shape. For this reason, it must be mounted so that the longitudinal direction of the conductor terminal 18 is perpendicular to the normal line of the substrate, and it is difficult to adjust the height of the conductor terminal 18.

尚、同一の半導体装置内に複数の半導体素子を積層する構成でなくても、複数個の略球形形状の導電体端子２５を積層した構造によって、回路基板１２と接続用回路基板１５とを接続する導電体の高さを調整しやすくなる効果は得られる。このような導電体端子２５には、はんだボールや核の周りに導電層を有する導電体端子が好適に使用できる。   Note that the circuit board 12 and the connection circuit board 15 are connected by a structure in which a plurality of substantially spherical conductor terminals 25 are stacked, even if a plurality of semiconductor elements are not stacked in the same semiconductor device. The effect which becomes easy to adjust the height of the conductor to perform is acquired. As such a conductor terminal 25, a conductor terminal having a conductive layer around a solder ball or core can be preferably used.

〔実施の形態３〕
本発明の実施の形態３に係る半導体装置の構成を図７に示す。図７に示す半導体装置は、上記実施の形態１または２で説明したような半導体装置を複数個積層した積層体とし、この積層体自体を一つの半導体装置とした構成例である。 [Embodiment 3]
FIG. 7 shows the configuration of the semiconductor device according to the third embodiment of the present invention. The semiconductor device shown in FIG. 7 is a structural example in which a plurality of semiconductor devices as described in the first or second embodiment are stacked, and the stacked body itself is a single semiconductor device.

すなわち、図７に示す半導体装置は、半導体装置１および２を積層して、下段の半導体装置１における接続用回路基板１５の外部端子接続部１７と、その上段の半導体装置２の回路基板１２の外部接続部とが外部接続端子２０によって接続された構成である。これにより、下段半導体装置１と上段半導体装置２とが電気的に接続され、半導体装置の積層体を形成することができる。   That is, in the semiconductor device shown in FIG. 7, the semiconductor devices 1 and 2 are stacked, and the external terminal connection portion 17 of the connection circuit board 15 in the lower semiconductor device 1 and the circuit board 12 of the upper semiconductor device 2 are connected. The external connection unit is connected to the external connection terminal 20. Thereby, the lower semiconductor device 1 and the upper semiconductor device 2 are electrically connected, and a stacked body of semiconductor devices can be formed.

尚、上述のように、複数の半導体装置を積層配置する構成においては、上段および下段の半導体装置が共に、本発明に係る半導体装置である必要はなく、少なくとも下段に配置される半導体装置が本発明に係るものであれば良い。また、上段に配置されるのは、半導体装置以外の電子部品であっても良い。   As described above, in the configuration in which a plurality of semiconductor devices are stacked, both the upper and lower semiconductor devices do not have to be semiconductor devices according to the present invention, and at least the semiconductor devices arranged in the lower stage are the main devices. Any device according to the invention may be used. Further, electronic components other than the semiconductor device may be disposed in the upper stage.

本実施の形態３に係る半導体装置では、上段に配置される半導体装置２（または電子部品）の動作による熱は、下段の半導体装置１における接続用回路基板１５、導電体端子１８、回路基板１２、外部接続用端子２０を介した経路によっても実装基板に伝達される。   In the semiconductor device according to the third embodiment, the heat generated by the operation of the semiconductor device 2 (or electronic component) disposed in the upper stage is the circuit board 15 for connection, the conductor terminal 18, and the circuit board 12 in the lower semiconductor device 1. Also, the signal is transmitted to the mounting board through a route via the external connection terminal 20.

すなわち、接続用回路基板１５と回路基板１２とが導電体端子１８で接続されることで、これらがワイヤボンドで接続されている場合と比較して、上段に積層された半導体装置や電子部品の放熱特性の向上が可能となる。これは、導電体端子１８は、ワイヤに比べて断面積が大きく、かつ、経路も短くなるためである。   That is, the connection circuit board 15 and the circuit board 12 are connected by the conductor terminals 18, so that compared with the case where they are connected by wire bonding, the semiconductor device and the electronic component stacked in the upper stage are compared. The heat dissipation characteristics can be improved. This is because the conductor terminal 18 has a larger cross-sectional area and a shorter path than the wire.

〔実施の形態４〕
本発明に係る半導体装置の製造方法を、図８（ａ）〜（ｄ）を参照して以下に説明する。尚、図８（ａ）〜（ｄ）では、図３に示す構造の半導体装置を製造する場合を例示する。 [Embodiment 4]
A method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. 8A to 8D illustrate the case where the semiconductor device having the structure shown in FIG. 3 is manufactured.

先ず、図８（ａ）に示すように、回路基板１２に半導体素子１１を搭載し、半導体素子１１と回路基板１２とをワイヤ１４にて接続する。   First, as shown in FIG. 8A, the semiconductor element 11 is mounted on the circuit board 12, and the semiconductor element 11 and the circuit board 12 are connected by the wire 14.

次に、図８（ｂ）に示すように、導電体１８を回路基板１２に搭載する。その後、図８（ｃ）に示すように、接着材１６が予め接着された接続用回路基板１５を半導体素子１１上に接着する。接続用回路基板１５には、外部端子接続部１７が先に形成されている。このとき、接着材１６にて半導体素子１１と接続用回路基板１５とを接着する工程での熱により、導電体１８と接続用回路基板１５とを同時に接続してもよい。   Next, as shown in FIG. 8B, the conductor 18 is mounted on the circuit board 12. Thereafter, as shown in FIG. 8C, the connection circuit board 15 to which the adhesive 16 is bonded in advance is bonded onto the semiconductor element 11. An external terminal connection portion 17 is formed on the connection circuit board 15 first. At this time, the conductor 18 and the connection circuit board 15 may be simultaneously connected by heat in the process of bonding the semiconductor element 11 and the connection circuit board 15 with the adhesive 16.

上記接着時に熱を加えることで、導電体１８の材料が軟化または溶融、もしくはそれに近い状態になって硬度もしくは弾性が低下し、そこに上から接続用回路基板１５を圧力を加えて接続されることで、導電体１８の高さを制御しながら、接続用回路基板１５と接続することができる。   By applying heat at the time of bonding, the material of the conductor 18 is softened or melted, or is in a state close to that, the hardness or elasticity is lowered, and the connecting circuit board 15 is connected thereto by applying pressure thereto. Thus, it is possible to connect to the connection circuit board 15 while controlling the height of the conductor 18.

また、接続用回路基板１５と半導体素子１１とを接着した後に、接続用回路基板１５と導電体１８とを接続する工程を設けてもよい。   Further, after bonding the connection circuit board 15 and the semiconductor element 11, a step of connecting the connection circuit board 15 and the conductor 18 may be provided.

最後に、図８（ｄ）に示すように、封止樹脂１９を注入もしくは封止し、外部接続端子２０を搭載する。   Finally, as shown in FIG. 8D, the sealing resin 19 is injected or sealed, and the external connection terminals 20 are mounted.

尚、上記図８（ａ）〜（ｄ）では、一つの半導体装置を製造する方法として説明したが、この工程の全てを、図９（ａ）〜（ｅ）に示すように、複数個分の半導体装置に対応したフレーム状の回路基板１２’とフレーム状の接続用回路基板１５’とによって製造し、最後に半導体装置各個片にカットする工程によって製造してもよい。   In FIGS. 8A to 8D, the method of manufacturing one semiconductor device has been described. However, as shown in FIGS. 9A to 9E, all the steps are divided into a plurality of processes. The semiconductor device may be manufactured by using a frame-shaped circuit board 12 ′ and a frame-shaped connection circuit board 15 ′ corresponding to the semiconductor device, and finally cutting the semiconductor device into individual pieces.

この製造方法では、樹脂封止する際の金型が必要なく、任意のサイズの半導体装置の製造に対応でき、コスト低減を図ることができる。   This manufacturing method does not require a metal mold for resin sealing, can be used for manufacturing a semiconductor device of any size, and can reduce costs.

高密度実装化された半導体装置を形成でき、小型化および薄型化が要求される半導体装置に適用できる。   A semiconductor device mounted with high density can be formed, and can be applied to a semiconductor device that is required to be small and thin.

本発明の実施形態を示すものであり、実施の形態１に係る半導体装置の構成を示す断面図である。1, showing an embodiment of the present invention, is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1. FIG. 実施の形態１に係る半導体装置の変形例を示す断面図である。FIG. 6 is a cross-sectional view showing a modification of the semiconductor device according to the first embodiment. 実施の形態１に係る半導体装置の変形例を示す断面図である。FIG. 6 is a cross-sectional view showing a modification of the semiconductor device according to the first embodiment. 実施の形態１に係る半導体装置の変形例を示す断面図である。FIG. 6 is a cross-sectional view showing a modification of the semiconductor device according to the first embodiment. 実施の形態２に係る半導体装置の構成を示す断面図である。FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. 実施の形態２に係る半導体装置の変形例を示す断面図である。FIG. 10 is a cross-sectional view showing a modification of the semiconductor device according to the second embodiment. 実施の形態３に係る半導体装置の構成を示す断面図である。FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment. 図８（ａ）〜（ｄ）は、実施の形態４に係る半導体装置の製造工程を示す断面図である。8A to 8D are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the fourth embodiment. 図９（ａ）〜（ｅ）は、実施の形態４に係る半導体装置の製造工程の変形例を示す断面図である。9A to 9E are cross-sectional views showing a modification of the manufacturing process of the semiconductor device according to the fourth embodiment. 従来の半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the conventional semiconductor device. 図１０の半導体装置を複数個積層してなる積層体の構成を示す断面図である。It is sectional drawing which shows the structure of the laminated body formed by laminating | stacking the semiconductor device of FIG. 従来の半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the conventional semiconductor device.

符号の説明Explanation of symbols

１，２ 半導体装置
１１ 半導体素子
１２ 回路基板
１４ ワイヤ
１５ 接続用回路基板
１７ 外部端子接続部
１８ 導電体端子
１９ 封止樹脂
２０ 外部接続端子
２１ 導電体端子（核を有する導電体端子）
２２，２３ 半導体素子
２５ 導電体端子 DESCRIPTION OF SYMBOLS 1, 2 Semiconductor device 11 Semiconductor element 12 Circuit board 14 Wire 15 Connection circuit board 17 External terminal connection part 18 Conductor terminal 19 Sealing resin 20 External connection terminal 21 Conductor terminal (conductor terminal having a core)
22, 23 Semiconductor element 25 Conductor terminal

Claims (7)

回路基板上に少なくとも一つの半導体素子を載置してなる半導体装置において、
最上層にある上記半導体素子の上面に、外部端子接続部を備えた接続用回路基板が接着剤を介して載置され、
上記最上層にある半導体素子と上記回路基板とはワイヤを介して接続されており、
上記ワイヤの一部は、上記接着剤に覆われており、
上記接続用回路基板の下面と上記回路基板の上面とが導電体端子にて接続され、
上記回路基板と上記接続用回路基板との間は、封止樹脂によって封止されていることを特徴とする半導体装置。 In a semiconductor device in which at least one semiconductor element is mounted on a circuit board,
On the upper surface of the semiconductor element in the uppermost layer, a connection circuit board having external terminal connection portions is placed via an adhesive,
The semiconductor element in the uppermost layer and the circuit board are connected via a wire,
A part of the wire is covered with the adhesive,
The lower surface of the circuit board for connection and the upper surface of the circuit board are connected by a conductor terminal,
A semiconductor device, wherein the circuit board and the connection circuit board are sealed with a sealing resin. 上記導電体端子は、核の外側に導電層を有する端子であることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductor terminal is a terminal having a conductive layer outside a nucleus. 上記導電体端子は、半導体装置の厚さ方向に複数個の略球形形状の導電体端子を積層してなることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the conductor terminal is formed by laminating a plurality of substantially spherical conductor terminals in a thickness direction of the semiconductor device. 上記回路基板上に複数の半導体素子を有し、
下段にある半導体素子の上面に、上段にある半導体素子が接着剤を介して載置され、上記下段にある半導体素子と上記回路基板とはワイヤを介して接続されており、当該ワイヤの一部は当該接着剤に覆われていることを特徴とする請求項１に記載の半導体装置。 A plurality of semiconductor elements on the circuit board;
The upper semiconductor element is placed on the upper surface of the lower semiconductor element via an adhesive, and the lower semiconductor element and the circuit board are connected via a wire, and part of the wire The semiconductor device according to claim 1, wherein the semiconductor device is covered with the adhesive. 上記請求項１ないし４の何れかに記載の半導体装置上に、他の半導体装置もしくは他の電子部品が積層配置され、
上記半導体装置の上記外部端子接続部と、その上段の他の半導体装置もしくは他の電子部品とが導電体によって接続されていることを特徴とする半導体装置の積層体。 On the semiconductor device according to any one of claims 1 to 4, another semiconductor device or another electronic component is stacked and disposed.
A laminated body of a semiconductor device, wherein the external terminal connection portion of the semiconductor device and another semiconductor device or other electronic component on the upper side thereof are connected by a conductor. 回路基板上に半導体素子を載置し、該半導体素子と該回路基板とをワイヤを介して電気的に接続する工程と、
上記回路基板上に導電体端子を載置する工程と、
外部端子接続部を備えた接続用回路基板を、上記半導体素子上に接着剤を介して載置し、当該接着剤により上記ワイヤの一部を覆うと共に、上記接続用回路基板の下面と上記回路基板上に載置された導電体端子とを接続する工程と、
上記回路基板と上記接続用回路基板との間を樹脂封止する工程と、
上記回路基板の下面に外部接続端子を載置する工程を有することを特徴とする半導体装置の製造方法。 Placing a semiconductor element on a circuit board and electrically connecting the semiconductor element and the circuit board via a wire;
Placing a conductor terminal on the circuit board;
A connection circuit board having an external terminal connection portion is placed on the semiconductor element via an adhesive, and a part of the wire is covered with the adhesive, and the lower surface of the connection circuit board and the circuit Connecting a conductor terminal placed on the substrate;
A step of resin sealing between the circuit board and the connection circuit board;
A method for manufacturing a semiconductor device, comprising a step of placing an external connection terminal on a lower surface of the circuit board. 複数個分の半導体装置に対応する回路基板上に半導体素子を載置し、該半導体素子と該回路基板とをワイヤを介して電気的に接続する工程と、
上記回路基板上に導電体端子を載置する工程と、
外部端子接続部を備えた複数個分の半導体装置に対応する接続用回路基板を、上記半導体素子上に接着剤を介して載置し、当該接着剤により上記ワイヤの一部を覆うと共に、上記接続用回路基板の下面と上記回路基板上に載置された導電体端子とを接続する工程と、
上記回路基板と上記接続用回路基板との間を樹脂封止する工程と、
上記回路基板の下面に外部接続端子を載置する工程と、
上記複数個分がつながった半導体装置から個別の半導体装置を切り出す工程を有することを特徴とする半導体装置の製造方法。 Placing a semiconductor element on a circuit board corresponding to a plurality of semiconductor devices, and electrically connecting the semiconductor element and the circuit board via wires;
Placing a conductor terminal on the circuit board;
A circuit board for connection corresponding to a plurality of semiconductor devices having external terminal connection portions is placed on the semiconductor element via an adhesive, and a part of the wire is covered with the adhesive, and Connecting the lower surface of the circuit board for connection and a conductor terminal placed on the circuit board;
A step of resin sealing between the circuit board and the connection circuit board;
Placing external connection terminals on the lower surface of the circuit board;
A method of manufacturing a semiconductor device comprising a step of cutting out individual semiconductor devices from the plurality of semiconductor devices connected to each other.
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Publication number Priority date Publication date Assignee Title
JP2016529703A (en) * 2013-07-15 2016-09-23 インヴェンサス・コーポレイション Microelectronic assembly having stacked terminals joined by connectors extending through the seal

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JP2000294720A (en) * 1999-04-07 2000-10-20 Sharp Corp Semiconductor integrated circuit package
JP2003218283A (en) * 2002-01-22 2003-07-31 Sharp Corp Semiconductor device and method for manufacturing the same

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2000294720A (en) * 1999-04-07 2000-10-20 Sharp Corp Semiconductor integrated circuit package
JP2003218283A (en) * 2002-01-22 2003-07-31 Sharp Corp Semiconductor device and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016529703A (en) * 2013-07-15 2016-09-23 インヴェンサス・コーポレイション Microelectronic assembly having stacked terminals joined by connectors extending through the seal

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