JP2010136545A - High-voltage output driver and piezoelectric pump - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To cause a drive power source voltage to change depending on the amplitude of a drive signal to drive a piezoelectric element efficiently. <P>SOLUTION: A boosting circuit including Lvs, Q3, and D1 boosts a low-voltage signal power source to generate a high-voltage drive power source that is determined in accordance with a drive control signal for a piezoelectric element. A drive wave generating means is supplied with power from the signal power source, and generates a drive wave for the piezoelectric element having an amplitude corresponding to the drive control signal. Amplifiers AP1 and AP2 amplify the drive wave to obtain a drive signal having an amplitude corresponding to the drive control signal to drive the piezoelectric element. Drive power source voltage output from the boosting circuit is compared with the drive signal at a comparator CP8 to set the drive power source voltage higher than the drive signal by a given value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a high-voltage output driver that outputs a drive signal to a piezoelectric element, and a piezoelectric pump using the same.

  Conventionally, a diaphragm pump using a piezoelectric element has been proposed. This pump is called a piezoelectric pump, and is driven by reciprocating the piezoelectric element and reciprocating the diaphragm by sequentially changing the direction of voltage application to the piezoelectric element.

  In such a piezoelectric pump, a drive circuit that outputs a drive signal for the piezoelectric element is required, and in order to control the pump flow rate, it is necessary to control the applied voltage and cycle. Motor drive control includes drive current control using an inverter, but amplitude control of drive current that controls applied voltage is widely performed in simple drive control of a small motor.

JP-A-6-109068 JP-A-8-205563 Japanese Patent Laid-Open No. 2000-60847

  Here, the personal computer has a cooling fan for cooling a member such as a CPU, and the applied voltage to the fan motor is usually changed to adjust the strength of the fan. Piezoelectric pumps are small in size, and it is considered practically possible to configure a water cooling system for internal members of a personal computer. In this case, a circuit that efficiently obtains a high voltage output for driving the piezoelectric pump that effectively controls the discharge amount of the piezoelectric pump is desired.

  The present invention is a high-voltage output driver for driving a piezoelectric element, and boosts a low-voltage signal power supply to generate a high-voltage drive power supply determined according to a drive control signal for the piezoelectric element; A drive waveform generating means for generating a drive waveform of a piezoelectric element having an amplitude corresponding to the drive control signal using the signal power supply as a power supply; amplifying the drive waveform using the drive power supply as a power supply; and the drive control signal And an amplifier circuit that obtains a drive signal for driving the piezoelectric element, and sets the voltage of the drive power source that is the output of the booster circuit to a value that exceeds the drive signal by a predetermined value. It is characterized by.

  The booster circuit preferably boosts the drive waveform based on a drive waveform for a drive power source that is offset by a predetermined value.

  The booster circuit has a feedback loop that controls a voltage obtained by dividing the voltage of the drive power supply by a predetermined voltage division ratio so as to be the same as the drive waveform, and the amplifier circuit is a voltage of the drive signal. A feedback loop for controlling the voltage divided by a predetermined voltage dividing ratio to be the same as the driving waveform for the driving power supply, and the voltage dividing ratio of the booster circuit and the voltage dividing ratio of the amplifier circuit are made the same. Is preferred.

  The drive waveform generating means includes a digital-analog converter, and outputs the drive waveform from a digital value that changes over time, and the drive waveform for the drive power source that is higher in voltage by a predetermined value with respect to the same digital value. It is preferable to obtain

  In addition, the amplifier circuit includes an operational amplifier that compares the drive waveform with a feedback signal obtained by dividing the drive signal and makes both coincide with each other, and based on the feedback signal, the boost circuit It is preferable to set the voltage of the driving power source, which is the output of the above, to a value exceeding the driving signal by a predetermined value.

  The boosting circuit preferably boosts the driving waveform to a value that exceeds a predetermined value with respect to the higher one of the driving power supply driving waveform and the feedback signal based on a signal offset by a predetermined value.

  The present invention also includes a piezoelectric pump that includes the above-described high-voltage output driver and a piezoelectric element that is driven by a drive signal that is an output of the high-voltage output driver, and that is driven by reciprocating a diaphragm that uses the piezoelectric element. About.

  The piezoelectric element can be efficiently driven by changing the drive power supply voltage according to the amplitude of the drive signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

"Configuration of piezoelectric pump"
A configuration of a diaphragm pump (piezoelectric pump) using a piezoelectric element will be described with reference to FIG. Inside the pump casing 10, a diaphragm 12 whose periphery is fixed to the inner wall of the pump casing 10 and whose center side moves up and down is disposed, and a pump chamber 14 is formed on one side of the diaphragm 12. The pump chamber 14 is provided with an inlet 18 connected to the inflow passage 16 and an outlet 22 connected to the outflow passage 20. Between the inflow passage 16 and the inlet 18, a check valve 24 on the inflow side is provided. A check valve 26 on the outflow side is provided between the outflow passage 20 and the outflow port 22.

  Here, the diaphragm 12 has a structure in which piezoelectric elements PZ1 and PZ2 having electrodes on both surfaces are bonded to both the front and back surfaces of a thin metal plate M as shown in FIG. Then, an AC voltage of one phase (sine wave-like drive signal) is applied between the upper electrode of the piezoelectric element PZ1 and the lower electrode of the piezoelectric element PZ2, and the middle between the piezoelectric elements PZ1 and PZ2 An AC voltage (a sine wave-like drive signal having an opposite phase) having an opposite phase (180 degrees different) is applied to the metal plate M. As a result, the two piezoelectric elements PZ1 and PZ2 warp greatly when the applied voltage is large, and as shown in FIGS. 1 and 2, the diaphragm 12 vibrates up and down with the peripheral portion as a fulcrum and the center as the maximum amplitude. It will be.

  The check valve 24 on the inflow side allows the flow of fluid in the direction of flowing into the pump chamber 14 and blocks the opposite flow. On the other hand, the check valve 26 on the outflow side allows the flow of fluid in the direction of flowing out from the pump chamber 14 and blocks the opposite flow. Therefore, as shown in FIG. 1, the fluid in the inflow passage 16 is pushed out to the outflow passage 20 through the pump chamber 14 in accordance with the volume change of the pump chamber 14 accompanying the vibration of the diaphragm 12.

"Drive signal output circuit"
FIG. 3 shows a configuration of a drive signal output circuit that outputs a drive signal to the piezoelectric element PZ. The R-side input signal that is one drive waveform (sine wave-like AC waveform) is input to the positive input terminal of the buffer amplifier BF1. The output of the buffer amplifier BF1 is connected to the negative input terminal, and the R-side input signal is output as it is. The output of the buffer amplifier BF1 is input to the positive input terminal of the comparator (error amplifier) CP1. A feedback signal is input to the negative input terminal of the comparator CP1, and an error signal of both signals is obtained as an output of the comparator CP1. The obtained error signal is supplied to the output amplifier AP1 driven by a high power supply voltage, and the output of the output amplifier AP1 is supplied to the output terminal T1. An electrode on one side of the piezoelectric element PZ is connected to the output terminal T1, and is connected to the ground via the voltage dividing resistors R1 and R2. The middle point of the voltage dividing resistors R1 and R2 is connected to the negative input terminal of the comparator CP1 via the terminal T2, and the voltage obtained by dividing the output voltage is negatively fed back to the comparator CP1.

  Therefore, the comparator CP1 operates so that the output voltage of the voltage dividing resistors R1 and R2, which are feedback signals, coincides with the R-side input signal. Accordingly, the drive signal ROUT from the output terminal T1 is input to the R-side input. Depending on the signal.

  The F-side input signal is a signal (complementary signal) that is 180 degrees out of phase with the R-side input signal, and the F-side input signal is input to the F-side via the buffer amplifier BF2, the comparator CP2, and the output amplifier AP2. A high-voltage drive signal corresponding to the signal is supplied to the output terminal T3. The output terminal T3 is connected to the other electrode of the piezoelectric element PZ and connected to the ground via the voltage dividing resistors R3 and R4, and the midpoint voltage of the voltage dividing resistors R3 and R4 is negative to the comparator CP2. It has been returned. Therefore, the drive signal FOUT output from the output terminal T3 has a polarity opposite to that of the drive signal ROUT from the output terminal T1, and a pair of drive signals ROUT and FOUT whose phases are 180 degrees different from the electrodes on both surfaces of the piezoelectric element PZ. Will be applied. This piezoelectric element PZ constitutes the diaphragm 12 of the above-described piezoelectric pump, and the diaphragm 12 reciprocates. The piezoelectric pump described above has two piezoelectric elements PZ1 and PZ2. However, the piezoelectric element PZ may correspond to one of them, and the diaphragm 12 is configured by one piezoelectric element PZ. May be.

  Next, the drive power supply control signal is input to the positive input terminal of the comparator CP3. A feedback signal is input to the negative input terminal of the comparator CP3. The output of the comparator CP3 is input to the negative input terminal of the comparator CP4. A preset triangular wave is supplied to the positive input terminal of the comparator CP4. Therefore, a PWM signal having a duty ratio corresponding to the output voltage of the comparator CP3 is obtained at the output of the comparator CP4. That is, if the drive power supply control signal is higher than the feedback signal, the output voltage of the comparator CP3 increases, and a PWM signal with a low duty ratio (H level period) is output from the comparator CP4. The drive power supply control signal is generated based on a control power supply voltage VCC for controlling the drive of the piezoelectric element PZ, as will be described later.

  The output of the comparator CP4 is supplied to the gates of the p-channel transistor Q1 and the n-channel transistor Q2. The transistor Q1 has a source connected to the terminal T5, a drain connected to the drain of the transistor Q2, and a source of the transistor Q2 connected to the ground. The connection point between the drains of the transistors Q1 and Q2 is connected to the terminal T6.

  The terminal T5 is connected to the anode of an external diode D1 via an external coil Lvs, and the cathode of the diode D1 is connected to the ground via an external capacitor C1. Further, the gate of the n-channel transistor Q3 is connected to the terminal T6, the drain of the transistor Q3 is connected to the connection point of the coil Lvs and the diode D1, and the source is connected to the ground.

  Therefore, when the PWM signal output from the comparator CP4 is at the H level, the transistor Q2 is turned on and the terminal T6 is at the L level, the transistor Q3 is turned off. When the PWM signal is at the L level, the transistor Q2 is turned off and the terminal T6 is turned on. Becomes H level and the transistor Q3 is turned on. When the transistor Q3 is turned on, energy is accumulated in the coil Lvs, and when the transistor Q3 is turned off, the capacitor C1 is charged according to the energy accumulated in the coil Lvs. Therefore, the longer the L level period in the output from the comparator CP4, the larger the charge amount to the capacitor C1, and the higher the drive power supply voltage that is the output from the capacitor C1. If a transistor is provided in parallel with the diode D1, it becomes easy to lower the drive power supply voltage by switching.

  The upper side of the capacitor C1 (electrode connected to the cathode of the diode D1) is connected to a terminal T7, and this terminal T7 is supplied to the output amplifiers AP1 and AP2 as a drive power supply voltage. The upper side of the capacitor C1 is connected to the ground through external voltage dividing resistors R5 and R6. The midpoint of the voltage dividing resistors R5 and R6 is connected to a terminal T8 via an external resistor R7 and a capacitor C2. The terminal T8 is connected to the negative input terminal of the comparator CP4. The resistor R7 and the capacitor C2 constitute a high-pass filter, which removes the high frequency component of the drive power supply voltage output. Further, the midpoint of the voltage dividing resistors R5 and R6 is connected to the terminal T9, and this terminal T9 is connected to the negative input terminal of the comparator CP3. Therefore, a voltage obtained by dividing the drive power supply voltage by the voltage dividing resistors R5 and R6 becomes a feedback signal (feedback signal) to be compared with the drive power supply control signal so that the voltage of the feedback signal matches the voltage of the drive power supply control signal. The drive power supply voltage is controlled.

  In this way, the drive power supply voltage can be arbitrarily controlled by the drive power supply control signal. As a result, the amplitudes of the drive signals ROUT and FOUT, which are outputs from the terminals T1 and T3, are controlled. As will be described later, the drive power control signal is supplied to the driver from the outside as the power supply voltage VCC.

  FIG. 4 shows the states of the drive signals ROUT and FOUT. By reducing the drive power supply voltage output, the amplitudes of ROUT and FOUT are reduced. Thereby, the movement of the piezoelectric element PZ is controlled, and the amplitude of the diaphragm of the piezoelectric pump is controlled, so that the discharge amount of the pump can be controlled.

"Configuration of output amplifier AP"
5 and 6 show configuration examples of the output amplifier AP. A constant current is supplied from ICOM, which is supplied to the drain and gate of n-channel transistor Q11. The source of the transistor Q11 is connected to the ground (PGND). The gates of the transistors Q11 are commonly connected to the gates of n-channel transistors Q12, Q13, Q14 whose sources are connected to the ground (PGND). Therefore, the transistors Q12, Q13, and Q14 form a current mirror with respect to the transistor Q11, and the same constant current flows through these transistors Q11 to Q14.

  The drain of the transistor Q12 is connected to the drain of the p-channel transistor Q15, and the source of the transistor Q15 is connected to the drive power supply VS. The drain and gate of the transistor Q15 are short-circuited, and the gates of p-channel transistors Q16 and Q17 whose sources are connected to VS are connected to this gate. Therefore, the same constant current flows through these transistors Q16 and Q17 as those flowing through the transistor Q11.

  The drain of the transistor Q13 is connected to the drive power supply VS via the p-channel transistors Q18 and Q19 whose two drains and gates are short-circuited, and the drains of the transistors Q13 and Q18 are connected to the gate of the p-channel transistor Q20. Has been. The drain of the transistor Q17 is connected to a terminal RF connected to an external ground via n-channel transistors Q21 and Q22 in which the two drains and gates are short-circuited. A connection point between the transistors Q17 and Q21 is connected to the gate of the n-channel transistor Q23.

  The source of the transistor Q20 and the drain of the transistor Q23 are connected in common to the drain of the transistor Q16 and to the gate of the p-channel transistor Q24. Further, the drain of the transistor Q20 and the source of the transistor Q23 are connected in common to the drain of the transistor Q14 and to the gate of the n-channel transistor Q25. The drive current Idr is supplied from the ICTLF terminal to the drain of the transistor Q20, the source of the transistor Q23, the drain of the transistor Q14, and the gate of the n-channel transistor Q25. That is, the ICTLF terminal is connected to the output of the comparator CP1 (or the comparator CP2).

  The source of the transistor Q24 is connected to the drive power supply VS, the drain is connected to the drain of the transistor Q25 and the output terminal OUT (T1 or T3), and the source of the transistor Q25 is connected to the terminal RF. Yes.

  In such a circuit, a current obtained by dividing the constant current flowing through the transistor Q16 flows through the transistor Q20 and the transistor Q23. In addition, a constant current flowing through the transistor Q13 flows through the transistors Q19 and Q18, and a current flowing through the transistor Q17 flows through the transistors Q21 and Q22. Therefore, normally, the currents flowing through the transistors Q20 and Q23 are equal.

  When the drive current Idr is a current Idr + flowing toward the gate of the transistor Q25, as shown in FIG. 5, the transistor Q25 is turned on, a current flows in a direction of drawing a current from the output terminal OUT, and the output terminal OUT Move to the L level. At this time, since the sum of the currents flowing through the transistors Q20 and Q23 is equal to the constant current flowing through the transistor Q14, the transistor Q24 is off.

  On the other hand, if the drive current Idr is the current Idr− that flows in the direction of pulling out from the gate of the transistor Q25, the drain current of the transistor Q23 increases as shown in FIG. 6, the transistor Q24 is turned on, and the output terminal OUT Current flows in the direction of discharging current, and the output terminal OUT moves to the H level side.

  In this way, the output transistors Q24 and Q25 are controlled according to the current flowing through the ICTLF, and the output from the output terminal OUT is controlled. The output amplifier AP functions as a high withstand voltage output unit that obtains an output by power from the drive power supply VS. Therefore, the amplifiers shown in FIGS. 5 and 6 are prepared as the output amplifiers AP1 and AP2 in FIG. 3, and the outputs of the comparators CP1 and CP2 are input to the ICTLF of the respective amplifiers. ROUT and FOUT can be obtained respectively.

  The power supply voltage of the signal system is, for example, about 5V, and the drive power supply VS is, for example, about 200V.

“Configuration of VCC-linked DAC”
In a conventional apparatus, there is a case in which a circuit that can output a power supply voltage VCC that is a control power supply voltage for controlling fan driving is already prepared for fan drive control. In this case, it is preferable to generate a signal for controlling the piezoelectric element PZ in accordance with the power supply voltage VCC.

  FIG. 7 shows a configuration suitable for such a case. A terminal T11 to which a power supply VCC whose voltage inputted from the outside is appropriately changed according to the drive request of the pump is connected to the ground via a voltage dividing resistor composed of resistors R11 and R12 connected in series. The middle point of the voltage dividing resistors R11 and R12 is input to the positive input terminal of the buffer amplifier BF11 whose output is short-circuited to the negative input terminal, and this output is the power supply VDAC of the D / A converter 30.

  In this example, the reference V1 is input to the positive input terminal, the middle point of the voltage dividing resistors R11 and R12 is connected to the negative input terminal, and the middle point of the voltage dividing resistors R11 and R12 is output via the diode D11. And the reference V2 is input to the positive input terminal, the midpoint of the voltage dividing resistors R11 and R12 is connected to the negative input terminal, and the output of the voltage dividing resistors R11 and R12 is connected via the diode D12. And a comparator CP12 connected to the midpoint. The diode D11 passes only the current flowing from the middle point of the voltage dividing resistors R11 and R12 toward the output of the comparator CP11, and the diode D12 flows from the output of the comparator CP11 toward the middle point of the voltage dividing resistors R11 and R12. Only shed. Therefore, the midpoint voltage of the voltage dividing resistors R11 and R12 is clipped by the reference voltages V1 and V2. Therefore, the power supply VDAC changes as shown in FIG. 8 as the power supply voltage VCC changes. That is, the power supply VDAC linearly changes from V2 to V1 when the power supply voltage VCC is 0 to V2 (R11 + R12) / R12, and between V2 (R11 + R12) / R12 to V1 (R11 + R12) / R12, V1 At (R11 + R12) / R12 or higher, it is fixed at V1.

  FIG. 9 shows the configuration of the D / A converter 30. A resistor corresponding to the number of bits of the input digital signal is connected in series between the power supply VDAC and the ground. Two switches are provided corresponding to the connection points between the resistors, and the ends of the R-side switch group SWr on one side that are not on the resistance side are commonly connected to output the R-side signal and the other side. The ends of the F-side switch group SWf that are not on the resistance side are commonly connected to output an F-side signal.

  A counter circuit 32 is provided to control the R side and F side switch groups. The counter 32 repeats up-counting and down-counting a predetermined clock. For example, the 512-stage count value is repeatedly output in order of 0 → 511 → 0 → 511. The outputs of these counters are associated with each other so that the R-side switch group SWr and the F-side switch group SWf have the opposite outputs. That is, the output of the F-side switch group SWf is set to 511 if the output of the R-side switch group SWr is 0 when the output of the counter 32 is 0.

  Accordingly, the R side signal and the F side signal become complementary sine curves that sequentially change with respect to one clock, as shown in the figure. As the power supply VDAC changes, the amplitudes of the R side signal and the F side signal change in conjunction with each other. Therefore, an R-side signal and an F-side signal whose amplitude changes according to the power supply VCC are obtained at the output of the D / A converter 30. Further, the maximum output of the D / A converter 30 is output as a drive power supply control signal.

  9 is input to the buffer amplifiers BF1 and BF2 and the comparator CP3 in FIG. Then, by appropriately setting the ratio of the voltage dividing resistors R1, R2, R3, R4, R5, and R6, the discharge amount of the piezoelectric pump can be controlled to the target value according to the input VCC. Become.

  In FIG. 9, the R-side signal and the F-side signal are output from the D / A converter 30 as they are. However, the R side signal and the F side signal are vertically symmetrical. Accordingly, only half (180 degrees) of output can be output from the D / A converter 30, and the output of the other half can be inverted. As a result, the resistor string in the D / A converter 30 can be halved.

  Thus, in this embodiment, the drive power supply control signal is generated according to the power supply voltage VCC to control the boosting. Here, the drive power supply voltage needs to be larger than the drive signals ROUT and FOUT, but need not be constant. In particular, when the driving power supply voltage is constant, as shown in FIG. 10, when the difference from the driving signal is large, the upper transistors of the amplifiers AP1 and AP2 handle the difference, and the power consumption here increases. There is a problem.

  Therefore, it is preferable to change the drive power control signal in accordance with the waveform of the drive signal as shown in FIG. That is, as shown in FIG. 12, a switch 34 is provided to generate a signal that takes the larger of the R-side signal and the F-side signal (a signal that only the peak side continues), and this is used as a drive power control signal. This drive control signal is supplied to the booster circuit in FIG. For this reason, as shown in FIG. 11, only the peaks where the drive power supply voltage is slightly higher than the envelopes of the drive signals ROUT and FOUT are continued. As a result, loss in the output transistor in driving the piezoelectric element can be reduced and efficient driving of the piezoelectric element can be achieved.

  Here, the drive power supply voltage needs to be higher than the drive signal by a predetermined value. For this purpose, the driving power supply voltage can be set higher than the driving signal by a predetermined value by changing the voltage dividing ratio of the resistors R1 (R3): R2 (R4) and the voltage dividing ratio of the resistors R5: R6 in FIG. it can. That is, the drive power supply voltage can be set higher than the drive signal by making R5 / (R5 + R6) smaller than R1 / (R1 + R2).

  However, when the relationship between the drive power supply voltage and the voltage of the drive signal is set by the voltage dividing ratio in this way, the drive power supply voltage has a larger difference at the peak of the drive signal as shown in FIG.

  Therefore, in the present embodiment, as shown in FIG. 12, when the drive voltage control signal is output from the D / A converter 30 that outputs the drive waveform, the output is shifted from the drive waveform. For example, the D / A converter 30 can be output in the range of 0 to 521, and the drive waveform is turned on sequentially (switching from 0 → 511 → 0 →) in order to generate a sine wave. The drive voltage control signal is output, and the switches corresponding to 265 to 521 are sequentially turned on (repeated 265 → 521 →) to obtain a drive voltage control signal that is only a mountain and is higher by 10 as a digital value. .

  As a result, as shown in FIG. 14, the drive power supply control signal can be output as a value higher by a predetermined value than the higher one of the R side signal and the F side signal.

  By controlling the boosting of the driving power supply voltage with the offset driving voltage control signal obtained in this way, the voltage dividing ratio of the resistors R1 (R3): R2 (R4) and the voltage dividing ratio of the resistors R5: R6 are the same. As shown in FIG. 15, the drive power supply voltage can be controlled to be higher than the drive signal by a predetermined value, and the difference can always be set to the same value.

"Configuration of drive power supply voltage control"
In FIG. 16, instead of the comparator CP3 (FIG. 3) that compares the drive power supply control signal and the feedback signal obtained by dividing the drive power supply voltage, the comparators CP1 and CP2 that divided the drive signals ROUT and FOUT are supplied. A configuration employing a comparator CP8 that also compares feedback signals is shown. That is, at the positive input terminal of the comparator CP8, a signal obtained by offsetting a drive power control signal having a predetermined offset and a feedback signal to the comparator CP1 obtained by dividing the drive signal ROUT by the resistors R1 and R2 by the offset power supply OB4. The three signals of the feedback signal to the comparator CP2 obtained by dividing the driving signal FOUT by the resistors R3 and R4 and offset by the offset power supply OB5 are input, and the driving power supply voltage input to the negative input terminal. Are compared by resistors R5 and R6.

  The comparator CP8 controls the divided voltage of the drive power supply voltage that is negatively fed back to the highest voltage among the three input signals. Therefore, even when the voltage of the drive signal becomes high for some reason, the drive power supply voltage is controlled to be higher than that to ensure proper driving of the piezoelectric element. In addition, since the signal offset from the drive power supply control signal is also supplied to the positive input terminal, even when the drive signal does not rise when the power supply rises, the drive power supply control signal is compared with the feedback signal to the negative input terminal. Thus, an appropriate drive power supply voltage can be raised.

"Comparator Configuration"
FIG. 17 shows the configuration of the comparator CP8. The other end of the constant current source CS11 having one end connected to the power supply is connected to one end of the resistor R41. The other end of the resistor R41 is connected to the emitter of the PNP transistor Q41, and the collector of the transistor Q41 is connected to the ground. A drive power supply control signal is supplied to the base of the transistor Q41. Similarly, the other end of the constant current source CS12 having one end connected to the power supply is connected to the emitter of the PNP transistor Q42 via the resistor R42, and the collector of the transistor Q42 is connected to the ground. A signal is supplied to the base of the transistor Q42 by dividing the drive signal ROUT by the resistors R1 and R2. Further, the other end of the constant current source CS13 having one end connected to the power source is connected to the emitter of the PNP transistor Q43 via the resistor R43, and the collector of the transistor Q43 is connected to the ground. A signal is supplied to the base of the transistor Q43 by dividing the drive signal FOUT by the resistors R3 and R4.

  The upper sides (constant current sources CS11, CS12, CS13 side) of the resistors R41, R42, R43 are connected to the bases of the NPN transistors Q44, Q45, Q46, respectively. The collectors of the transistors Q44, Q45 and Q46 are commonly connected to the collector of a PNP transistor Q47 whose emitter is connected to the power supply and whose base collector is short-circuited. The emitters of the transistors Q44, Q45, and Q46 are commonly connected to the collector of an NPN transistor Q48 whose emitter is connected to the ground. Here, the base of the transistor Q48 is connected to the base of an NPN-type current mirror input-side transistor (not shown) in which the base is short-circuited between the base collector and the emitter is connected to the ground and a constant current flows. Apply constant current.

  The base of the transistor Q47 is connected to the base of a PNP transistor Q49 whose emitter is connected to the power supply, and the collector of the transistor Q49 is connected to the collector of the NPN transistor Q50. The emitter of the transistor Q50 is connected to the collector of the transistor q48. Therefore, the transistor Q47 and the transistor Q49 constitute a current mirror to pass the same current, and the transistors Q44, Q45, Q46 and the transistor Q50 function as differential transistors.

  The base of the transistor Q50 is connected to one end of a constant current source CS14 connected to the power source at the other end, and to the emitter of a PNP transistor Q51 whose collector is connected to the ground. The base of the transistor Q51 is connected to a negative input terminal IN to which a negative feedback signal obtained by dividing the drive power supply voltage by resistors R5 and R6 is supplied.

  The connection point between the collector of the transistor Q49 and the collector of the transistor Q50 is connected to the collector of a PNP transistor Q52 whose emitter is connected to the power supply and whose base collector is short-circuited. The base of the transistor Q52 is connected to the base of a PNP transistor Q53 whose emitter is connected to the power supply, and the collector of this transistor Q53 is connected to the collector of the NPN transistor Q54 whose emitter is connected to the ground and the output terminal OUT It is connected to the. The base of the transistor Q54 is connected to the base of the current mirror input side transistor together with the base of the transistor Q48, and a constant current flows.

  The transistor Q51 operates in response to the negative feedback signal, whereby the base current of the transistor Q50 is controlled and the current flowing through the transistor Q50 is controlled. Since the transistors Q47 and Q49 function as current mirrors and flow the same current, the currents flowing through the transistors Q52 and Q53 change according to the current flowing through the transistor Q50, and the current flowing through the output OUT is controlled.

  On the other hand, the emitters of the transistors Q44, Q45, and Q46 are commonly connected to the emitter of the transistor Q50. Therefore, the base voltage of the transistor Q44, Q45, Q46 that is turned on and the base potential of the transistor Q50 are the same. Thus, the current of the transistor Q50 is controlled. That is, the transistors Q44, Q45, and Q46 are connected in parallel, and the drive power control signal, the drive signal ROUT, and the drive signal FOUT are supplied to the bases, respectively. Therefore, the transistor having the highest base potential is turned on, and the base voltage of the transistor and the base potential of the transistor Q50 are the same.

  Here, a voltage drop occurs according to the current flowing through the resistors R41, R42, and R43, and therefore the voltage drops at these resistors R41, R42, and R43 correspond to the offset voltages OB1, OB4, and OB5. Further, VBE of transistors Q41, Q42, and Q43 is canceled with VBE of transistor Q51.

  As described above, according to the present embodiment, driving is performed based on a voltage obtained by adding a certain offset to the voltage of the highest signal among the three signals of the driving power control signal, the driving signal ROUT, and the driving signal FOUT. The power supply voltage can be controlled. Therefore, even when the drive signal becomes high, the drive power supply voltage can be raised following that.

It is a figure which shows the structure of a piezoelectric pump. It is a figure which shows the structure of the diaphragm of a piezoelectric pump. It is a figure which shows the structure of the output part of a high voltage output driver. It is a figure which shows the waveform of a drive signal. It is a figure which shows the structure of an output amplifier. It is a figure which shows the structure of an output amplifier. It is a figure which shows the structure for the output of power supply VDAC. It is a figure which shows the characteristic with respect to the power supply VCC of power supply VDAC. It is a figure which shows the structure of the D / A converter which obtains the output of the output amplitude according to power supply VDAC. It is a figure which shows the waveform of a drive power supply voltage, a drive signal, and output current. It is a figure which shows the waveform of a drive power supply voltage at the time of changing a drive power supply voltage according to a drive signal, a drive signal, and an output current. It is a figure which shows the structure which changes a drive power supply control signal according to a R side signal and a F side signal. It is a figure which shows the waveform of a drive power supply voltage at the time of changing a drive power supply voltage according to the feedback signal of a drive signal, a drive signal, and an output current. It is a figure which shows the waveform of the drive power supply control signal, R side signal, and F side signal in the structure of FIG. It is a figure which shows the waveform of a drive power supply voltage, a drive signal, and an output current at the time of changing a drive power supply voltage according to the feedback signal of a drive power supply control signal. It is a figure which shows the structure of the output amplifier which added the structure for controlling a drive power supply voltage. It is a figure which shows the structure of comparator CP8.

Explanation of symbols

  10 pump casing, 12 diaphragm, 14 pump chamber, 16 inlet, 18 inlet, 20 outlet, 22 outlet, 24, 26 check valve, 30 converter, 32 counter circuit, AP1, AP2 output amplifier, BF1, BF2 , BF11 buffer amplifier, C1, C2 capacitors, CP1, CP2, CP3, CP4, CP8, CP11, CP12 comparators, CS11-CS13 constant current sources, D1, D11, D12 diodes, Q1-Q3, Q11-Q25, Q41-Q54 Transistor, R1-R7, R11, R12, R41-43 resistors.

Claims (7)

A high voltage output driver for driving a piezoelectric element,
A step-up circuit for boosting a low-voltage signal power supply and generating a high-voltage drive power supply determined according to a drive control signal for the piezoelectric element;
Drive waveform generating means for generating a drive waveform of a piezoelectric element having an amplitude corresponding to the drive control signal, using the signal power supply as a power supply;
An amplifier circuit that amplifies the drive waveform using the drive power supply as a power supply, and obtains a drive signal that drives the piezoelectric element with an amplitude according to the drive control signal;
Have
A high-voltage output driver characterized in that the voltage of the drive power supply, which is the output of the booster circuit, is set to a value that exceeds the drive signal by a predetermined value. The high voltage output driver according to claim 1,
The high voltage output driver characterized in that the boosting circuit boosts the driving waveform based on a driving waveform for driving power supply offset by a predetermined value. The high voltage output driver according to claim 2,
The booster circuit has a feedback loop that controls a voltage obtained by dividing the voltage of the drive power supply by a predetermined voltage division ratio to be the same as the drive waveform;
The amplifier circuit has a feedback loop that controls the voltage obtained by dividing the voltage of the drive signal at a predetermined voltage division ratio to be the same as the drive waveform for the drive power source,
A high-voltage output driver, wherein the voltage dividing ratio of the booster circuit and the voltage dividing ratio of the amplifier circuit are the same. The high voltage output driver according to claim 3,
The drive waveform generation means includes a digital-analog converter, and outputs the drive waveform from a digital value that changes with time, and obtains the drive waveform for the drive power source whose voltage is higher by a predetermined value with respect to the same digital value. A high-voltage output driver characterized by that. The high voltage output driver according to claim 1,
The amplifier circuit has an operational amplifier that compares the drive waveform with a feedback signal obtained by dividing the drive signal and operates to match the two.
A high-voltage output driver characterized in that, based on the feedback signal, the voltage of the drive power supply that is the output of the booster circuit is set to a value that exceeds the drive signal by a predetermined value. The high voltage output driver according to claim 5,
The high voltage output driver, wherein the booster circuit boosts the driving waveform to a value that exceeds a predetermined value with respect to the higher one of the driving waveform for driving power supply and the feedback signal based on a signal offset by a predetermined value with respect to the driving waveform. A high voltage output driver according to any one of claims 1 to 6 and a piezoelectric element driven by a drive signal which is an output of the high voltage output driver,
A piezoelectric pump, which is driven by reciprocating a diaphragm using the piezoelectric element.

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