JP2010104132A - High-voltage output driver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively detect a connection error of a load even if the a drive power voltage changes. <P>SOLUTION: In a high-voltage output driver, the drive power voltage is changed according to a control signal. Amplifiers AP1 and AP2 output drive currents to be supplied from the drive power voltage to a load PZ. A detected voltage according to a flowing current is generated in a current detecting resistor R20. A comparator CP51 compares the detected voltage with its threshold, and outputs a frequency signal according to the change of the detected voltage on the basis of the comparison results. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a high-voltage output driver that outputs a drive signal to a load.

  Conventionally, a diaphragm pump using a piezoelectric element has been proposed. The pump reciprocates the diaphragm by reciprocating the piezoelectric element by sequentially changing the direction of voltage application to the piezoelectric element.

  Such a diaphragm pump requires a high-voltage output driver that obtains a high-voltage drive signal for the piezoelectric element. In order to control the pump flow rate, it is necessary to control the applied voltage and cycle. On the other hand, in the control of a load such as a normal motor, the drive control is often performed by controlling the amplitude of the supplied current, and it is considered preferable to perform the amplitude control also in the output control of the piezoelectric element.

JP-A-6-109068 JP-A-8-205563 Japanese Patent Laid-Open No. 2000-60847

  Here, in the control of the motor, the rotation control is performed by obtaining the FG signal related to the rotation. When amplitude control is performed on a piezoelectric element as described above, if there is an FG signal, the control device can drive the piezoelectric element in the same way as driving a motor.

  The present invention boosts a power supply voltage to generate a drive power supply voltage, and outputs a drive current generation circuit that changes the drive power supply voltage according to a control signal, and a drive signal supplied from the drive power supply voltage to a load. An output circuit, a current detection resistor that generates a detection voltage corresponding to the current flowing through the load, a comparison circuit that compares the detection voltage with a threshold value, and obtains a frequency signal indicating the drive frequency of the load from the comparison result; The threshold value is changed according to the control signal.

  Further, it is preferable that the drive signal has a pair of sinusoidal shapes that change complementarily, and a voltage corresponding to a difference between the two is applied to the load.

  In addition, it is preferable that an error signal indicating an error state in load driving and the frequency signal are input and an AND gate that takes a logical product of both is provided, and output of the frequency signal is stopped when an error occurs.

  Further, it is preferable that the comparison circuit detects a load short-circuit when the detection voltage is larger than the threshold value.

  Further, it is preferable that the comparison circuit detects a load open when the detection voltage is smaller than the threshold value.

  According to the present invention, suitable abnormality detection can be performed even if the drive power supply voltage changes.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

"Configuration of piezoelectric pump"
A configuration of a diaphragm pump (piezoelectric pump) using a piezoelectric element will be described with reference to FIG. Inside the pump casing 10, a diaphragm 12 whose periphery is fixed to the inner wall of the pump casing 10 and whose center side moves up and down is disposed, and a pump chamber 14 is formed on one side of the diaphragm 12. The pump chamber 14 is provided with an inlet 18 connected to the inflow passage 16 and an outlet 22 connected to the outflow passage 20. Between the inflow passage 16 and the inlet 18, a check valve 24 on the inflow side is provided. A check valve 26 on the outflow side is provided between the outflow passage 20 and the outflow port 22.

  Here, the diaphragm 12 has a structure in which piezoelectric elements PZ1 and PZ2 having electrodes on both surfaces are bonded to both the front and back surfaces of a thin metal plate M as shown in FIG. Then, an AC voltage of one phase (sine wave-like drive signal) is applied between the upper electrode of the piezoelectric element PZ1 and the lower electrode of the piezoelectric element PZ2, and the middle between the piezoelectric elements PZ1 and PZ2 An AC voltage (a sine wave-like drive signal having an opposite phase) having an opposite phase (180 degrees different) is applied to the metal plate M. As a result, the two piezoelectric elements PZ1 and PZ2 warp greatly when the applied voltage is large, and as shown in FIGS. 1 and 2, the diaphragm 12 vibrates up and down with the peripheral portion as a fulcrum and the center as the maximum amplitude. It will be.

  The check valve 24 on the inflow side allows the flow of fluid in the direction of flowing into the pump chamber 14 and blocks the opposite flow. On the other hand, the check valve 26 on the outflow side allows the flow of fluid in the direction of flowing out from the pump chamber 14 and blocks the opposite flow. Therefore, as shown in FIG. 1, the fluid in the inflow passage 16 is pushed out to the outflow passage 20 through the pump chamber 14 in accordance with the volume change of the pump chamber 14 accompanying the vibration of the diaphragm 12.

"Drive signal output circuit"
FIG. 3 shows a configuration of a drive signal output circuit that outputs a drive signal to the piezoelectric element PZ. The R-side input signal that is one drive waveform (sine wave-like AC waveform) is input to the positive input terminal of the buffer amplifier BF1. The output of the buffer amplifier BF1 is connected to the negative input terminal, and the R-side input signal is output as it is. The output of the buffer amplifier BF1 is input to the positive input terminal of the comparator (error amplifier) CP1. A feedback signal is input to the negative input terminal of the comparator CP1, and an error signal of both signals is obtained at the output of the comparator CP1. The obtained error signal is supplied to the output amplifier AP1 driven by a high power supply voltage, and the output of the output amplifier AP1 is supplied to the output terminal T1. An electrode on one side of the piezoelectric element PZ is connected to the output terminal T1, and is connected to the ground via the voltage dividing resistors R1 and R2. The middle point of the voltage dividing resistors R1 and R2 is connected to the negative input terminal of the comparator CP1 via the terminal T2, and the voltage obtained by dividing the output voltage is negatively fed back to the comparator CP1.

  Therefore, the comparator CP1 operates so that the output voltage of the voltage dividing resistors R1 and R2, which are feedback signals, coincides with the R-side input signal. Accordingly, the drive signal ROUT from the output terminal T1 is input to the R-side input. Depending on the signal.

  The F-side input signal is a signal (complementary signal) that is 180 degrees out of phase with the R-side input signal, and the F-side input signal is input to the F-side via the buffer amplifier BF2, the comparator CP2, and the output amplifier AP2. A high-voltage drive signal corresponding to the signal is supplied to the output terminal T3. The output terminal T3 is connected to the other electrode of the piezoelectric element PZ and connected to the ground via the voltage dividing resistors R3 and R4, and the midpoint voltage of the voltage dividing resistors R3 and R4 is negative to the comparator CP2. It has been returned. Therefore, the drive signal FOUT output from the output terminal T3 has a polarity opposite to that of the drive signal ROUT from the output terminal T1, and a pair of drive signals ROUT and FOUT whose phases are 180 degrees different from the electrodes on both surfaces of the piezoelectric element PZ. Will be applied. This piezoelectric element PZ constitutes the diaphragm 12 of the above-described piezoelectric pump, and the diaphragm 12 reciprocates. The piezoelectric pump described above has two piezoelectric elements PZ1 and PZ2. However, the piezoelectric element PZ may correspond to one of them, and the diaphragm 12 is configured by one piezoelectric element PZ. May be.

  Next, the drive power supply control signal is input to the positive input terminal of the comparator CP3. A feedback signal is input to the negative input terminal of the comparator CP3. The output of the comparator CP3 is input to the negative input terminal of the comparator CP4. A preset triangular wave is supplied to the positive input terminal of the comparator CP4. Therefore, a PWM signal having a duty ratio corresponding to the output voltage of the comparator CP3 is obtained at the output of the comparator CP4. That is, if the drive power supply control signal is higher than the feedback signal, the output voltage of the comparator CP3 increases, and a PWM signal with a low duty ratio (H level period) is output from the comparator CP4. The drive power supply control signal is generated based on a control power supply voltage VCC for controlling the drive of the piezoelectric element PZ, as will be described later.

  The output of the comparator CP4 is supplied to the gates of the p-channel transistor Q1 and the n-channel transistor Q2. The transistor Q1 has a source connected to the terminal T5, a drain connected to the drain of the transistor Q2, and a source of the transistor Q2 connected to the ground. The connection point between the drains of the transistors Q1 and Q2 is connected to the terminal T6.

  The terminal T5 is connected to the anode of an external diode D1 via an external coil Lvs, and the cathode of the diode D1 is connected to the ground via an external capacitor C1. Further, the gate of the n-channel transistor Q3 is connected to the terminal T6, the drain of the transistor Q3 is connected to the connection point of the coil Lvs and the diode D1, and the source is connected to the ground.

  Therefore, when the PWM signal output from the comparator CP4 is at the H level, the transistor Q2 is turned on and the terminal T6 is at the L level, the transistor Q3 is turned off. When the PWM signal is at the L level, the transistor Q2 is turned off and the terminal T6 is turned on. Becomes H level and the transistor Q3 is turned on. When the transistor Q3 is turned on, energy is accumulated in the coil Lvs, and when the transistor Q3 is turned off, the capacitor C1 is charged according to the energy accumulated in the coil Lvs. Therefore, the longer the L level period in the output from the comparator CP4, the larger the charge amount to the capacitor C1, and the higher the drive power supply voltage that is the output from the capacitor C1. If a transistor is provided in parallel with the diode D1, it becomes easy to lower the drive power supply voltage by switching.

  The upper side of the capacitor C1 (electrode connected to the cathode of the diode D1) is connected to a terminal T7, and this terminal T7 is supplied to the output amplifiers AP1 and AP2 as a drive power supply voltage. The upper side of the capacitor C1 is connected to the ground through external voltage dividing resistors R5 and R6. The midpoint of the voltage dividing resistors R5 and R6 is connected to a terminal T8 via an external resistor R7 and a capacitor C2. The terminal T8 is connected to the negative input terminal of the comparator CP4. The resistor R7 and the capacitor C2 constitute a high-pass filter, and the control of the drive power supply voltage is stabilized. Further, the midpoint of the voltage dividing resistors R5 and R6 is connected to the terminal T9, and this terminal T9 is connected to the negative input terminal of the comparator CP3. Therefore, a voltage obtained by dividing the drive power supply voltage by the voltage dividing resistors R5 and R6 becomes a feedback signal (feedback signal) to be compared with the drive power supply control signal so that the voltage of the feedback signal matches the voltage of the drive power supply control signal. The drive power supply voltage is controlled.

  In this way, the drive power supply voltage can be arbitrarily controlled by the drive power supply control signal. As a result, the amplitudes of the drive signals ROUT and FOUT, which are outputs from the terminals T1 and T3, are controlled. As will be described later, the drive power control signal is supplied to the driver from the outside as the power supply voltage VCC.

  FIG. 4 shows the states of the drive signals ROUT and FOUT. By reducing the drive power supply voltage, the amplitudes of ROUT and FOUT are reduced. Thereby, the movement of the piezoelectric element PZ is controlled, and the amplitude of the diaphragm of the piezoelectric pump is controlled, so that the discharge amount of the pump can be controlled.

  Here, FIG. 5 shows a configuration of output portions of the output amplifiers AP1 and AP2. The output amplifier AP1 includes a p-channel output transistor Q31 and an n-channel transistor Q32. The output amplifier AP2 includes a p-channel output transistor Q33 and an n-channel transistor Q34. The source of the transistor Q31 is connected to the drive power supply, and the drain of the transistor Q31 is connected to the drain of the transistor Q32. The source of the transistor Q33 is connected to the drive power supply, and the drain of the transistor Q33 is connected to the drain of the transistor Q34. The sources of the transistors Q32 and Q34 are connected in common and connected to the ground via the current detection resistor R21.

  A terminal T1 is connected to a connection point between the drains of the transistors Q31 and Q32, a terminal T3 is connected to a connection point between the drains of the transistors Q33 and Q34, and the piezoelectric element PZ is connected between the terminals T1 and T3. It is connected.

  Therefore, when the transistors Q33 and Q32 are turned on, a current flows through the resistor 21 through the transistor Q33, the piezoelectric element PZ, and the transistor Q32 as shown in the figure, and the voltage above the resistor 21 is detected. In addition, since the piezoelectric element PZ functions as a capacitor, the drive current that flows as described above flows as an alternating current.

  FIG. 6 shows the voltages ROUT and FOUT applied to the piezoelectric element PZ in the driving state and the waveform of the driving current flowing through the piezoelectric element PZ. In this way, a complementary sine wave is applied to the piezoelectric element PZ, and a drive current that is 90 degrees out of phase flows therethrough.

  Here, as shown in FIG. 5, the drive voltages ROUT and FOUT output from the terminals T1 and T3 change according to the drive power supply voltage. Therefore, the amount of current flowing through the resistor R21 changes according to the drive power supply voltage. Here, the drive power supply voltage is determined according to the drive power supply control signal as described above, and this drive power supply control signal is determined according to the voltage VCC input to the driver. Therefore, in the present embodiment, the FG signal reference voltage Vfg is determined according to the voltage VCC supplied from the outside.

  Here, in the conventional device, a circuit that can output the voltage VCC for fan drive control may already be prepared. In this case, as described later, it is preferable to generate a signal for controlling the piezoelectric element PZ in accordance with VCC. In this embodiment, the FG signal reference voltage Vfg is generated using this voltage VCC. The FG signal reference voltage is set to a voltage that is about ½ of the upper voltage of the current detection resistor R21.

“FG signal reference voltage”
FIG. 7 shows a configuration for changing the FG signal reference voltage Vfg according to the voltage VCC. A terminal T31 to which the voltage VCC is input is connected to the ground via a voltage dividing resistor composed of a series connection of resistors R31 and R32. The midpoint of the voltage dividing resistors R31 and R32 is input to the positive input terminal of the buffer amplifier BF31 whose output is short-circuited to the negative input terminal, and this output is supplied to the negative input terminal of the comparator CP41 as the detection reference voltage Vfg. The reference voltage Vfg is supplied to the negative input terminal of the comparator CP31 in FIG. 9 via the buffer amplifier BF31.

  In this example, the reference V31 is input to the positive input terminal, the midpoint of the voltage dividing resistors R31 and R32 is connected to the negative input terminal, and the midpoint of the voltage dividing resistors R31 and R32 is output via the diode D31. Is connected to the comparator CP41 and the reference V32 is input to the positive input terminal, the negative input terminal is connected to the midpoint of the voltage dividing resistors R31 and R32, and the output is connected to the voltage dividing resistors R31 and R32 via the diode D32. And a comparator CP42 connected to the midpoint. The diode D31 allows only a current flowing from the midpoint of the voltage dividing resistors R31 and R32 toward the output of the comparator CP41, and the diode D32 allows a current to flow from the output of the comparator CP41 toward the midpoint of the voltage dividing resistors R31 and R32. Only shed. Therefore, the midpoint voltage of the voltage dividing resistors R31 and R32 is clipped by the reference voltages V31 and V32. Therefore, the FG signal reference voltage Vfg changes as shown in FIG. 8 as the power supply voltage VCC changes. That is, the FG signal reference voltage Vfg linearly changes from V32 to V31 when the power supply voltage VCC is 0 to V32 (R31 + R32) / R32 and between V32 (R31 + R32) / R32 to V31 (R31 + R32) / R32. However, it is fixed at V31 above V31 (R31 + R32).

"Generation of FG signal"
FIG. 9 shows a configuration for generating an FG signal. The positive input terminal of the comparator CP31 is connected to a terminal T22 to which the upper voltage of the current detection resistor R20 is supplied. An FG signal reference voltage Vfg is supplied to the negative input terminal of the comparator CP31. Accordingly, the comparator CP31 outputs an H level when the upper voltage of the current detection resistor R20 exceeds the FG signal reference voltage Vfg, and outputs an L level when it falls below the FG signal reference voltage Vfg.

  The comparator CP31 employs a comparator having hysteresis for comparison. This is because there is a possibility that various noises such as a voltage generated according to the force applied to the piezoelectric element PZ are applied to the drive current, and there is a high possibility that the drive current is not a clean sine wave. Therefore, if the comparison result with Vfg, which is an intermediate voltage, is used as it is as a signal, there is a possibility that the H and L level changes are repeated in the vicinity where the result is inverted. Generation of a whisker-like pulse in the FG signal due to vibration is prevented.

"Processing when an error is detected"
In the present embodiment, the output of the comparator CP31 is input to the AND gate AND31. An error detection signal is input to the other input terminal of the AND gate AND31. This error detection signal is normally at the H level and is at the L level when an error is detected. This prohibits the output of the FG signal when an error occurs.

  That is, as shown in FIG. 8, when a load short circuit occurs and the drive current increases, a circuit for detecting a load short circuit is provided, and the detection signal is set to L level when a load short circuit is detected. As a result, the FG signal is fixed to the L level when a load short-circuit occurs.

  An external microcomputer or the like generates a drive control signal in response to the supply of the FG signal, and can detect the occurrence of an abnormality when the FG signal is not supplied. As a result, it is not necessary to output an error detection signal from a dedicated terminal, and the driver terminal can be omitted.

  For example, an error signal can be generated by detecting a high voltage of the drive power supply as abnormal. In this case, an error is detected when the feedback signal to the comparator CP4 in FIG. 3 is higher than the drive voltage control signal by a predetermined level, or the feedback signals to the comparators CP1 and CP2 of the drive signals ROUT and FOUT are R side signals, It is preferable to detect an error by being higher than a predetermined value with respect to the F-side signal.

  Furthermore, when the upper voltage of the voltage detection resistor R20 in FIG. 9 is equal to or higher than a predetermined value, it is preferable to detect an error due to a load short when the load is short-circuited or lower than a predetermined value. Further, it is also preferable to change the threshold value at the time of error detection according to the power supply voltage VCC as described above.

"Configuration of output amplifier AP"
10 and 11 show configuration examples of the output amplifier AP. A constant current is supplied from ICOM, which is supplied to the drain and gate of n-channel transistor Q11. The source of the transistor Q11 is connected to the ground (PGND). The gates of the transistors Q11 are commonly connected to the gates of n-channel transistors Q12, Q13, Q14 whose sources are connected to the ground (PGND). Therefore, the transistors Q12, Q13, and Q14 form a current mirror with respect to the transistor Q11, and the same constant current flows through these transistors Q11 to Q14.

  The drain of the transistor Q12 is connected to the drain of the p-channel transistor Q15, and the source of the transistor Q15 is connected to the drive power supply VS. The drain and gate of the transistor Q15 are short-circuited, and the gates of p-channel transistors Q16 and Q17 whose sources are connected to VS are connected to this gate. Therefore, the same constant current flows through these transistors Q16 and Q17 as those flowing through the transistor Q11.

  The drain of the transistor Q13 is connected to the drive power supply VS via the p-channel transistors Q18 and Q19 whose two drains and gates are short-circuited, and the drains of the transistors Q13 and Q18 are connected to the gate of the p-channel transistor Q20. Has been. The drain of the transistor Q17 is connected to a terminal RF connected to an external ground via n-channel transistors Q21 and Q22 in which the two drains and gates are short-circuited. A connection point between the transistors Q17 and Q21 is connected to the gate of the n-channel transistor Q23.

  The source of the transistor Q20 and the drain of the transistor Q23 are connected in common to the drain of the transistor Q16 and to the gate of the p-channel transistor Q24. Further, the drain of the transistor Q20 and the source of the transistor Q23 are connected in common to the drain of the transistor Q14 and to the gate of the n-channel transistor Q25. The drive current Idr is supplied from the ICTLF terminal to the drain of the transistor Q20, the source of the transistor Q23, the drain of the transistor Q14, and the gate of the n-channel transistor Q25. That is, the ICTLF terminal is connected to the output of the comparator CP1 (or the comparator CP2).

  The source of the transistor Q24 is connected to the drive power source VS, the drain is connected to the drain of the transistor Q25 and the output terminal OUT (T1 or T2), and the source of the transistor Q25 is connected to the terminal RF. Yes.

  In such a circuit, a current obtained by dividing the constant current flowing through the transistor Q16 flows through the transistor Q20 and the transistor Q23. In addition, a constant current flowing through the transistor Q13 flows through the transistors Q19 and Q18, and a current flowing through the transistor Q17 flows through the transistors Q21 and Q22. Therefore, normally, the currents flowing through the transistors Q20 and Q23 are equal.

  When the drive current Idr is a current Idr + flowing toward the gate of the transistor Q25, as shown in FIG. 10, the transistor Q25 is turned on, and a current in a direction of drawing a current from the output terminal OUT flows. Move to the L level. At this time, since the sum of the currents flowing through the transistors Q20 and Q23 is equal to the constant current flowing through the transistor Q14, the transistor Q24 is off.

  On the other hand, if the drive current Idr is a current Idr− that flows in the direction of pulling out from the gate of the transistor Q25, the drain current of the transistor Q23 increases as shown in FIG. 11, the transistor Q24 is turned on, and the output terminal OUT Current flows in the direction of discharging current, and the output terminal OUT moves to the H level side.

  In this way, the output transistors Q24 and Q25 are controlled according to the current flowing through the ICTLF, and the output from the output terminal OUT is controlled. The output amplifier AP functions as a high withstand voltage output unit that obtains an output by power from the drive power supply VS. Accordingly, the amplifiers shown in FIGS. 10 and 11 are prepared as the output amplifiers AP1 and AP2 in FIGS. 3 and 9, respectively, and the outputs of the comparators CP1 and CP2 are input to the ICTLF of the respective amplifiers. Drive signals ROUT and FOUT can be obtained, respectively.

  The power supply voltage of the signal system is, for example, about 5V, and the drive power supply VS is, for example, about 200V.

“Configuration of VCC-linked DAC”
In a conventional apparatus, there is a case in which a circuit that can output a power supply voltage VCC that is a control power supply voltage for controlling fan driving is already prepared for fan drive control. In this case, it is preferable to generate a signal for controlling the piezoelectric element PZ in accordance with the power supply voltage VCC.

  FIG. 12 shows a configuration suitable for such a case. A terminal T11 to which a power supply VCC whose voltage inputted from the outside is appropriately changed according to the drive request of the pump is connected to the ground via a voltage dividing resistor composed of resistors R11 and R12 connected in series. The middle point of the voltage dividing resistors R11 and R12 is input to the positive input terminal of the buffer amplifier BF11 whose output is short-circuited to the negative input terminal, and this output is the power supply VDAC of the D / A converter 30.

  In this example, the reference V1 is input to the positive input terminal, the middle point of the voltage dividing resistors R11 and R12 is connected to the negative input terminal, and the middle point of the voltage dividing resistors R11 and R12 is output via the diode D11. Is connected to the buffer amplifier BF12 and the reference V2 is input to the positive input terminal, the midpoint of the voltage dividing resistors R11 and R12 is connected to the negative input terminal, and the output is divided by the voltage dividing resistors R11 and R12 via the diode D12. And a buffer amplifier BF13 connected to the middle point. The diode D11 passes only the current flowing from the middle point of the voltage dividing resistors R11 and R12 toward the output of the buffer amplifier BF12, and the diode D12 moves from the output of the buffer amplifier BF13 toward the middle point of the voltage dividing resistors R11 and R12. Only the flowing current is passed. Therefore, the midpoint voltage of the voltage dividing resistors R11 and R12 is clipped by the reference voltages V1 and V2. Therefore, the power supply VDAC changes as shown in FIG. 13 as the power supply voltage VCC changes. That is, the power supply VDAC linearly changes from V2 to V1 when the power supply voltage VCC is 0 to V2 (R11 + R12) / R12, and between V2 (R11 + R12) / R12 to V1 (R11 + R12) / R12, V1 Above (R11 + R12), it is fixed at V1.

  FIG. 14 shows the configuration of the D / A converter 30. A resistor corresponding to the number of bits of the input digital signal is connected in series between the power supply VDAC and the ground. Two switches are provided corresponding to the connection points between the resistors, and the ends of the R-side switch group SWr on one side that are not on the resistance side are commonly connected to output the R-side signal and the other side. The ends of the F-side switch group SWf that are not on the resistance side are commonly connected to output an F-side signal.

  A counter circuit 32 is provided to control the R side and F side switch groups. The counter 32 repeats up-counting and down-counting a predetermined clock. For example, the 512-stage count value is repeatedly output in order of 0 → 511 → 0 → 511. The outputs of these counters are associated with each other so that the R-side switch group SWr and the F-side switch group SWf have the opposite outputs. That is, the output of the F-side switch group SWf is set to 511 if the output of the R-side switch group SWr is 0 when the output of the counter 32 is 0.

  Accordingly, the R side signal and the F side signal become complementary sine curves that sequentially change with respect to one clock, as shown in the figure. As the power supply VDAC changes, the amplitudes of the R side signal and the F side signal change in conjunction with each other. Therefore, an R-side signal and an F-side signal whose amplitude changes according to the power supply VCC are obtained at the output of the D / A converter 30. Further, the maximum output of the D / A converter 30 is output as a drive power supply control signal.

  The output signal of FIG. 14 is input to the buffer amplifiers BF1 and BF2 and the comparator CP3 of FIGS. Then, by appropriately setting the ratio of the voltage dividing resistors R1, R2, R3, R4, R5, and R6, the discharge amount of the piezoelectric pump can be controlled to the target value according to the input VCC. Become.

  In FIG. 14, the R-side signal and the F-side signal are output from the D / A converter 30 as they are. However, the R side signal and the F side signal are vertically symmetrical. Accordingly, only half (180 degrees) of output can be output from the D / A converter 30, and the output of the other half can be inverted. As a result, the resistor string in the D / A converter 30 can be halved.

It is a figure which shows the structure of a piezoelectric pump. It is a figure which shows the structure of the diaphragm of a piezoelectric pump. It is a figure which shows the structure of the output part of a high voltage output driver. It is a figure which shows the waveform of a drive signal. It is a figure which shows load drive (output) electric current. It is a figure which shows the waveform of a drive signal and an output current. It is a figure which shows the structure for detection reference voltage generation | occurrence | production. It is a figure which shows the characteristic of a detection reference voltage. It is a figure which shows the structure of the output part of the high voltage output driver containing the structure of FG signal generation. It is a figure which shows the structure of an output amplifier. It is a figure which shows the structure of an output amplifier. It is a figure which shows the structure for the output of power supply VDAC. It is a figure which shows the characteristic with respect to the power supply VCC of power supply VDAC. It is a figure which shows the structure of the D / A converter which obtains the output of the output amplitude according to power supply VDAC.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Pump casing, 12 Diaphragm, 14 Pump chamber, 16 Inlet part, 18 Inlet part, 20 Outlet part, 22 Outlet part, 24,26 Check valve, 30 Converter, 32 Counter circuit, AP1, AP2 Output amplifier, BF1, BF2 , BF11, BF12, BF13 buffer amplifier, C1, C2 capacitor, CP1, CP2, CP3, CP4 comparator (error amplifier), D1, D11, D12 diode, Q1-Q2, Q11-Q25 transistors, R1-R7, R11, R12 resistance.

Claims (5)

A drive current generation circuit that boosts a power supply voltage to generate a drive power supply voltage and changes the drive power supply voltage according to a control signal;
An output circuit for outputting a drive signal supplied from the drive power supply voltage to the load;
A current detection resistor that generates a detection voltage corresponding to the current flowing through the load;
A comparison circuit that compares the detection voltage with a threshold value, and obtains a frequency signal indicating a drive frequency of the load from the comparison result;
Including
A high-voltage output driver, wherein the threshold value is changed according to the control signal. The high voltage output driver according to claim 1,
The drive signal has a pair of sine wave shapes that change complementarily, and a voltage of a difference between the two is applied to the load. The high voltage output driver according to claim 1 or 2,
An error signal indicating an error state in load driving, and the frequency signal are input, and has an AND gate that takes a logical product of both,
A high voltage output driver that stops frequency signal output when an error occurs. The high voltage output driver according to claim 1 or 2,
The comparison circuit detects a load short-circuit when the detection voltage is larger than the threshold value. The high voltage output driver according to claim 1 or 2,
The comparison circuit detects a load open when the detection voltage is smaller than the threshold value.

Images