JP2010136505A - Inverter apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily solve the problem without need for closely arranging respective elements and without increasing the number of components and cost and to effectively suppress surge voltage with switching of a switching element. <P>SOLUTION: Even if third and second transistors 13 and 12 are switched from ON to OFF, current continuously flows to respective parasitic inductances 56b and 55c. Since a cathode K of a fourth diode 24 is connected to vicinity of an emitter E of the third transistor 13 and an anode A of a first diode 21 is connected to vicinity of a collector C of the second transistor 12, a current route from the fourth diode 24 to an inductive load 17 is formed through the parasitic inductance 56b, and a current route from a DC resistor 18 to the first diode 21 is formed through the parasitic inductance 55c. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an inverter device that converts a DC voltage into an AC voltage.

  8A and 8B illustrate a conventional inverter device. FIG. 8A schematically shows a wiring pattern on the substrate of the inverter device, and FIG. 8B shows a wiring connection of the inverter device. As shown in these drawings, in the inverter device, the first transistor 111 and the second transistor 112 are connected in series between the DC power source 110 and the ground, and the third transistor 113 and the fourth transistor 114 are connected in series. Is inserted. An inductive load 117 and a DC resistor 118 are connected in series between the wiring 115 connecting the first and second transistors 111 and 112 and the wiring 116 connecting the third and fourth transistors 113 and 114. is doing. Furthermore, the first to fourth transistors 111 to 114 are connected in parallel to the first to fourth diodes 121 to 124 that respectively flow currents in opposite directions to the transistors. The collectors, emitters, and bases of the first to fourth transistors 111 to 114 are denoted by C, E, and B, respectively. Further, the symbols A and K are attached to the anode and cathode of the first to fourth diodes 121 to 124, respectively.

  Further, in the wiring 115, the connection portion 115a to which the DC resistor 118 is connected to the emitter E of the first transistor 111 is a wiring portion 115b, and the connection portion 115a to the collector C of the second transistor 112 is a wiring portion 115c. These wiring portions 115b and 115c have parasitic inductances 131 and 132, respectively. Similarly, in the wiring 116, a connection portion 116a to which the inductive load 117 is connected to the emitter E of the third transistor 113 is a wiring portion 116b, and a connection portion 116a to the collector C of the fourth transistor 114 is a wiring portion 116c. Yes. These wiring portions 116b and 116c have parasitic inductances 133 and 134, respectively.

  Next, the basic operation of such an inverter device will be described. In this basic operation, the influence of the parasitic inductances 131 to 134 is ignored.

  (Step 1) As shown in FIG. 9A, the third and second transistors 113 and 112 are turned on, and the DC current is of the DC power supply 110 is changed to the third transistor 113 → inductive load 117 → DC resistor 118 → second transistor 112. → Flow through the grounding route. At this time, a positive voltage is generated in the inductive load 117.

  (Step 2) As shown in FIG. 9B, the third and second transistors 113 and 112 are turned off, and the self-induced current + iy generated in the inductive load 117 is grounded → the fourth diode 124 → the inductive load 117 → the DC resistance. The current flows through the path 118 → first diode 121 → DC power supply 110. Also at this time, a positive voltage is generated in the inductive load 117.

  (Step 3) As shown in FIG. 9C, the first and fourth transistors 111 and 114 are turned on, and the DC current is of the DC power supply 110 is changed from the first transistor 111 to the DC resistor 118 to the inductive load 117 to the fourth transistor 114. → Flow through the grounding route. At this time, a negative voltage is generated in the inductive load 117.

  (Step 4) As shown in FIG. 9D, the first and fourth transistors 111 and 114 are turned off, and the self-induced current -iy generated in the inductive load 117 is grounded → second diode 122 → DC resistance 118 → inductive. It flows through the route of load 117 → third diode 123 → DC power supply 110. At this time, a negative voltage is generated in the inductive load 117.

  Such operations in steps 1 to 4 are repeated to convert the DC voltage of the DC power supply 110 into an AC voltage.

  By the way, in the inverter device as shown in FIGS. 8A and 8B, if the switching speed of the first to fourth transistors 111 to 114 is slow, the parasitic inductances 131 to 134 of the wirings 115 do not become a problem.

  However, in recent years, there is a tendency to increase the switching speed in order to reduce the size and price of the device, and surge voltage due to the parasitic inductance has become a problem. Here, if the current flowing through the switching element is i and the time is t, the current change di / dt increases as the switching of the switching element becomes faster. When the parasitic inductance is Ls and the surge voltage generated in the parasitic inductance is Vs, Vs = Ls · di / dt. Therefore, the faster the switching of the switching element, the higher the surge voltage Vs. I understand. The surge voltage Vs causes dielectric breakdown and element damage, and causes failure of the device and deterioration of durability.

  Next, in the inverter device of FIG. 8A and FIG. 8B, the operation | movement which considered each parasitic inductance 131-134 is demonstrated.

  (Step 1) As shown in FIG. 9A, the third and second transistors 113 and 112 are turned on, and the DC current is of the DC power supply 110 is changed to the third transistor 113 → parasitic inductance 133 → inductive load 117 → DC resistance 118 → It flows through the path of parasitic inductance 132 → second transistor 112 → ground.

  (Step 2) As shown in FIG. 9B, the third and second transistors 113 and 112 are turned off. At this time, the self-induced current + iy generated in the inductive load 117 is a path of ground → fourth diode 124 → parasitic inductance 134 → inductive load 117 → DC resistance 118 → parasitic inductance 131 → first diode 121 → DC power supply 110. It flows in.

  (Step 3) As shown in FIG. 9C, the first and fourth transistors 111 and 114 are turned on, and the DC current is of the DC power supply 110 is changed to the first transistor 111 → the parasitic inductance 131 → the DC resistance 118 → the inductive load 117 → It flows through the path of parasitic inductance 134 → fourth transistor 114 → ground.

(Step 4) As shown in FIG. 9D, the first and fourth transistors 111 and 114 are turned off. At this time, the self-induced current −iy generated in the inductive load 117 is ground → second diode 122 → parasitic inductance 132 → DC resistance 118 → inductive load 117 → parasitic inductance 133 → third diode 123 → DC power supply 110. Here, in step 1, current flows through the parasitic inductances 133 and 132, whereas in step 2, the third and second transistors 113 and 112 are turned off, and each parasitic inductance is The current paths 133 and 132 are cut off, and no current flows through the parasitic inductances 133 and 132.

  Even if the current paths of the parasitic inductances 133 and 132 are interrupted by switching from step 1 to step 2, the energy is held in the parasitic inductances 133 and 132. Respective back electromotive forces are generated in the parasitic inductances 133 and 132, and these back electromotive forces appear as surge voltages.

  Similarly, in step 3, current flows through the parasitic inductances 131 and 134, but in step 4, the first and fourth transistors 111 and 114 are turned off, and the current paths of the parasitic inductances 131 and 134 are changed. It is cut off and no current flows through each of the parasitic inductances 131 and 134.

  When the current path of each of the parasitic inductances 131 and 134 is interrupted by switching from step 3 to step 4, the held energy of each of the parasitic inductances 131 and 134 is released, and each of the parasitic inductances 131 and 134 is released. Each counter electromotive force is generated, and these counter electromotive forces appear as surge voltages.

  As described above, these surge voltages cause dielectric breakdown and element damage, leading to failure of the apparatus and deterioration of durability.

  Next, the first to fourth transistors 111 to 114 in the inverter device of FIGS. 8A and 8B were replaced with bipolar field-effect transistors (hereinafter referred to as FETs) to form an inverter device as shown in FIG. In the inverter device of FIG. 10, the switching operation similar to that of FIGS. 9A to 9D is performed by simulation, and the current waveforms and voltage waveforms of the first to fourth FETs 111 to 114 associated with this switching operation are shown at the respective locations x. Since it was determined by measurement, the results are shown in FIGS.

  However, the voltage of the DC power supply 110 is 1 (KV), the switching frequency of the first to fourth FETs 111 to 114 is 50 (KHz), and the resistance value of the first to fourth FETs 111 to 114 when turned on is 0.001 ( Ω), the inductance of the inductive load 117 is 100 (μH), the resistance of the DC resistor 118 is 10 (Ω), and the inductance of each of the parasitic inductances 131 to 134 is 1 (μH).

  FIGS. 11A and 11B show the current waveform and voltage waveform of the first FET 111, FIGS. 11C and 11D show the current waveform and voltage waveform of the second FET 112, and FIGS. ) Shows the current waveform and voltage waveform of the third FET 113, and FIGS. 11G and 11H show the current waveform and voltage waveform of the fourth FET 114.

  As described above, when the third and second FETs 113 and 112 are turned off by switching from step 1 to step 2, surge voltages of the parasitic inductances 133 and 132 are generated, and these surge voltages Vs are shown in FIG. , (F), the voltage waveforms of the third and second FETs 113 and 112 appear.

  Similarly, when the first and fourth transistors 111 and 114 are turned off by switching from step 3 to step 4, surge voltages of the parasitic inductances 131 and 134 are generated, and these surge voltages Vs are shown in FIG. , (H), the voltage waveforms of the first and fourth FETs 111 and 114 appear.

  Such a surge voltage is more likely to occur as the switching speed increases as described above. In recent inverter devices, since the switching speed is increased in order to reduce the size and the price, such a surge voltage is a serious problem.

  In addition, in a transistor including a compound semiconductor such as SiC, GaAs, or GaN, the surge voltage resistance is lower than that of a single semiconductor element such as Si, and therefore, the conventional circuit configuration cannot be used as it is.

  Various proposals have been made to deal with such a surge voltage. For example, in Patent Document 1, the wiring length is shortened in order to reduce the parasitic inductance of the wiring between the elements.

  Further, in Patent Document 2, the gate voltage and collector voltage of the switching element are detected, and the gate resistance of the switching element is increased stepwise according to the detected voltage to suppress the current change di / dt.

  Further, in Patent Document 3, a plurality of wiring conductors are arranged in close contact with each other in a parallel plate shape, and each magnetic flux generated by the current of each wiring conductor is canceled out to reduce the parasitic inductance of each wiring conductor. Yes.

In Patent Document 4, a snubber circuit including an IGBT (Insulated Gate Bipolar Transistor), an avalanche diode, a reverse current prevention diode, and a resistor is connected in parallel with the transistor to suppress a surge voltage applied to the transistor. .
JP 2005-51109 A JP 2008-92663 A JP 2001-274322 A JP 2002-152024 A

  However, when the wiring length between the elements as in Patent Document 1 is shortened, the elements are arranged close to each other, and there is a problem that heat radiation of the elements becomes difficult or malfunction occurs due to noise between the elements.

  Further, when the gate resistance of the switching element is increased stepwise according to the detection voltage as in Patent Document 2, or a snubber circuit is provided as in Patent Document 4, the number of elements or parts increases, resulting in a cost reduction. Increased.

  Furthermore, it is not easy to form each wiring conductor in close contact with each other like a parallel plate as in Patent Document 3, and there are large restrictions on the wiring pattern and the arrangement of elements, so that it is difficult to realize and the cost is low. Increased.

  Therefore, the present invention has been made in view of the above-described conventional problems, and it is not necessary to arrange each element close to each other and can be easily realized without increasing the number of parts and cost. An object of the present invention is to provide an inverter device capable of effectively suppressing a surge voltage associated with switching of a switching element.

  In order to solve the above-mentioned problem, the present invention inserts the first and second switching elements connected in series between the DC power source and the ground, and inserts the third and fourth switching elements connected in series. Connecting the connection wiring between the first switching element and the second switching element and the connection wiring between the third switching element and the fourth switching element via an inductive load, and flowing a current in a direction opposite to that of the first to fourth switching elements, respectively. A fourth diode is connected in parallel to the first to fourth switching elements, the third and second switching elements are turned on, and a DC power supply current is passed in one direction through the third and second switching elements to the inductive load. After that, the third and second switching elements are turned off, and a one-way self-induced current is passed through the inductive load through the fourth and first diodes, followed by the first and fourth switches. The switching element is turned on and a DC power supply current is passed through the inductive load in the reverse direction through the first and fourth switching elements, and then the first and fourth switching elements are turned off and inducted through the second and third diodes. In an inverter device that converts a DC voltage to an AC voltage by repeating a switching operation in which a self-inductive current is caused to flow in the opposite direction to the capacitive load, the anode of the first diode is connected to the connection wiring between the first and second switching elements. A connection point between the connection line and the inductive load is connected to a portion closer to the second switching element, and the cathode of the second diode is connected to the connection line and the inductive load in the connection line between the first and second switching elements. Connect the point closer to the first switching element than the point, and connect the anode of the third diode to the connection between the third and fourth switching elements. The connection line and the inductive load are connected to a portion closer to the fourth switching element than the connection point of the inductive load, and the cathode of the fourth diode is connected to the connection line and the inductive load in the connection line between the third and fourth switching elements. It is connected to a part near the third switching element rather than the connection point.

  For example, the connection distance on the wiring between the cathode of the first switching element and the second diode is shorter than the connection distance on the wiring between the anode of the second switching element and the second diode, and the second switching element and the first diode The connection distance on the wiring between the anodes is shorter than the connection distance on the wiring between the first switching element and the cathode of the first diode, and the connection distance on the wiring between the cathode of the third switching element and the fourth diode is the fourth. The connection distance on the wiring between the switching element and the anode of the fourth diode is shorter than the connection distance on the wiring between the fourth switching element and the anode of the third diode. It is shorter than the connection distance above.

  A wiring between the first switching element and the cathode of the first diode, a wiring between the second switching element and the anode of the second diode, a wiring between the third switching element and the cathode of the third diode, and a fourth switching element; At least one of the wires between the anodes of the fourth diode is grounded via a capacitor.

  Further, a direct current resistor is connected in series with the capacitor.

  Also, there are provided three or more sets of first and second switching elements or third and fourth switching elements that are inserted in series between the DC power source and the ground, and an inductive load is provided between each set of switching elements. The diodes are connected in parallel to each switching element, and each of the diodes flows a current in a direction opposite to that of each switching element.

  For example, the first to fourth switching elements or the first to fourth diodes include a compound semiconductor such as SiC, GaAs, or GaN.

  The basic configuration of the inverter device of the present invention is the same as that of the inverter device of FIGS. 8A and 8B, and includes a DC power supply, first to fourth switching elements, first to fourth diodes, and an inductive load. The first to fourth switching elements are selectively switched to repeat the operation of flowing a current in one direction or flowing a current in the reverse direction to the inductive load, thereby converting the DC voltage into the AC voltage. Then, characteristic wiring is routed to suppress the occurrence of surge voltage caused by the parasitic inductance of the wiring. That is, the anode of the first diode is connected to a portion closer to the second switching element than the connection point between the connection wiring and the inductive load in the connection wiring between the first and second switching elements, and the cathode of the second diode is connected to the second diode. The connection wiring between the first and second switching elements is connected to a portion closer to the first switching element than the connection point between the connection wiring and the inductive load, and the anode of the third diode is connected between the third and fourth switching elements. A connection point between the connection line and the inductive load in the line is connected to a portion near the fourth switching element, and the cathode of the fourth diode is connected to the connection line and the inductive load between the third and fourth switching elements. The connection point is closer to the third switching element than the connection point.

  Here, when the third and second switching elements are turned on and a DC power supply current is passed through the inductive load in one direction through the third and second switching elements, between the third switching element and the third and fourth switching elements. A current flows through a path of connection wiring → inductive load → connection wiring between the first and second switching elements → second switching element. After that, when the third and second switching elements are turned off and a one-way self-inductive current flows through the inductive load through the fourth and first diodes, the connection between the fourth diode and the third and fourth switching elements is performed. Current flows through a path of wiring → inductive load → connection wiring between the first and second switching elements → first diode.

  Therefore, even when the third and second switching elements are both on and off, a current flows through the connection wiring between the third and fourth switching elements and the connection wiring between the first and second switching elements. This is because the cathode of the fourth diode is connected to the portion near the third switching element in the connection wiring between the third and fourth switching elements, and the anode of the first diode is connected to the connection wiring between the first and second switching elements. This is because it is connected to a portion near the second switching element. When the third and second switching elements are turned off, the self-induced current of the inductive load is quickly attenuated while flowing. For this reason, a surge voltage does not occur in the parasitic inductance of the connection wiring.

  Similarly, when the first and fourth switching elements are turned on and a DC power supply current is passed through the inductive load through the first and fourth switching elements in the reverse direction, the first switching element → the first and second switching elements The current flows through a path of the connection wiring → inductive load → connection wiring between the third and fourth switching elements → fourth switching element. Thereafter, when the first and fourth switching elements are turned off and a self-inductive current in the reverse direction is passed through the inductive load through the second and third diodes, the connection between the second diode and the first and second switching elements is performed. Current flows through a path of wiring → inductive load → connection wiring between the third and fourth switching elements → third diode.

  Therefore, when the first and fourth switching elements are both on and off, current flows through the connection wiring between the first and second switching elements and the connection wiring between the third and fourth switching elements. This is because the cathode of the second diode is connected to a portion near the first switching element in the connection wiring between the first and second switching elements, and the anode of the third diode is connected to the connection wiring between the third and fourth switching elements. This is because it is connected to a portion near the fourth switching element. When the first and fourth switching elements are turned off, the self-induced current of the inductive load is quickly attenuated while flowing. For this reason, a surge voltage does not occur in the parasitic inductance of the connection wiring.

  Thus, the characteristic wiring routing can suppress the generation of a surge voltage due to the parasitic inductance of the wiring. In addition, it is not necessary to arrange the elements close to each other, and the number of parts and cost are not increased, which can be easily realized.

  In order to perform such characteristic wiring, for example, the connection distance on the wiring between the first switching element and the cathode of the second diode is the connection on the wiring between the second switching element and the anode of the second diode. Shorter than the distance, the connection distance on the wiring between the second switching element and the anode of the first diode is shorter than the connection distance on the wiring between the first switching element and the cathode of the first diode, The connection distance on the wiring between the cathodes of the four diodes is shorter than the connection distance on the wiring between the fourth switching elements and the anode of the fourth diode, and the connection distance on the wirings between the fourth switching element and the anode of the third diode. Is shorter than the connection distance on the wiring between the third switching element and the cathode of the third diode.

  In addition, the wiring whose connection distance is increased by such characteristic wiring routing may be grounded via a capacitor. Thereby, generation | occurrence | production of a surge voltage can be prevented reliably. Furthermore, surge voltage can be further suppressed by connecting a DC resistor in series with the capacitor.

  Also, there are provided three or more sets of first and second switching elements or third and fourth switching elements that are inserted in series between the DC power source and the ground, and an inductive load is provided between each set of switching elements. The present invention can also be applied to a multi-phase inverter device in which diodes that are connected to each other and flow currents in directions opposite to the switching elements are connected in parallel to the switching elements.

  For example, when the first to fourth switching elements or the first to fourth diodes include a compound semiconductor such as SiC, GaAs, or GaN, the resistance of the elements to the surge voltage is low, so that the present invention is effective. is there.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  1A and 1B show a first embodiment of the inverter device of the present invention. FIG. 1A schematically shows a wiring pattern on the substrate of the inverter device of this embodiment, and FIG. 1B shows the embodiment of this embodiment. The wiring connection of an inverter apparatus is shown.

  In the inverter device of this embodiment, the first to fourth transistors 11 to 14, the first to fourth diodes 21 to 24, and the first to fourth capacitors 41 to 44 are distributed and arranged on the plurality of wiring patterns P1 to P4. These elements are interconnected.

  In this inverter device, the first transistor 11 and the second transistor 12 are inserted in series between the DC power source 1 and the ground, and the third transistor 13 and the fourth transistor 14 are inserted in series. Therefore, it can be said that a series circuit composed of the first and second transistors 11 and 12 and a series circuit composed of the third and fourth transistors 13 and 14 are connected in parallel between the DC power source 1 and the ground.

  In addition, an inductive load 17 and a DC resistor 18 are connected in series between a wiring portion 15 that connects the first and second transistors 11 and 12 and a wiring portion 16 that connects the third and fourth transistors 13 and 14. Is inserted.

  Furthermore, the first to fourth transistors 11 to 14 are connected in parallel to the first to fourth diodes 21 to 24 that respectively flow currents in directions opposite to those of the transistors.

  Here, the anode A of the first diode 21 is connected to the emitter E of the first transistor 11 through the wiring portion 15 and the wiring portion 31, and the cathode K of the first diode 21 is connected to the collector C of the first transistor 11 through the wiring portion 32. Therefore, it can be said that the first diode 21 is connected in parallel to the first transistor 11 in a direction in which a current flows in a direction opposite to that of the first transistor 11.

  The anode A of the first diode 21 is connected to a portion of the wiring portion 15 that is closer to the second transistor 12 than the connection point 15 a between the wiring portion 15 and the inductive load 17, that is, the collector C of the second transistor 12. Has been. In order to realize this connection, the wiring portion 31 between the collector C of the second transistor 12 and the anode A of the first diode 21 is more than the wiring portion 32 between the collector C of the first transistor 11 and the cathode K of the first diode 21. Has also been shortened.

  A wiring portion 32 connected to the cathode K of the first diode 21, and a first capacitor 41 is inserted and connected between the portion of the wiring portion 32 near the first transistor 11 and the ground.

  The anode A of the second diode 22 is connected to the emitter E of the second transistor 12 through the wiring portion 33, and the cathode K of the second diode 22 is connected to the collector C of the second transistor 12 through the wiring portion 34 and the wiring portion 15. Therefore, it can be said that the second diode 22 is connected in parallel to the second transistor 12 in a direction in which a current flows in a direction opposite to that of the second transistor 12.

  The cathode K of the second diode 22 is connected to a portion near the first transistor 11 relative to the connection point 15 a in the wiring portion 15, that is, near the emitter E of the first transistor 11. In order to realize this connection, the wiring portion 34 between the emitter E of the first transistor 11 and the cathode K of the second diode 22 is shorter than the wiring portion 33 between the emitter E of the second transistor 12 and the anode A of the second diode 22. Has been.

  A second capacitor 42 is connected to the cathode K of the second diode 22, and the wiring portion 33 is grounded through the second diode 22 and the second capacitor 42.

  Further, the anode A of the third diode 23 is connected to the emitter E of the third transistor 13 through the wiring portion 16 and the wiring portion 35, and the cathode K of the third diode 23 is connected to the collector C of the third transistor 13 through the wiring portion 36. Since it is connected, it can be said that the third diode 23 is connected in parallel to the third transistor 13 in a direction in which a current flows in a direction opposite to that of the third transistor 13.

  The anode A of the third diode 23 is connected to a portion near the fourth transistor 14 relative to the connection point 16 a in the wiring portion 16, that is, near the collector C of the fourth transistor 14. In order to realize this connection, the wiring portion 35 between the collector C of the fourth transistor 14 and the anode A of the third diode 23 is more than the wiring portion 36 between the collector C of the third transistor 13 and the cathode K of the third diode 23. It has been shortened.

  A wiring portion 36 connected to the cathode K of the third diode 23, and a third capacitor 43 is inserted and connected between a portion of the wiring portion 36 near the third transistor 13 and the ground.

  The anode A of the fourth diode 24 is connected to the emitter E of the fourth transistor 14 through the wiring portion 37, and the cathode K of the fourth diode 24 is connected to the collector C of the fourth transistor 14 through the wiring portion 38 and the wiring portion 16. Therefore, it can be said that the fourth diode 24 is connected in parallel to the fourth transistor 14 in a direction in which a current flows in a direction opposite to that of the fourth transistor 14.

  The cathode K of the fourth diode 24 is connected to a portion near the third transistor 13 relative to the connection point 16 a in the wiring portion 16, that is, near the emitter E of the third transistor 13. In order to realize this connection, the wiring portion 38 between the third transistor 13 and the cathode K of the fourth diode 24 is made shorter than the wiring portion 37 between the emitter E of the fourth transistor 14 and the anode A of the fourth diode 24. Yes.

  A fourth capacitor 44 is connected to the cathode K of the fourth diode 24, and the wiring portion 37 is grounded through the fourth diode 24 and the fourth capacitor 44.

  In such a wiring configuration, since the parasitic inductance of the relatively long wiring portion cannot be ignored, the parasitic inductance of each of the wiring portions 15b, 15c, 16b, 16c, 32, 33, 36, and 37 is denoted by 55b. , 55c, 56b, 56c, 52, 53, 56, 57.

  Next, the operation of the inverter device of this embodiment will be described based on the influence of parasitic inductance.

  (Step 1) As shown in FIG. 2A, the third and second transistors 13 and 12 are turned on, and the DC current is of the DC power source 1 is changed to the third transistor 13 → parasitic inductance 56b → inductive load 17 → DC resistance 18 → It flows through the path of parasitic inductance 55c → second transistor 12 → ground. At this time, a positive voltage is generated in the inductive load 17.

  (Step 2) As shown in FIG. 2B, the third and second transistors 13 and 12 are turned off. At this time, a self-induced current + iy is generated in the inductive load 17, but ground → parasitic inductance 57 → fourth diode 24 → parasitic inductance 56b → inductive load 17 → DC resistance 18 → parasitic inductance 55c → first diode 21 → parasitic. Since a current feedback path of inductance 52 → DC power supply 1 is formed, self-induced current + iy flows through this feedback path, and the + voltage of inductive load 17 is maintained. The fourth and first diodes 24 and 21 serve as feedback diodes.

  (Step 3) As shown in FIG. 2C, the first and fourth transistors 11 and 14 are turned on, and the DC current is of the DC power source 1 is changed to the first transistor 11 → the parasitic inductance 55b → the DC resistor 18 → the inductive load 17 → It flows along the path of parasitic inductance 56c → fourth transistor 14 → ground. At this time, a negative voltage is generated in the inductive load 17.

  (Step 4) As shown in FIG. 2D, the first and fourth transistors 11 and 14 are turned off. At this time, the self-induced current -iy generated in the inductive load 17 is generated, but grounding → parasitic inductance 53 → second diode 22 → parasitic inductance 55b → DC resistance 18 → inductive load 17 → parasitic inductance 56c → third diode. A current feedback path of 23 → parasitic inductance 56 → DC power supply 1 is formed, and the self-inductive current -iy flows through this feedback path, and the negative voltage of the inductive load 17 is maintained. The second and third diodes 22 and 23 function as feedback diodes.

  Such operations in steps 1 to 4 are repeated to convert the DC voltage of the DC power source 1 into an AC voltage.

  Here, as is apparent from FIGS. 2A and 2B, in step 1, current flows in the parasitic inductances 56b and 55c, and in step 2, current also flows in the same parasitic inductances 56b and 55c. That is, even when the third and second transistors 13 and 12 are switched from on to off by switching from step 1 to step 2, current continues to flow through the parasitic inductances 56b and 55c. This is because the cathode K of the fourth diode 24 is connected to the vicinity of the emitter E of the third transistor 13, and the anode A of the first diode 21 is connected to the vicinity of the collector C of the second transistor 12. This is because a current path from the DC resistor 18 to the inductive load 17 is formed via the parasitic inductance 56b, and a current path from the DC resistor 18 to the first diode 21 is formed via the parasitic inductance 55c.

  In the dead time when the third and second transistors 13 and 12 are turned off, the self-inductive current of the inductive load 17 is quickly attenuated while flowing to the DC power source 1. For this reason, a surge voltage hardly occurs in the parasitic inductances 56b and 55c of the wiring portions 16b and 15c.

  Similarly, as apparent from FIGS. 2C and 2D, in step 3, current flows through the parasitic inductances 55b and 56c, and even in step 4, current flows through the same parasitic inductances 55b and 56c. Even when the first and fourth transistors 11 and 14 are switched from on to off by switching to 4, current continues to flow through the parasitic inductances 55b and 56c. This is because the cathode K of the second diode 22 is connected to the vicinity of the emitter E of the first transistor 11 and the anode A of the third diode 23 is connected to the vicinity of the collector C of the fourth transistor 14. This is because a current path from the DC resistor 18 to the DC resistor 18 is formed via the parasitic inductance 55b, and a current path from the inductive load 17 to the third diode 23 is formed via the parasitic inductance 56c.

  In the dead time when the first and fourth transistors 11 and 14 are turned off, the self-inductive current of the inductive load 17 is rapidly attenuated while flowing to the DC power source 1. For this reason, a surge voltage hardly occurs in the parasitic inductances 55b and 56c of the wiring portions 15b and 16c.

  On the other hand, in the present embodiment, since the anode A of the first diode 21 is connected to the vicinity of the collector C of the second transistor 12, the wiring portion 32 between the cathode K of the first diode 21 and the collector C of the first transistor 11 is reduced. It is getting longer. Similarly, since the cathode K of the second diode 22 is connected in the vicinity of the emitter E of the first transistor 11, the wiring portion 33 between the anode A of the second diode 22 and the emitter E of the second transistor 12 becomes long, Since the anode A of the third diode 23 is connected to the vicinity of the collector C of the fourth transistor 14, the wiring portion 36 between the cathode K of the third diode 23 and the collector C of the third transistor 13 becomes longer, and further, the fourth diode. Since the cathode K of 24 is connected to the vicinity of the emitter E of the third transistor 13, the wiring portion 37 between the anode A of the fourth diode 24 and the emitter E of the fourth transistor 14 is long.

  The parasitic inductances 52, 53, 56, and 57 of the wiring portions 32, 33, 36, and 37 that are thus long are so large that they cannot be ignored and cause a surge voltage.

  For example, as is apparent from FIGS. 2B and 2C, in step 2, current flows through the parasitic inductances 52 and 57, and in step 3, current does not flow through the same parasitic inductances 52 and 57. Switching from 2 to 3 may cause respective surge voltages in the parasitic inductances 52 and 57.

  As is clear from FIGS. 2D and 2A, in step 4, current flows through the parasitic inductances 53 and 56. In step 1, current does not flow through the same parasitic inductances 53 and 56. Switching from 4 to 1 may generate respective surge voltages in the parasitic inductances 53 and 56.

  However, since the wiring portions 32, 33, 36, and 37 are grounded via the first to fourth capacitors 41 to 44 as described above, the parasitic inductances 52, 53, 56, and A current component with a steep voltage change of 57 can be caused to flow to the ground side through the first to fourth capacitors 41 to 44, and the parasitic inductance 52, 53, 56, 57 is suppressed by suppressing the current change di / dt. The surge voltage can be suppressed.

  Thus, in the inverter device of the present embodiment, even when the third and second transistors 13 and 12 are switched from on to off by switching from step 1 to step 2, current flows through the parasitic inductances 56b and 55c. Continuing and after the third and second transistors 13 and 12 are turned off, the self-induced current of the inductive load 17 is quickly attenuated. For this reason, almost no surge voltage is generated in the parasitic inductances 56b and 55c of the wiring portions 16b and 15c.

  Similarly, even when the first and fourth transistors 11 and 14 are switched from on to off by switching from step 3 to step 4, current continues to flow through the parasitic inductances 55b and 56c, and the first and fourth transistors After the transistors 11 and 14 are turned off, the self-induced current of the inductive load 17 is quickly attenuated. For this reason, almost no surge voltage is generated in the parasitic inductances 55b and 56c of the wiring portions 15b and 16c.

  In addition, since the wiring portions 32, 33, 36, and 37 that are long due to the wiring are grounded via the first to fourth capacitors 41 to 44, the parasitic inductances 52, 53, and 56 of the wiring portions are grounded. , 57 can be suppressed.

  In addition, it is not necessary to arrange the elements close to each other, and the number of parts and cost are not increased, which can be easily realized.

  Further, since the surge voltage can be effectively suppressed, the first to fourth transistors 11 to 14 or the first to fourth diodes 21 to 24 have a withstand voltage characteristics including compound semiconductors such as SiC, GaAs, and GaN. Low ones can be applied.

  Next, the first to fourth transistors 11 to 14 in the inverter device of FIGS. 1A and 1B are replaced with a field effect transistor (hereinafter referred to as an FET) from a bipolar transistor to configure an inverter device as shown in FIG. Then, in the inverter device of FIG. 3, the switching operation similar to that of FIGS. 2A to 2D is performed by simulation, and the current waveforms and voltage waveforms of the first to fourth FETs 11 to 14 associated with this switching operation are obtained at respective locations x. Since it measured and calculated | required, the result is shown to Fig.4 (a)-(h).

  However, the voltage of the DC power supply 1 is 1 (KV), the switching frequency of the first to fourth FETs 11 to 14 is 50 (KHz), and the resistance value of the first to fourth FETs 11 to 14 when turned on is 0.001 ( Ω), the inductance of the inductive load 17 is 100 (μH), the resistance of the DC resistor 18 is 10 (Ω), the inductance of each parasitic inductance 55b, 55c, 56b, 56c is 1 (μH), and each parasitic The inductances of the inductances 52, 53, 56, and 57 were set to 5 (μH), and the capacities of the first to fourth capacitors 41 to 44 were set to 10 (μH).

  4A and 4B show the current waveform and voltage waveform of the first FET 11, FIGS. 4C and 4D show the current waveform and voltage waveform of the second FET 12, and FIGS. ) Shows the current waveform and voltage waveform of the third FET 13, and FIGS. 4G and 4H show the current waveform and voltage waveform of the fourth FET 14.

  As described above, even if the third and second FETs 13 and 12 are turned off by switching from step 1 to step 2, current continues to flow through the parasitic inductances 56b and 55c, and the self-induced current of the inductive load 17 4a and 4b, the surge voltages hardly occur in the parasitic inductances 56b and 55c of the wiring portions 16b and 15c, and the third and second FETs 13, as shown in FIGS. No surge voltage appears in the 12 voltage waveform.

  Similarly, even when the first and fourth FETs 11 and 14 are switched off by switching from step 3 to step 4, current continues to flow through the parasitic inductances 55b and 56c, and the self-inductive current of the inductive load 17 is rapidly increased. As shown in FIGS. 4 (h) and 4 (b), almost no surge voltage is generated in the parasitic inductances 55b and 56c of the wiring portions 15b and 16c. No surge voltage appears in the voltage waveform.

  FIG. 5 is a diagram showing a modification in which the direct current resistors 61 to 64 are added in series to the first to fourth capacitors 41 to 44 in the inverter device of FIG. 3. Each of the DC resistors 61 to 64 is provided to convert a surge voltage generated in each of the parasitic inductances 52, 53, 56, and 57 into heat and discharge it.

  Also in the inverter device of this modified example, the switching operation similar to that shown in FIGS. 2A to 2D is performed by simulation, and the current waveforms and voltage waveforms of the first to fourth FETs 11 to 14 accompanying this switching operation are measured at the respective locations x. The results are shown in FIGS. 6 (a) to 6 (h).

  6A and 6B show the current waveform and voltage waveform of the first FET 11, FIGS. 6C and 6D show the current waveform and voltage waveform of the second FET 12, and FIGS. ) Shows the current waveform and voltage waveform of the third FET 13, and FIGS. 6G and 6H show the current waveform and voltage waveform of the fourth FET 14.

  As apparent from FIGS. 6A to 6H, even when the third and second FETs 13 and 12 are turned off, no surge voltage appears in the voltage waveforms of the third and second FETs 13 and 12, and the first and Even if the fourth FETs 11 and 14 are switched off, no surge voltage appears in the voltage waveforms of the first and fourth FETs 11 and 14.

  FIG. 7 schematically shows a wiring pattern on a substrate in the second embodiment of the inverter device of the present invention.

  The inverter device according to the present embodiment is a three-phase inverter device, and includes a plurality of wiring patterns P1 to P5, first to sixth transistors 71 to 76, first to sixth diodes 91 to 96, and first to sixth capacitors. 101 to 106 are distributed and arranged, and these elements are interconnected.

  In this inverter device, the first transistor 71 and the second transistor 72 are connected in series between the DC power source 1 and the ground, the third transistor 73 and the fourth transistor 74 are connected in series, and the fifth transistor is inserted. 75 and the sixth transistor 76 are inserted in series.

  In addition, a wiring portion 81 connecting the first and second transistors 71 and 72, a wiring portion 82 connecting the third and fourth transistors 73 and 74, and a wiring portion 83 connecting the fifth and sixth transistors 75 and 76 are provided. Three terminals of the inductive load 84 are connected to each other. A DC resistor 85 is inserted between one of the three terminals of the inductive load 84 and the wiring portion 83.

  In addition, the first to sixth transistors 71 to 76 are connected in parallel with first to sixth diodes 91 to 96 that allow current to flow in the opposite direction to the transistors.

  Further, the cathode K side of the first to sixth diodes 91 to 96 is grounded via the first to sixth capacitors 101 to 106.

  In the inverter device having such a configuration, the anodes of the first, third, and fifth diodes 91, 93, 96 are connected to the vicinity of the collector C of the second, fourth, and sixth transistors 72, 74, 76. The cathodes K of the second, fourth, and sixth diodes 92, 94, 96 are connected to the vicinity of the emitter E of the first, third, and fifth transistors 71, 73, 75. For this reason, when the first and second transistors 71 and 72 are switched on and off, the third and fourth transistors 73 and 74 are switched on and off, and the fifth and sixth transistors 75 and 76 are switched on and off, the second, The current continues to flow in the wiring portion near the collector C of the fourth and sixth transistors 72, 74, and 76, and also in the wiring portion near the emitter E of the first, third, and fifth transistors 71, 73, and 75. Current continues to flow, and no surge voltage is generated due to the parasitic inductance of these wiring portions.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. It is understood.

  For example, in each of the above embodiments, the wiring portion that has become longer due to the routing of the wiring is grounded via the capacitor, but there is no longer wiring portion, or even if there is a longer wiring portion, If there is no influence of the parasitic inductance of the wiring portion, there is no need to ground through a capacitor.

  Also, multiple sets of switching elements are connected in series between the DC power supply and the ground, and the connection wiring between the switching elements of each set is connected via an inductive load. The present invention can also be applied to a multiphase inverter device in which each diode to be flown is connected in parallel to each switching element.

It is a figure which shows typically the wiring pattern on the board | substrate in 1st Embodiment of the inverter apparatus of this invention. It is a circuit diagram which shows the wiring connection of the inverter apparatus of 1st Embodiment. It is a figure which shows the flow of the electric current in operation | movement of step 1 of the inverter apparatus of 1st Embodiment. It is a figure which shows the flow of the electric current in operation | movement of step 2 of the inverter apparatus of 1st Embodiment. It is a figure which shows the flow of the electric current in operation | movement of step 3 of the inverter apparatus of 1st Embodiment. It is a figure which shows the flow of the electric current in operation | movement of step 4 of the inverter apparatus of 1st Embodiment. It is a circuit diagram which shows the inverter apparatus comprised by replacing the bipolar transistor in FIG. 1B with a field effect transistor. (A) thru | or (h) is a figure which shows the current waveform and voltage waveform of 1st thru | or 4th FET in the inverter apparatus of FIG. It is a circuit diagram which shows the inverter apparatus comprised by connecting the direct current | flow resistance in series with the capacitor | condenser in FIG. (A) thru | or (h) is a figure which shows the current waveform and voltage waveform of 1st thru | or 4th FET in the inverter apparatus of FIG. It is a figure which shows typically the wiring pattern on the board | substrate in 2nd Embodiment of the inverter apparatus of this invention. It is a figure which shows typically the wiring pattern on the board | substrate in the conventional inverter apparatus. It is a circuit diagram which shows the wiring connection of the conventional inverter apparatus. It is a figure which shows the flow of the electric current in operation | movement of step 1 of the conventional inverter apparatus. It is a figure which shows the flow of the electric current in operation | movement of step 2 of the conventional inverter apparatus. It is a figure which shows the flow of the electric current in operation | movement of step 3 of the conventional inverter apparatus. It is a figure which shows the flow of the electric current in operation | movement of step 4 of the conventional inverter apparatus. FIG. 8B is a circuit diagram showing a conventional inverter device configured by replacing the bipolar transistor in FIG. 8B with a field effect transistor. (A) thru | or (h) is a figure which shows the current waveform and voltage waveform of 1st thru | or 4th FET in the conventional inverter apparatus of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply 11-14 First to fourth transistors 15, 16, 31-38 Wiring portion 17 Inductive load 18 DC resistance 21-24 First to fourth diodes 41-44 First to fourth capacitors 52, 53, 56, 57, 55a, 55c, 56a, 56c Parasitic inductance 61-64 DC resistance

Claims (6)

The first and second switching elements are inserted in series between the DC power source and the ground, and the third and fourth switching elements are inserted in series, and the connection wiring between the first and second switching elements and the third And the fourth switching element are connected to each other through an inductive load, and the first to fourth diodes that flow currents in directions opposite to those of the first to fourth switching elements are used as the first to fourth switching elements, respectively. In parallel connection, the third and second switching elements are turned on, a DC power supply current is passed through the inductive load in one direction through the third and second switching elements, and then the third and second switching elements are turned off. Then, a one-way self-induced current is passed through the inductive load through the fourth and first diodes, and then the first and fourth switching elements are turned on, and the first and fourth switches are turned on. After the DC power supply current is passed through the inductive load in the reverse direction through the switching element, the first and fourth switching elements are turned off, and the self-inductive current is passed through the inductive load in the reverse direction through the second and third diodes. In the inverter device that repeats the switching operation and converts from DC voltage to AC voltage,
Connecting the anode of the first diode to a portion closer to the second switching element than the connection point between the connection wiring and the inductive load in the connection wiring between the first and second switching elements;
Connecting the cathode of the second diode to a portion closer to the first switching element than the connection point between the connection wiring and the inductive load in the connection wiring between the first and second switching elements;
Connecting the anode of the third diode to a portion closer to the fourth switching element than the connection point between the connection wiring and the inductive load in the connection wiring between the third and fourth switching elements;
An inverter device comprising: a cathode of a fourth diode connected to a portion of the connection wiring between the third and fourth switching elements closer to the third switching element than a connection point between the connection wiring and the inductive load. The connection distance on the wiring between the first switching element and the cathode of the second diode is shorter than the connection distance on the wiring between the second switching element and the anode of the second diode;
The connection distance on the wiring between the second switching element and the anode of the first diode is shorter than the connection distance on the wiring between the first switching element and the cathode of the first diode;
The connection distance on the wiring between the third switching element and the cathode of the fourth diode is shorter than the connection distance on the wiring between the fourth switching element and the anode of the fourth diode;
2. The inverter according to claim 1, wherein a connection distance on the wiring between the fourth switching element and the anode of the third diode is shorter than a connection distance on the wiring between the third switching element and the cathode of the third diode. apparatus.   Wiring between the first switching element and the cathode of the first diode, wiring between the second switching element and the anode of the second diode, wiring between the third switching element and the cathode of the third diode, and fourth switching element and fourth The inverter device according to claim 2, wherein at least one of the wirings between the anodes of the diodes is grounded via a capacitor.   4. The inverter apparatus according to claim 3, wherein a direct current resistor is connected in series with the capacitor.   Three or more sets of first and second switching elements or third and fourth switching elements inserted in series between the DC power source and the ground are provided, and the connection wiring between the switching elements of each set is connected via an inductive load. 2. The inverter device according to claim 1, wherein the diodes are connected in parallel and are connected in parallel to the switching elements.   The inverter device according to claim 1, wherein the first to fourth switching elements or the first to fourth diodes include a compound semiconductor such as SiC, GaAs, or GaN.

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