JP2010135631A - Interconnect structure and method of forming same, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To fine a connection portion having a linear structure made of carbon elements more by reducing the resistance of the connection portion. <P>SOLUTION: A via plug 33 and a base film 32b covering an inner wall surface of an interconnect groove 32a on the via plug 33 are formed simultaneously by burying a conductor material 34 in gaps between CNTs (Carbon Nano Tubes) 28 in a via hole 28a and hollows of the CNTs 28d by, for example, a supercritical CVD method such that the via hole 28a is filled and the inner wall surface of the interconnect groove 32a is covered. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a wiring structure using a linear structure made of a carbon element at a wiring connection portion, a method for forming the wiring structure, and a semiconductor device.

In a semiconductor device typified by an LSI or the like, a connection portion connected to a wiring or the like has a connection hole (contact hole, via hole, etc.) of a metal or alloy such as aluminum (Al), tungsten (W), copper (Cu), etc. Filled with and formed.
However, with the metal or alloy as described above, it is difficult to form a fine connection portion that meets the recent demand for further miniaturization and higher integration of semiconductor devices. In this case, with the metal or alloy as described above, it is considered that the electrical resistance value of the connection portion is increased and the current density is reduced. Therefore, it is expected that there will be limits in the future for connections filled with metals or alloys.

In order to cope with the above problems, attempts have been made to use a linear structure made of a carbon element such as carbon nanotube (CNT) as a filling material for a connecting portion (Patent Documents 1 to 4, Non-Patent Documents). Reference 1 to 3).
CNTs are excellent in fineness, electrical conduction characteristics and allowable current density characteristics, and are expected to be able to realize fine and low-resistance connections by applying them to conductive materials that embed contact holes or via holes. Yes.

  As a connection portion using CNTs, there is a technique (see Non-Patent Documents 1 to 3 and the like) in which a gap between CNTs in a connection hole is filled with an insulator after the CNT is formed in the connection hole. Further, in order to further reduce the resistance of the connection portion, a technique for filling a gap between the CNTs in the connection hole with a conductive material (see Patent Documents 1 and 2, etc.) has been devised.

JP-A-2005-109465 Special table 2007-525030 gazette JP 2006-108210 A JP-A-2005-72171 IEEE International Interconnect Technology Conference 2006, pp.230. IEEE International Interconnect Technology Conference 2007, pp.204. IEEE International Interconnect Technology Conference 2008, pp.237.

As described above, an attempt has been made to further reduce the resistance of the connection portion by filling the gap between the CNTs in the connection hole with a conductive material.
However, in order to cope with the demand for further miniaturization of the connection part, there is a problem that a sufficient reduction in resistance cannot be obtained even with the technique of filling the gap between the CNTs in the connection hole with a conductive material.

  The present invention has been made in view of the above-described problems, and realizes further reduction in resistance of a connection portion having a linear structure made of a carbon element, thereby enabling further miniaturization of the connection portion. An object is to provide a wiring structure, a method for forming the wiring structure, and a semiconductor device.

  One aspect of the wiring structure includes a wiring and a connecting portion electrically connected to the wiring, and the connecting portion fills a linear structure made of a carbon element and a gap between the linear structures. And a conductive material filling the hollow of the linear structure.

  One embodiment of a semiconductor device is a semiconductor device in which a functional element is formed on a semiconductor substrate, and a wiring formed above the semiconductor substrate and a connection electrically connected to the wiring under the wiring The connecting portion includes a linear structure made of a carbon element, and a conductive material that fills a space between the linear structures and fills a hollow space of the linear structure. Is formed.

  Another aspect of the semiconductor device is a semiconductor device in which a functional element and a wiring are formed on a semiconductor substrate, and an electrode connected to the wiring above the wiring and a connection bump formed on the electrode. And the connection bump is formed to include a linear structure made of carbon element and a conductive material that fills a space between the linear structures and fills the hollow space of the linear structure. ing.

  One aspect of a method for forming a wiring structure is a method for forming a wiring structure including a wiring and a connection portion electrically connected to the wiring, wherein the connection portion includes a linear structure made of a carbon element. After the formation, the gap between the linear structures is filled with the conductive material and the hollows of the linear structures are filled.

  According to each aspect described above, the connection portion having a linear structure made of a carbon element can be further reduced in resistance, and the connection portion can be further miniaturized.

―Basic outline of this embodiment―
Examples of the linear structure made of carbon element include carbon nanotubes (CNT) and carbon nanofibers (CNF). Such a linear structure generally has a hollow structure.
In this embodiment, paying attention to the hollow structure of the linear structure, after forming the linear structure in the connection hole of the wiring structure, the conductive material is filled in the gaps between the linear structures and the linear structure The structure filled in the hollow is adopted. With this configuration, the connection portion using the linear structure can be made as low as possible, and further miniaturization of the connection portion can be realized without sacrificing the reduction in resistance.

The conductive material filling the gaps between the linear structures and the hollows of the linear structures is one selected from Ti, Ta, Ru, TiN, TaN, or one selected from an alloy containing Au and Au. Is preferably used.
One type selected from Ti, Ta, Ru, TiN, and TaN is a conductive material that is usually used as a base film (barrier film) of a wiring formed on a connection portion. By using this base film material as a material for filling the gaps between the linear structures and the hollows of the linear structures, the connecting portion, the connecting portion, and the base film can be integrally formed at the same time. By integrally forming the connection portion and the base film, the manufacturing process can be simplified, and since there is no conductive material interface between the connection portion and the base film, the resistance value due to the presence of the interface is reduced. The rise can be prevented.

  Au or an alloy containing Au is a low-resistance conductive material and can be processed by etching. By using this low-resistance conductive material as a material for filling the gaps between the linear structures and the hollows of the linear structures and as a material for forming the wiring, the resistance of the wiring structure is reduced as much as possible. To do.

-Specific aspects of this embodiment-
Hereinafter, specific aspects of the present embodiment will be described in detail with reference to the drawings. In the following embodiments, a semiconductor device including a MOS transistor is exemplified as a functional element having a wiring structure, and the structure will be described together with a manufacturing method.

(First embodiment)
1 to 3 are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps.
First, as shown in FIG. 1A, a MOS transistor 20 which is one of functional elements is formed on a silicon semiconductor substrate 10.
Specifically, the element isolation structure 11 is formed on the surface layer of the silicon semiconductor substrate 10 by, for example, STI (Shallow Trench Isolation) method, and the element active region is defined on the semiconductor substrate 10.
Next, impurities are ion-implanted into the element active region to form the well 12. As an impurity to be ion-implanted, an N-type impurity such as phosphorus (P ⁺ ) or arsenic (As ⁺ ) is used when manufacturing a PMOS transistor, and a P-type such as boron (B ⁺ ) is used when manufacturing an NMOS transistor. Impurities are used.

  Next, a thin gate insulating film 13 is formed in the element active region by a thermal oxidation method or the like, and a polycrystalline silicon film and a silicon nitride film are deposited on the gate insulating film 13 by a CVD method or the like. Then, the silicon nitride film, the polycrystalline silicon film, and the gate insulating film 13 are processed into electrode shapes by lithography and subsequent dry etching. Thus, the gate electrode 14 made of a polycrystalline silicon film is formed on the gate insulating film 13. At the same time, a cap film 15 made of a silicon nitride film is formed on the gate electrode 14.

Next, using the cap film 15 as a mask, impurities are ion-implanted into the well 12 with a predetermined dose and acceleration energy to form a pair of extension regions 16. As an impurity to be ion-implanted, a P-type impurity such as boron (B ⁺ ) is used when a PMOS transistor is manufactured, and an N-type such as phosphorus (P ⁺ ) or arsenic (As ⁺ ) is used when an NMOS transistor is manufactured. Impurities are used.

Next, for example, a silicon oxide film is deposited on the entire surface by a CVD method or the like, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surfaces of the gate electrode 14 and the cap film 15. 17 is formed.
Next, using the cap film 15 and the sidewall insulating film 17 as a mask, an impurity is ion-implanted into the well 12 under a condition deeper than the extension region 16 to form a pair of source / drain regions 18. As an impurity to be ion-implanted, a P-type impurity such as boron (B ⁺ ) is used when a PMOS transistor is manufactured, and an N-type such as phosphorus (P ⁺ ) or arsenic (As ⁺ ) is used when an NMOS transistor is manufactured. Impurities are used.
Thus, the MOS transistor 20 having the gate electrode 14, the extension region 16, and the source / drain region 18 is formed.

Subsequently, as shown in FIG. 1B, an interlayer insulating film 22 and contact plugs 23 electrically connected to the source / drain regions 18 in the interlayer insulating film 22 are sequentially formed.
Specifically, first, for example, a silicon oxide film is deposited by CVD or the like so as to cover the MOS transistor 20 to form an interlayer insulating film 22.
Next, the interlayer insulating film 22 is processed by lithography and subsequent dry etching so that a part of the surface of the source / drain region 18 is exposed, and a contact hole 23 a is formed in the interlayer insulating film 22.

Next, Ti, TiN, or a laminated film of Ti and TiN is deposited on the interlayer insulating film 22 by a sputtering method or the like so as to cover the inner wall surface of the contact hole 23a, thereby forming a base film 23b.
Next, a conductive material, for example, tungsten (W) is deposited on the interlayer insulating film 22 by a CVD method or the like so as to fill the contact hole 23a through the base film 23b. Then, W and the base film 23b are polished by a chemical-mechanical polishing (CMP) method until the surface of the interlayer insulating film 22 is exposed, and the contact hole 23a is filled with W through the base film 23b. Contact plug 23 is formed.

Subsequently, as shown in FIG. 1C, an interlayer insulating film 24 and a lower wiring 25 electrically connected to the contact plug 23 in the interlayer insulating film 24 are sequentially formed.
Specifically, first, for example, a silicon oxide film is deposited on the interlayer insulating film 22 by a CVD method or the like so as to cover the contact plug 23, thereby forming the interlayer insulating film 24.

Next, the lower wiring 25 is formed by a so-called single damascene method.
First, the interlayer insulating film 24 is processed by lithography and subsequent dry etching so that at least a part of the upper surface of the contact plug 23 is exposed to the bottom surface, thereby forming a wiring groove 25 a in the shape of the wiring in the interlayer insulating film 24.
Next, Ti, TiN, a laminated film of Ti and TiN, or the like is deposited on the interlayer insulating film 24 by a sputtering method or the like so as to cover the inner wall surface of the wiring trench 25a, thereby forming a base film 25b.
Next, copper (Cu) or the like is deposited on the base film 25b by sputtering or the like so as to cover the inner wall surface of the wiring groove 25a via the base film 25b, thereby forming a plating seed film (not shown).

  Next, by a plating method, a conductive material such as Cu or Cu alloy is grown on the plating seed film so as to fill the wiring groove 25a with the conductive material through the base film 25b. Then, the conductive material is polished by CMP until the surface of the interlayer insulating film 24 is exposed, and the lower wiring 25 filling the wiring trench 25a with the conductive material via the base film 25b is formed. Here, the plating seed film is integrated with the conductive material.

Subsequently, as shown in FIG. 1D, a protective film 26 and an interlayer insulating film 27 are sequentially formed, and then a via hole 28 a is formed in the interlayer insulating film 27.
Specifically, first, SiN or the like is deposited on the interlayer insulating film 24 so as to cover the lower wiring 25 by a CVD method or the like, and a protective film 26 is formed.
Next, SiOC or the like is deposited on the protective film 26 by a plasma CVD method or the like to a thickness of about 200 nm, for example, to form an interlayer insulating film 27.
Next, the interlayer insulating film 27 is processed by lithography and subsequent dry dry etching using a fluorine-based gas or the like so that a part of the upper surface of the lower wiring 25 is exposed, and vias are formed in the interlayer insulating film 27 and the protective film 26. Hole 28a is formed.

Subsequently, as shown in FIG. 2A, after forming the base film 28b, the fine particle catalyst 28c is deposited. 2A to 3C, the illustration of the configuration of the lower portion of the lower wiring 25 is omitted.
Specifically, first, a base conductive material is deposited on the interlayer insulating film 27 including the bottom surface of the via hole 28a by a sputtering method or the like to form the base film 28b. The base conductive material is preferably one or more selected from Ti, Ta, TiN, and TaN (becomes a laminated film).
By using Ta or TaN as the base conductive material, it becomes a base film that satisfactorily protects the lower wiring 25 and Cu diffusion from the lower wiring 25 is prevented. By using Ti or TiN as the base conductive material, an excellent electrical and mechanical contact layer for the lower wiring 25 is obtained. In the present embodiment, the Ta film 28b-1 and the TiN film 28b-2 are stacked and deposited to form the base film 28b.

  In this embodiment, anisotropic long slow sputtering is used for depositing the underlying conductive material. This anisotropic long throw sputtering method is a sputtering method having a distance larger than the target diameter as a target-sample distance as a method for forming a highly anisotropic thin film. By using the anisotropic long throw sputtering method, adhesion of the underlying conductive material to the side wall of the via hole 28a is prevented. Since the base conductive material is deposited only on the bottom surface in the via hole 28a, the via hole 28a is not occupied by the base film 28b having a higher resistance than the CNT described later, and a via plug having as low resistance as possible is realized. Is done.

Next, a fine particle catalyst 28 c serving as a catalyst for growing CNTs is deposited on the bottom surface of the via hole 28 a and the base film 28 b formed on the interlayer insulating film 27. As the fine particle catalyst 28c, one kind selected from Co, Fe and Ni, or a binary metal (TiCo, NbCo, etc.) containing at least one kind selected from Co, Fe and Ni, or Co, Fe, It is preferable to use an alloy containing at least two of Ni. In this embodiment, Co is used, and Co fine particles are deposited by a laser ablation method, a sputtering method, or a vapor deposition method to form a fine particle catalyst 28c.
In the present embodiment, it is preferable to increase the anisotropy of the deposition of the particulate catalyst 28c by, for example, depositing on the particulate catalyst 28c semiconductor substrate via a differential exhaust mechanism in a vacuum chamber.
Instead of depositing the particulate catalyst 28c, for example, a thin catalyst film (Co film or the like) having a thickness of about 1 nm is formed on the bottom surface of the via hole 28a and the base film 28b formed on the interlayer insulating film 27. May be.

Subsequently, as shown in FIG. 2B, CNTs 28d, which are linear structures made of carbon elements, are grown.
Specifically, the CNTs 28d are vertically aligned and grown from the fine particle catalyst 28c in contact with the base film 28b by a CVD method or the like. As growth conditions for the CNT 28d, for example, a thermal CVD method is used, a mixed gas of acetylene / argon is introduced into the vacuum chamber as a reaction gas, the pressure is set to about 1 kPa, and the substrate temperature is set to about 400 ° C. to 450 ° C. The flow rate of acetylene (10% argon dilution) / argon is, for example, 0.5 sccm / 1000 sccm. The growth rate of the CNT 28d is about 1 μm / hour.

In the growth of the CNT 28d, a hot filament CVD method in which gas dissociation is performed by a hot filament may be used instead of the thermal CVD method. In that case, the hot filament temperature is set to about 900 ° C. to 1800 ° C., for example. Further, a plasma CVD method may be used.
In the present embodiment, the case where CNT is formed as a linear structure made of a carbon element has been exemplified. However, for example, carbon nanofiber (CNF) may be formed instead of CNT.

Subsequently, as shown in FIG. 2C, an insulating filling material 29 is deposited so as to fill the gaps between the formed CNTs 28d.
Specifically, on the interlayer insulating film 27 including the inside of the via hole 28a, for example, a coating type organic SOG (Spin-on glass) is spin-coated so as to fill the gap between the formed CNTs 28d, and the filling material 29 is coated. accumulate. At this time, the space between the CNTs 28d is filled with the filling material 29 to form a composite layer of the CNTs 28d and the filling material 29 (hereinafter referred to as a CNT / SOG composite layer). Here, in order to increase the wettability of application of organic SOG, oxygen plasma treatment, ozone treatment, UV treatment, or the like may be appropriately performed on the semiconductor substrate 10 before application.

  After spin coating of organic SOG, the filling material 29 is cured by baking (for example, 250 ° C. for 5 minutes) and curing (for example, 400 ° C. for 30 minutes) on the semiconductor substrate 10. It is preferable to use a porous type organic SOG because there are no defects such as cracks after curing. The insulator filling material 29 may be deposited using a plasma CVD method, but it is preferable to use a coating SOG excellent in embedding in the gap between the CNTs 28d. In addition, inorganic SOG may be used instead of organic SOG.

Subsequently, as shown in FIG. 2D, the CNT / SOG composite layer and the base film 28b on the interlayer insulating film 27 are planarized so that the CNT / SOG composite layer remains only in the via hole 28a. Remove.
Specifically, the polishing of the CNT / SOG composite layer (first polishing) and the polishing of the base film 28b on the interlayer insulating film 27 (second polishing) are sequentially performed by CMP.

In the first polishing, for example, a slurry for an oxide film (alkali) is used, and the base film 28b is used as a polishing stopper. The first polishing is preferably high-selective polishing in which organic SOG> TaN or Ta with respect to the polishing rate of TaN or Ta of the base film 28b and the polishing rate of organic SOG (SiO ₂ ) of the filling material 29. Further, since the polishing rate tends to decrease as the quality of the CNT becomes higher, the polishing rate of the CNT 28d can be increased by using an acid-based slurry. However, in this case, since the polishing rate of the organic SOG decreases, the hydrogen ion concentration (pH) of the slurry is appropriately adjusted so that the desired flatness of the CNT / SOG composite layer can be obtained.

The second polishing is performed using Ta slurry (acid-based) and the interlayer insulating film 27 as a polishing stopper (until the surface of the interlayer insulating film 27 is exposed). The second polishing is preferably highly selective polishing such that TaN or Ta> SiOC with respect to the TaN or Ta polishing rate of the base film 28b and the SiOC polishing rate of the interlayer insulating film 27.
Then, as a post-process of CMP, the semiconductor substrate 10 is subjected to a surface treatment using, for example, dilute hydrofluoric acid (5%) to remove the polishing residue.

Subsequently, as shown in FIG. 3A, after the protective film 21 and the interlayer insulating film 31 are sequentially formed, a wiring groove 32 a is formed in the interlayer insulating film 31 and the protective film 21.
Specifically, SiN or the like is deposited on the interlayer insulating film 27 by a CVD method or the like so as to cover the CNT / SOG composite layer, thereby forming the protective film 21.
Next, SiO ₂ or SiOC is deposited on the protective film 21 by a CVD method or the like to form an interlayer insulating film 31.
Next, the interlayer insulating film 31 and the protective film 21 are processed by lithography and subsequent dry etching so that the upper surface of the CNT / SOG composite layer is exposed on the bottom surface, and wiring having a wiring shape is formed on the interlayer insulating film 31 and the protective film 21. A groove 32a is formed.

Subsequently, as shown in FIG. 3B, after the filling material 29 in the via hole 28a is removed, the via plug 33 and the base film 32b are simultaneously formed.
Specifically, first, in the via hole 28a exposed from the bottom surface of the wiring groove 32a, the filling material 29 filling the gap between the CNTs 28d is removed by performing a wet treatment using, for example, dilute hydrofluoric acid (5%). .

Next, a conductive material 34 is deposited so as to fill the via hole 28a and cover the inner wall surface of the wiring groove 32a. In the present embodiment, the gap between the CNTs 28d in the via hole 28a and the inside of the CNT 28d are filled with the conductive material 34. FIG. 4 shows a state in which the conductive material 34 is embedded in the hollow of the CNT 28d. As the conductive material 34, it is preferable to use one selected from Ti, Ta, Ru, TiN, and TaN, which has a low resistance and is also suitable as a base material when forming a wiring by a single damascene method. Here, the case where Ti is used as the conductive material 34 is illustrated. For the deposition of the conductive material 34, a supercritical CVD method capable of selectively embedding the deposit in a fine space is used. In the supercritical CVD method, for example, CO ₂ is used as a medium. The critical point of CO ₂ is a pressure of 7.4 MPa and a temperature of 31 ° C. The raw material (organometallic complex) of the conductive material 34 is dissolved in supercritical CO ₂ and deposited. As a result, the via plug 33 in which the gap between the CNTs 28d in the via hole 28a and the hollow of the CNT 28d are filled with the conductive material 34, and the base film 32b covering the inner wall surface of the wiring groove 32a on the via plug 33 are simultaneously formed. The

As shown in FIG. 3C, the upper wiring 32 is formed.
Specifically, copper (Cu) or the like is deposited on the base film 32b by sputtering or the like so as to cover the inner wall surface of the wiring groove 32a via the base film 32b, thereby forming a plating seed film (not shown).
Next, by a plating method, a conductive material such as Cu or Cu alloy is grown on the plating seed film so as to fill the wiring trench 32a with the conductive material through the base film 32b. Then, the conductive material is polished by CMP until the surface of the interlayer insulating film 31 is exposed, and the upper wiring 32 that fills the wiring trench 32a with the conductive material through the base film 32b is formed. As a result, the wiring structure 30 in which the via plug 33 and the upper wiring 32 are electrically connected is formed.
Here, after the upper wiring 32 is formed, the semiconductor substrate 10 may be heat-treated at 400 ° C., for example. By this heat treatment, electrical bonding between the CNT 28d and the base film 32b is improved.

  Thereafter, one or more additional upper layer wiring structures are formed so as to be electrically connected to the wiring structure 30, and pad electrodes for external connection connected to the respective wiring structures are formed on the uppermost insulating film. A semiconductor device is formed through formation and the like. Here, the upper wiring structure is preferably formed in the same manner as the wiring structure 30.

  As described above, according to the present embodiment, the via plug 33 having the CNT 28d can be further reduced in resistance, and the via plug 33 can be further miniaturized.

(Modification)
Here, a modification of the first embodiment will be described. In this modification, a semiconductor device is manufactured as in the first embodiment, but a contact plug connected to the source / drain region is formed in the same manner as the via plug 33.
5 and 6 are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the modification of the first embodiment.

In this example, first, the process of FIG. 1A of the first embodiment is executed.
Subsequently, as shown in FIG. 5A, an interlayer insulating film 22 and a contact hole 23a are formed as in FIG.

Subsequently, as shown in FIG. 5B, after forming the base film 28b, the fine particle catalyst 41b is deposited. In FIG. 5B to FIG. 6D, the illustration of the configuration below the source / drain region 18 is omitted.
Specifically, first, a base conductive material is deposited on the interlayer insulating film 22 including the bottom surface of the contact hole 23a to form a base film 41a. The base film 41a is formed as a laminated film of the Ta film 41a-1 and the TiN film 41a-2 by the anisotropic long slow sputtering method using the same base conductive material as the base film 28b in the first embodiment. To do.

  Next, a fine particle catalyst 41b serving as a catalyst for growing CNTs is deposited on the bottom surface of the contact hole 23a and the base film 41a formed on the interlayer insulating film 22. As the fine particle catalyst 41b, similarly to the fine particle catalyst 28c of FIG. 2A, for example, Co is used, and Co fine particles are deposited by a laser ablation method, a sputtering method, or an evaporation method to form the fine particle catalyst 41b.

Subsequently, as shown in FIG. 5C, CNTs 41c are grown from the particulate catalyst 41b. The growth conditions for the CNT 41c are the same as the growth conditions for the CNT 28d in FIG.
Subsequently, as shown in FIG. 5D, an insulating filler material 42 is deposited so as to fill the gaps between the formed CNTs 41c. As the filling material 42, organic SOG is used in the same manner as the filling material 29 in FIG. 2C, and deposited under the same deposition conditions to form a CNT / SOG composite layer.

Subsequently, as shown in FIG. 6A, the CNT / SOG composite layer is planarized so that the CNT 41c remains only in the contact hole 23a. This flattening process is performed in the same manner as the flattening process of the CNT / SOG composite layer in the first embodiment.
Subsequently, as shown in FIG. 6B, an interlayer insulating film 24 and a wiring trench 25a are formed as in the first embodiment.

Subsequently, as shown in FIG. 6C, after the filling material 42 in the contact hole 23a is removed, the contact plug 43 and the base film 45a are simultaneously formed.
The removal of the filling material 42 in the contact hole 23a is performed in the same manner as the removal of the filling material 29 in the via hole 28a in the first embodiment. For example, Ti is deposited as the conductive material 44 so as to fill the contact hole 23a and cover the inner wall surface of the wiring groove 25a using the supercritical CVD method under the same conditions as those for forming the via plug 33 in the first embodiment. To do. In this example, the gap between the CNTs 41 c in the contact hole 23 a and the hollow space of the CNTs 41 c are embedded with the conductive material 44. As a result, the contact plug 43 in which the gap between the CNTs 41c in the contact hole 23a and the hollow space of the CNT 41c are filled with the conductive material 44 and the base film 45a covering the inner wall surface of the wiring groove 25a on the contact plug 43 are simultaneously provided. It is formed.

Subsequently, as shown in FIG. 6D, the single damascene method is performed in the same manner as the formation of the lower wiring 25 in the first embodiment. As a result, the lower wiring 45 that fills the wiring trench 25a with the conductive material such as Cu or Cu alloy through the base film 45a is formed. A wiring structure 40 is configured in which the contact plug 43 and the lower wiring 45 are electrically connected via a base film 45a.
Thereafter, the same processes as those in FIGS. 1D to 3C in the first embodiment are performed to form a semiconductor device.

  As described above, according to this example, in addition to further reducing the resistance of the via plug 33 having the CNTs 28d, the contact plug 43 having the CNT 41c can be further reduced in resistance, and the via plug 33 and the contact plug 43 can be reduced. Can be further miniaturized.

(Second Embodiment)
FIG. 7 is a schematic cross-sectional view showing the main steps of the semiconductor device manufacturing method according to the second embodiment.
In this embodiment, first, each process of FIG. 1A to FIG. 2B of the first embodiment is sequentially performed.

Subsequently, as shown in FIG. 7A, a conductive material 51 is deposited so as to fill the gaps between the formed CNTs 28d and the hollows of the CNTs 28d.
Specifically, the gap between the CNTs 28d on the interlayer insulating film 27 and in the via holes 28a and the inside of the hollows of the CNTs 28d (similar to FIG. 4) are embedded with the conductive material 51. As the conductive material 51, it is preferable to use one selected from Ti, Ta, Ru, TiN, and TaN which are low resistance. Here, the case where Ti is used as the conductive material 51 is illustrated. For the deposition of the conductive material 51, a supercritical CVD method capable of selectively filling a fine space with a deposit is used. In the supercritical CVD method, for example, CO ₂ is used as a medium. The critical point of CO ₂ is a pressure of 7.4 MPa and a temperature of 31 ° C. Deposition is performed by dissolving the raw material (organometallic complex) of the conductive material 51 in supercritical CO ₂ . Thereby, the space between the CNTs 28d in the via hole 28a and the hollow space of the CNTs 28d are filled with the conductive material 51, and a composite layer of the CNT 28d and the conductive material 51 (hereinafter referred to as a CNT / Ti composite layer). Is formed).

Subsequently, as shown in FIG. 7B, a via plug 52 is formed.
Specifically, the CNT / Ti composite layer and the base film 28b on the interlayer insulating film 27 are removed by planarization so that the CNT 28d remains only in the via hole 28a by CMP. In this flattening treatment, polishing is performed using Ta slurry (acid-based) and the interlayer insulating film 27 as a polishing stopper (until the surface of the interlayer insulating film 27 is exposed). This polishing is preferably highly selective polishing such that Ta> SiOC with respect to the Ta polishing rate of the base film 28b and the SiOC polishing rate of the interlayer insulating film 27.

  Then, as a post-process of CMP, the semiconductor substrate 10 is subjected to a surface treatment using, for example, dilute hydrofluoric acid (5%) to remove the polishing residue. As described above, the via plug 52 in which the gap between the CNTs 28d in the via hole 28a and the hollow of the CNT 28d are filled with the conductive material 51 is formed.

Subsequently, as shown in FIG. 7C, after the protective film 21, the interlayer insulating film 31, and the wiring trench 32a are formed, a base film 53a is formed.
Specifically, first, as in the first embodiment, after the protective film 21 and the interlayer insulating film 31 are sequentially formed, at least a part of the top surface of the via plug 52 is formed on the bottom surface of the interlayer insulating film 31 and the protective film 21. A wiring groove 32a is formed so as to be exposed.
Next, Ti, TiN, a laminated film of Ti and TiN, or the like is deposited on the interlayer insulating film 31 by a sputtering method or the like so as to cover the inner wall surface of the wiring groove 32a, thereby forming a base film 53a.

Subsequently, as shown in FIG. 7D, the upper wiring 53 is formed.
Specifically, first, copper (Cu) or the like is deposited on the base film 53a by sputtering or the like so as to cover the inner wall surface of the wiring groove 32a via the base film 53a, thereby forming a plating seed film (not shown). .
Next, by a plating method, a conductive material such as Cu or Cu alloy is grown on the plating seed film so as to fill the wiring groove 32a with the conductive material through the base film 53a. Then, the conductive material is polished by CMP until the surface of the interlayer insulating film 31 is exposed, and the upper wiring 53 that fills the wiring trench 32a with the conductive material through the base film 53a is formed. Thus, the wiring structure 50 in which the via plug 52 and the upper wiring 53 are electrically connected is formed.

  Here, after the upper wiring 53 is formed, the semiconductor substrate 10 may be heat-treated at 400 ° C., for example. By this heat treatment, electrical bonding between the CNT 28d and the base film 53a is improved.

  Thereafter, one or more additional upper layer wiring structures are formed so as to be electrically connected to the wiring structure 50, and a semiconductor device is formed through formation of a protective film and pad electrodes for external connection. Here, the upper wiring structure is preferably formed in the same manner as the wiring structure 50.

  As described above, according to the present embodiment, the via plug 52 having the CNTs 28d can be further reduced in resistance, and the via plug 52 can be further miniaturized.

Also in this embodiment, as in the modification of the first embodiment, the contact plug connected to the source / drain region may be formed in the same manner as the via plug 52.
In addition, for each of the via plug, which is a component of the wiring structure, and the contact plug connected to the source / drain region, the configuration of the via plug 33 in the first embodiment and the configuration of the via plug 52 in the second embodiment. In addition, it may be applied by interweaving as appropriate.

(Third embodiment)
8 and 9 are schematic cross-sectional views showing the main steps of the semiconductor device manufacturing method according to the third embodiment.
In this embodiment, first, each process of FIG. 1A and FIG. 1B of the first embodiment is sequentially executed.

Subsequently, as shown in FIG. 8A, a base film 61a and a lower wiring 61 are sequentially formed.
Specifically, Ti, TiN, a laminated film of Ti and TiN, or the like is deposited on the interlayer insulating film 22 by sputtering or the like so as to cover the contact plug 23 to form a base film 61.
Next, gold (Au) or an Au alloy is deposited on the base film 61a by vacuum vapor deposition, sputtering, or electroplating. Then, the deposited gold (Au) or Au alloy and the base film 61 are processed by lithography and milling so as to have an electrode shape on the contact plug 23, and electrically through the contact plug 23 and the base film 61a. A lower wiring 61 to be connected is formed.

Subsequently, as shown in FIG. 8B, after forming the interlayer insulating film 63, a via hole 64 a is formed in the interlayer insulating film 63.
Specifically, first, SiO ₂ or the like is deposited on the interlayer insulating film 22 to a thickness of, for example, about 500 nm on the interlayer insulating film 22 so as to cover the lower wiring 61, thereby forming the interlayer insulating film 63.
Next, a resist is applied onto the interlayer insulating film 63, and the resist is patterned by lithography to form a resist mask 65 having an opening 65a at a portion where a via hole is to be formed in the resist. Then, the interlayer insulating film 63 is dry-etched using a fluorine-based gas or the like using the resist mask 65, and a via hole 64 a that exposes a part of the upper surface of the lower wiring 61 is formed in the interlayer insulating film 63.

Subsequently, as shown in FIG. 8C, after the base film 64b is formed, the fine particle catalyst 64c is deposited. In FIG. 8C to FIG. 9D, the illustration of the configuration of the lower portion of the lower wiring 61 is omitted.
Specifically, first, a base conductive material is deposited on the interlayer insulating film 63 including the bottom surface of the via hole 64a by a sputtering method or the like while leaving the resist mask 65 used for lithography at the time of forming the via hole 64a. A base film 64b is formed. As the base conductive material, one or more selected from Ti, Ta, TiN, and TaN (becomes a laminated film) are used. By using Ta or TaN as the base conductive material, a base film that satisfactorily protects the lower wiring 61 is obtained, and Au diffusion from the lower wiring 61 is prevented. By using Ti or TiN as the base conductive material, a good electrical and mechanical contact layer for the lower wiring 61 is obtained. In this embodiment, similarly to the base film 28b of FIG. 2A, a Ta film 64b-1 and a TiN film 64b-2 are stacked and deposited by anisotropic long throw sputtering, and the base film 64b is formed. Form.

Next, a fine particle catalyst 64c serving as a catalyst for growing CNTs is deposited on the bottom surface of the via hole 64a and the resist mask 65.
As the fine particle catalyst 64c, similarly to the fine particle catalyst 28c of FIG. 2A, for example, Co is used, and Co fine particles are deposited by a laser ablation method, a sputtering method, or an evaporation method to obtain the fine particle catalyst 64c.

Subsequently, as shown in FIG. 8D, after removing the resist mask 65, a CNT 64d is grown.
Specifically, first, the resist mask 65 is removed by a wet process using hydrofluoric acid (HF) or the like using a lift-off method. At this time, the fine particle catalyst 64c is deposited only on the bottom surface of the via hole 64a.
Next, CNT 64d is grown from the particulate catalyst 64c deposited on the bottom surface of the via hole 64a. The growth conditions for CNT 64d are the same as the growth conditions for CNT 28d in FIG.

  Subsequently, as shown in FIG. 9A, an insulating filling material 66 is deposited so as to fill the gaps between the formed CNTs 64d. As the filling material 66, organic SOG is used in the same manner as the filling material 29 in FIG. 2C, and deposited under the same deposition conditions to form a CNT / SOG composite layer.

Subsequently, as shown in FIG. 9B, the CNT / SOG composite layer is planarized by CMP so that the CNT 64d remains only in the via hole 64a. This planarization treatment is preferably high-selective polishing in which organic SOG> SiO ₂ with respect to the polishing rate of SiO ₂ of the interlayer insulating film 63 and organic SOG (SiO ₂ ) of the filling material 66. Further, since the polishing rate tends to decrease as the quality of the CNT becomes higher, the polishing rate of the CNT 64d can be increased by using an acid-based slurry. However, in this case, since the polishing rate of the organic SOG decreases, the hydrogen ion concentration (pH) of the slurry is appropriately adjusted so that the desired flatness of the CNT / SOG composite layer can be obtained. The base film 64b on the interlayer insulating film 63 is left without being removed by polishing.

Subsequently, as shown in FIG. 9C, after the filling material 66 in the via hole 64a is removed, a via plug 68 is formed.
Specifically, first, the filling material 66 filling the gaps between the CNTs 64d in the via holes 64a is removed by performing a wet process using, for example, dilute hydrofluoric acid (5%).
Next, a conductive material 67 is deposited so as to fill the via hole 64a. In the present embodiment, the gap between the CNTs 64d in the via hole 64a and the hollow space of the CNTs 64d (similar to FIG. 4) are filled with the conductive material 67. As the conductive material 67, the same material (Au or Au alloy) as that of the lower wiring 61 is used. In the present embodiment, the conductive material 67 is deposited using the supercritical CVD method under the same conditions as those for forming the via plug 33 in the first embodiment. The conductive material 67 grows so as to fill the gap between the CNTs 64d in the via hole 64a, which is a fine space, and the hollow space of the CNT 64d, and when the via hole 64a is filled, the supercritical CVD is terminated. At this time, the via plug 68 is formed by filling the gap between the CNTs 64d in the via hole 64a and the hollow space of the CNT 64d with the conductive material 67 in a state where the conductive material 67 is not yet deposited on the base film 64b covering the interlayer insulating film 63. Is formed.
In this embodiment, the via plug 68 can be formed by filling the conductive material 67 only in the via hole 64a without performing a planarization process such as a CMP method.

Subsequently, as shown in FIG. 9D, an upper wiring 69 is formed.
Specifically, gold (Au) or an Au alloy is deposited on the interlayer insulating film 63 by vacuum deposition, sputtering, or electroplating. Then, the deposited gold (Au) or Au alloy and the base film 64b on the interlayer insulating film 63 are processed by lithography and milling methods so as to have an electrode shape on the via plug 68, and are electrically connected to the via plug 68. An upper wiring 69 is formed. Thus, the wiring structure 60 in which the via plug 68 and the upper wiring 69 are electrically connected is formed.

  Thereafter, one or more additional upper layer wiring structures are formed so as to be electrically connected to the wiring structure 60, and a semiconductor device is formed through formation of a protective film and pad electrodes for external connection. Here, the upper wiring structure is preferably formed in the same manner as the wiring structure 60.

  As described above, according to the present embodiment, the via plug 68 having the CNT 64d can be further reduced in resistance, and the via plug 68 can be further miniaturized.

  In the present embodiment, the case where Au or Au alloy is filled in the via hole 64a by the supercritical CVD method when the via plug 68 is formed is illustrated. Instead of filling Au or Au alloy, the via hole 64a is filled with one kind selected from Ti, Ta, Ru, TiN, and TaN by the supercritical CVD method as in the first embodiment to form a via plug. You may do it. In this case, when forming the upper wiring 69, it is preferable to form Ti, TiN or a laminated film of these as a contact layer between the via plug and the upper wiring 69.

Similarly to the modification of the first embodiment, the contact plug connected to the source / drain region may be formed in the same manner as the via plug 68.
Similarly to the second embodiment, a via plug connected to the lower wiring 61 may be formed similarly to the via plug 52.

(Fourth embodiment)
FIG. 10 is a schematic cross-sectional view showing the main steps of the semiconductor device manufacturing method according to the fourth embodiment.
In this embodiment, first, each process of FIG. 1 (a) and FIG.1 (b) of 1st Embodiment is performed.

Subsequently, as shown in FIG. 10A, a base film 71a and a lower wiring 71 are sequentially formed.
Specifically, Ti, TiN, a laminated film of Ti and TiN, or the like is deposited on the interlayer insulating film 22 by sputtering or the like so as to cover the contact plug 23, thereby forming a base film 71a.
Next, indium tin oxide (indium oxide added with tin oxide: ITO) is deposited on the base film 71a by, for example, plasma sputtering. Then, the deposited ITO and the underlying film 71a are processed by lithography and milling so as to have an electrode shape on the contact plug 23, and are electrically connected via the contact plug 23 and the underlying film 71a. Form.

Then, each process similar to FIG.8 (b)-FIG.9 (b) of 3rd Embodiment is performed.
Subsequently, as shown in FIG. 10B, after the filling material 66 in the via hole 64a is removed, the via plug 74 is formed. In FIG. 10B to FIG. 10C, the illustration of the configuration of the lower portion of the lower wiring 71 is omitted.
Specifically, first, the filling material 66 filling the gaps between the CNTs 64d in the via holes 64a is removed by performing a wet process using, for example, dilute hydrofluoric acid (5%).

A conductive material 73 is deposited so as to fill the via hole 64a. In the present embodiment, the gap between the CNTs 64d in the via hole 64a and the hollow space of the CNT 64d (similar to FIG. 4) are embedded with the conductive material 73. As the conductive material 73, one selected from Ti, Ta, Ru, TiN, and TaN is used. In the present embodiment, the conductive material 73 is deposited using the supercritical CVD method under the same conditions as those for forming the via plug 33 in the first embodiment. The conductive material 73 grows so as to fill the gap between the CNTs 64d in the via hole 64a, which is a fine space, and the hollow space of the CNT 64d, and the supercritical CVD is terminated when the via hole 64a is filled. At this time, the via plug 74 is formed by filling the gap between the CNTs 64d in the via hole 64a and the hollow space of the CNT 64d with the conductive material 67 in a state where the conductive material 73 is not yet deposited on the base film 64b covering the interlayer insulating film 63. Is formed.
In this embodiment, the via plug 74 can be formed by filling the conductive material 73 only in the via hole 64a without performing a planarization process such as a CMP method.

Subsequently, as shown in FIG. 10C, a base film 75a and an upper wiring 75 are formed.
Specifically, first, Ti, TiN, or a laminated film thereof is deposited on the interlayer insulating film 63 by a sputtering method or the like to form a base film 75a that functions as a contact layer.
Next, ITO is deposited on the base film 75a by, for example, plasma sputtering. Then, the deposited ITO and the underlying film 75a are processed by lithography and milling so as to have an electrode shape on the via plug 74, thereby forming an upper wiring 75 electrically connected via the via plug 74 and the underlying film 75a. To do. As a result, the wiring structure 70 in which the via plug 74 and the upper wiring 75 are electrically connected via the base film 75a is formed.

  Thereafter, one or more additional upper layer wiring structures are formed so as to be electrically connected to the wiring structure 70, and a semiconductor device is formed through formation of a protective film and pad electrodes for external connection. Here, the upper wiring structure is preferably formed in the same manner as the wiring structure 70.

  As described above, according to the present embodiment, the via plug 74 having the CNT 64d can be further reduced in resistance, and the via plug 74 can be further miniaturized.

In the present embodiment, the contact plug connected to the source / drain region may be formed in the same manner as the via plug 74 as in the modification of the first embodiment.
Similarly to the second embodiment, a via plug connected to the lower wiring 71 may be formed similarly to the via plug 52.

(Fifth embodiment)
11 to 13 are schematic cross-sectional views illustrating main processes of the method for manufacturing a semiconductor device according to the fifth embodiment.
In this embodiment, first, the manufacturing process in any one of the 1st-4th embodiment is performed.
Then, as shown in FIG. 11A, a pad electrode 81 for external connection is formed so as to be exposed on the surface of the semiconductor substrate 10. In each drawing of FIG. 11, illustration of the structure formed on the semiconductor substrate 10 according to any one of the first to fourth embodiments is omitted, and the pad electrode 81 is illustrated on the semiconductor substrate 10.

  Specifically, gold (Au) or an Au alloy is deposited on the semiconductor substrate 10 by vacuum deposition, sputtering, or electroplating. Then, the deposited gold (Au) or Au alloy is processed by lithography and milling so as to have an electrode shape, thereby forming a pad electrode 81 electrically connected to each lower wiring structure.

Subsequently, as shown in FIG. 11B, a resist mask 82 having an opening 82a is formed.
More specifically, a resist is applied so as to cover the pad electrode 81, and the resist is patterned by lithography to form an opening 82a that exposes a part of the surface of the pad electrode 81. Thus, a resist mask 82 having an opening 82a is formed.

Subsequently, as shown in FIG. 11C, after forming the base film 82b, the fine particle catalyst 84 is deposited. In FIG. 11C, the illustration of the configuration below the pad electrode 81 is omitted.
Specifically, a base conductive material is deposited on the resist mask 82 including the bottom surface of the opening 82a by a sputtering method or the like to form a base film 83. As the base conductive material, one or more selected from Ti, Ta, TiN, and TaN (becomes a laminated film) are used. By using Ta or TaN as the base conductive material, a base film that satisfactorily protects the pad electrode 81 is obtained, and Au diffusion from the pad electrode 81 is prevented. By using Ti or TiN as the base conductive material, an electrically and mechanically good contact layer for the pad electrode 81 is obtained. In the present embodiment, a Ta film 83-1 and a TiN film 83-2 are stacked and deposited to form a base film 83.

Next, a fine particle catalyst 84 serving as a catalyst for growing CNTs is deposited on the resist mask 82 including the bottom surface of the opening 82a.
As the fine particle catalyst 84, as in the fine particle catalyst 28c of FIG.

Subsequently, as shown in FIG. 11D, after removing the resist mask 82, the CNTs 82 are grown. In addition, in FIG.11 (d), the one pad electrode 81 and its periphery are expanded and shown.
Specifically, first, the resist mask 82 is removed by a wet process using hydrofluoric acid (HF) or the like using a lift-off method. At this time, the base film 83 remains only on the pad electrode 81, and the particulate catalyst 84 is deposited only on the base film 83.
Next, the CNT 85 is grown from the fine particle catalyst 84. The growth conditions for the CNT 85 are the same as the growth conditions for the CNT 28d in FIG.

Subsequently, as shown in FIG. 12A, an insulating filling material 86 is deposited so as to cover the formed CNTs 85 and fill the gaps between the CNTs 85. As the filling material 86, an organic SOG is used in the same manner as the filling material 29 in FIG. 2C, and deposited under the same deposition conditions to form a CNT / SOG composite layer.
Subsequently, as shown in FIG. 12B, the CNT / SOG composite layer is polished and planarized by CMP until the upper end surface of the CNT 85 is exposed. For CMP, for example, an oxide film (alkali) slurry is used.

Subsequently, as shown in FIG. 12C, CNT bumps 88 are formed.
Specifically, first, the filling material 86 filling the gaps between the CNTs 85 above the semiconductor substrate 10 is removed by performing a wet treatment using, for example, dilute hydrofluoric acid (5%).
Next, the gap between the CNTs 85 and the hollow space of the CNTs 85 are filled with the conductive material 87. As the conductive material 87, the same material (Au or Au alloy) as the electrode pad 81 is used. In the present embodiment, the conductive material 87 is deposited using the supercritical CVD method under the same conditions as those for forming the via plug 33 in the first embodiment. The conductive material 87 grows so as to fill the gaps between the CNTs 85, which are fine spaces, and the hollows of the CNTs 85. When the filling is completed, the supercritical CVD is terminated. At this time, the CNT bumps 88 are formed in which the conductive material 87 is not yet deposited in the CNT 85 non-formation region above the semiconductor substrate 10 and the gap between the CNTs 85 and the hollow space of the CNT 85 are filled with the conductive material 87. The
In the present embodiment, the conductive material 67 is filled into the gaps between the CNTs 85 and the hollows of the CNTs 85 without performing a planarization process such as a CMP method, and the CNT bumps 88 can be formed.

Subsequently, as shown in FIG. 13, flip chip bonding is performed.
Specifically, as shown in FIG. 13A, a substrate 101 on which various functional elements, wirings, and the like are formed and a pad electrode 102 made of Au or an Au alloy connected to the wiring is formed is prepared.
Then, as shown in FIG. 13B, the semiconductor substrate 10 and the substrate 101 are brought into contact with each other so that the CNT bumps 88 and the pad electrode 102 are in contact with each other, and the semiconductor substrate 10 and the substrate 101 are bonded by flip chip bonding. Join.

  As described above, according to the present embodiment, it is possible to further reduce the resistance of the CNT bump 88 including the CNT 85 and further miniaturize the CNT bump 88.

It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device by 1st Embodiment in order of a process. FIG. 2 is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps, following FIG. 1. FIG. 3 is a schematic cross-sectional view subsequent to FIG. 2, illustrating the method for manufacturing the semiconductor device according to the first embodiment in the order of steps. It is a schematic sectional drawing which shows the mode in CNT formed by 1st Embodiment. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the semiconductor device in the modification of 1st Embodiment. FIG. 6 is a schematic cross-sectional view showing main steps of the method for manufacturing the semiconductor device according to the modification of the first embodiment, following FIG. 5. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the semiconductor device by 2nd Embodiment. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the semiconductor device by 3rd Embodiment. FIG. 9 is a schematic cross-sectional view showing main steps of the method for manufacturing the semiconductor device according to the third embodiment, following FIG. 8. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the semiconductor device by 4th Embodiment. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the semiconductor device by 5th Embodiment. FIG. 12 is a schematic cross-sectional view showing main steps of the method for manufacturing the semiconductor device according to the fifth embodiment following FIG. FIG. 13 is a schematic cross-sectional view showing main steps of the method for manufacturing the semiconductor device according to the fifth embodiment, following FIG. 12.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon semiconductor substrate 11 Element isolation structure 12 Well 13 Gate insulating film 14 Gate electrode 15 Cap film 16 Extension region 17 Side wall insulating film 18 Source / drain region 20 MOS transistors 22, 24, 27, 31, 63 Interlayer insulating film 23, 43 Contact plug 23a Contact hole 23b, 25b, 28b, 32b, 41a, 45a, 53a, 61a, 64b, 71a, 75a, 82b, 83 Base film 25, 45, 71 Lower wiring 25a, 32a Wiring groove 21, 26 Protective film 28a, 64a, 64c Via hole 28b-1, 41a-1, 64b-1, 83-1 Ta film 28b-2, 41a-2, 64b-2, 83-2 TaN film 28c, 41b, 64c, 84 Particulate catalyst 28d, 41c, 64d, 85 CNT
29, 66, 86 Filling material 30, 40, 50, 60, 70 Wiring structure 32, 53, 61, 69, 75 Upper wiring 33, 52, 68, 74 Via plug 34, 51, 44, 67, 73, 87 Conductive material 65, 82 Resist mask 65a, 82a Opening 81, 102 Pad electrode 88 CNT bump 101 Substrate

Claims (7)

Wiring and
A connecting portion electrically connected to the wiring,
The connecting portion is formed to include a linear structure made of a carbon element, and a conductive material that fills the space between the linear structures and fills the hollow space of the linear structure. A wiring structure characterized by that.   The wiring is formed by filling a wiring groove formed in an interlayer insulating film on the connection portion with another conductive material through a base film made of the conductive material. Wiring structure described in 1.   The wiring structure according to claim 1, wherein the conductive material is one type selected from Ti, Ta, Ru, TiN, and TaN.   The wiring structure according to claim 1, wherein the wiring is formed of the conductive material on the connection portion. A semiconductor device in which a functional element is formed on a semiconductor substrate,
Wiring formed above the semiconductor substrate;
Under the wiring, including a connection part electrically connected to the wiring,
The connecting portion is formed to include a linear structure made of a carbon element, and a conductive material that fills the space between the linear structures and fills the hollow space of the linear structure. A semiconductor device. A semiconductor device in which functional elements and wirings are formed on a semiconductor substrate,
An electrode connected to the wiring above the wiring;
A connection bump formed on the electrode,
The connection bump is formed to include a linear structure made of a carbon element and a conductive material that fills a space between the linear structures and fills the hollow space of the linear structure. A semiconductor device. Wiring and
A wiring structure forming method including a connection portion electrically connected to the wiring,
A wiring comprising: forming a linear structure made of a carbon element in the connection portion; and filling a gap between the linear structures with a conductive material and filling the hollow of the linear structure. Structure formation method.

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