JP2010134837A - Device, method and program for verification of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a verification device which extracts only an original defect from layout data of a semiconductor integrated circuit device including an intentionally introduced experiment unit. <P>SOLUTION: The verification device verifies the layout data of the semiconductor integrated circuit including the experiment unit intentionally introduced by a designer, and includes: a verification rule generation unit which generates one or more verification rules including a design standard to the semiconductor integrated circuit and the experiment unit; a layout data generation unit which generates the layout data obtained by excluding the experiment unit included in the verification rules from an object for verification for each of the verification rules; and a defect extraction unit which extracts the defect as a unit which does not satisfy the design standard in the layout data obtained by excluding the experiment unit from the object for verification for each of the verification rules. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit verification apparatus, method, and program, and more particularly, to an apparatus, method, and program for verifying layout data of a semiconductor integrated circuit.

  In the layout design of a semiconductor integrated circuit, it is necessary to verify whether or not layout data satisfies a design standard. Locations that do not satisfy the design criteria in the layout data may include defects introduced by mistakes of the designer (hereinafter referred to as “original defects”) and experimental locations introduced intentionally by the designer. .

  Patent Document 1 describes a method for inspecting a TEG pattern that does not require a complicated DRC (Design Rule Check) rule to inspect a TEG (Test Element Group) pattern and can easily perform an accurate inspection. ing.

  Further, Patent Document 2 describes a mask pattern verification apparatus that performs verification of mask patterns with partially different geometric design rules in a short time with high accuracy.

JP 2004-153132 A JP 05-027412 A

  The following analysis was made by the present inventors. When the layout data includes the original defect and the experimental part, when the inspection method described in Patent Document 1 and the inspection apparatus described in Patent Document 2 are used, both the original defect and the experimental part are used. May be extracted as a location that does not satisfy the design criteria. Therefore, there is a problem that it is not possible to extract only the original defects that are necessary when verifying the layout.

  Therefore, it is an object to provide a verification apparatus, method, and program for extracting only original defects from layout data of a semiconductor integrated circuit device including an experimentally introduced experimental portion.

  A verification apparatus according to a first aspect of the present invention is an apparatus for verifying layout data of a semiconductor integrated circuit including an experimental portion intentionally introduced by a designer, and includes a design standard for the semiconductor integrated circuit and the experiment. A verification rule generation unit that generates one or more verification rules including a location, and a layout data generation unit that generates, for each of the verification rules, layout data that excludes an experimental location included in the verification rule from a verification target; And a defect extraction unit that extracts, for each of the verification rules, a defect that is a location that does not satisfy the design criteria in the layout data excluding the experimental location from the verification target.

  A verification method according to a second aspect of the present invention is a method for verifying layout data of a semiconductor integrated circuit including an experimental portion that is intentionally introduced by a designer, and includes a design standard for the semiconductor integrated circuit and the experiment. A step of generating one or more verification rules including a location, a layout data generating step for generating layout data excluding the experimental location included in the verification rule from the verification target, and the experimental location A defect extraction step of extracting, for each of the verification rules, a defect that is a location that does not satisfy the design criteria in the layout data excluding the above from the verification target.

  A verification program according to a third aspect of the present invention is a program for verifying layout data of a semiconductor integrated circuit including an experimental portion intentionally introduced by a designer, and includes a design standard for the semiconductor integrated circuit and the experiment. A process for generating one or more verification rules including a part, a layout data generation process for generating, for each of the verification rules, layout data excluding an experimental part included in the verification rule from a verification target, and an experimental part The computer is caused to execute a defect extraction process for extracting, for each of the verification rules, defects that are locations that do not satisfy the design criteria in the layout data excluding from the verification target.

  According to the verification apparatus, method, and program according to the present invention, only original defects can be extracted from layout data of a semiconductor integrated circuit device including an experimental portion intentionally introduced by a designer.

(First embodiment)
A verification apparatus according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the verification apparatus according to this embodiment.

  The verification device 10 verifies the layout data of the semiconductor integrated circuit including the experimentally introduced experimental part. Referring to FIG. 1, the verification apparatus includes a verification rule generation unit 11, a layout data generation unit 12, and a defect extraction unit 13.

  The verification rule generation unit 11 generates one or two or more verification rules including design criteria and experimental locations for the semiconductor integrated circuit. The layout data generation unit 12 generates layout data for each verification rule by excluding the experimental part included in the verification rule from the verification target. The defect extraction unit 13 extracts, for each of the verification rules, defects that are locations that do not satisfy the design criteria in the layout data in which the experimental locations are excluded from the verification targets.

  Further, the layout data generation unit 12 may exclude a cell hierarchy having an experiment location included in the verification rule from the verification target. Furthermore, the layout data generation unit 12 may exclude a cell region having an experiment location included in the verification rule from the verification target. In addition, the layout data generation unit 12 may exclude the experimental part included in the verification rule from the verification target by overlapping the recognition layers.

  Further, the experimental part may be described by a regular expression, and the layout data generation unit 12 may develop the regular expression.

  Moreover, when the layout data which excluded the experiment location from the object of verification overlaps, the defect extraction part 13 extracts a defect in either of the overlapping layout data.

  Further, the verification apparatus 10 may include a defect display unit 14. The defect display unit 14 displays the defects extracted by the defect extraction unit 13. Further, the defect display unit 14 may integrate and display the defects extracted for each of the verification rules.

  Next, the operation of the verification apparatus 10 according to this embodiment will be described. FIG. 2 is a flowchart showing the operation of the verification apparatus 10 according to this embodiment.

  Referring to FIG. 2, the verification rule generation unit 11 generates one or more verification rules including design criteria and experimental locations for the semiconductor integrated circuit (step S11).

  The layout data generation unit 12 generates layout data for each of the verification rules by excluding the experimental part included in the verification rule from the verification target (step S12).

  The defect extraction unit 13 extracts defects that are locations that do not satisfy the design criteria in the layout data in which the experimental locations are excluded from the verification targets for each of the verification rules (step S13).

(Second Embodiment)
A verification program according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram illustrating a configuration of a computer that executes the verification program according to the present embodiment.

  The verification program according to the present embodiment is a program for verifying layout data of a semiconductor integrated circuit including an experimentally introduced experimental part. Referring to FIG. 3, the computer 20 includes a CPU 21, a storage unit 22, an input unit 23, and a defect display unit 24.

  As an example, the verification program recorded in the storage unit 22 is read by the CPU 21 to generate one or more verification rules including design criteria and experimental locations for the semiconductor integrated circuit, and an experiment included in the verification rules. Layout data generation processing that generates layout data that excludes parts from the verification target for each of the verification rules, and defects that do not satisfy the design criteria in the layout data that excludes experimental parts from the verification targets And a defect extraction process for extracting.

  The defect display unit 24 displays the defects extracted in the defect extraction process. Further, the defect display unit 24 may integrate and display the defects extracted for each of the verification rules.

  A first embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a flowchart showing the operation of the verification apparatus in the present embodiment.

  Referring to FIG. 4, the layout data 31 is data representing a layout on an actual device generated based on a predetermined circuit diagram, and includes a plurality of unit cells and wirings connecting the unit cells. Here, the layout data 31 includes an experimental part intentionally introduced by the designer.

  The experimental location includes at least one of a TEG composed of only cells or wirings to be excluded at the time of verification, or a recognition layer for defining a pattern to be excluded at the time of verification. At the time of verification, these TEGs or recognition layers can be excluded.

Various methods can be used as a method for defining the experimental location. 7 to 9 are diagrams for explaining a method of defining the experimental location. FIG. 7 and FIG. 8 show an example in which an experimental part is defined by a TEG composed of only cells and wirings to be excluded at the time of verification.
On the other hand, FIG. 9 shows an example in which an experiment location is defined by a recognition layer for defining a pattern to be excluded during verification. 8A and 9A show the original layout data. On the other hand, FIG. 8B and FIG. 9B show layout data in which the experimental part is excluded from the verification target.

  The verification rule description file 32 includes verification rules including a design standard for confirming the layout and an experiment location associated with the design standard. Here, the design standard refers to, for example, a standard for the width and interval of wiring. In addition, the experimental part refers to, for example, a TEG composed of only cells and wirings to be excluded at the time of verification, or a recognition layer that defines a pattern portion to be excluded at the time of verification.

  FIG. 5 is a diagram showing an example of the verification rule description file 32 in the present embodiment. In the verification rule in the second line of FIG. 5, “layer name, design standard name, width (um), experimental location” is “METAL, basic standard, 0.3, TEG_ [1-5]”. This verification rule indicates that “the width of the METAL layer is verified at 0.3 μm. However, TEG_ [1-5] is excluded from the verification target”. Here, TEG_ [1-5] merely indicates the name of the cell, and another name may be used as long as the name can identify the cell. In the verification rule description file 32, the layer number of the recognition layer may be used instead of the cell name.

  The verification rule description file 32 relating to the design standard of the entire semiconductor integrated circuit is referred to, and the verification rule 33 divided for each verification standard is generated (step S21). The verification rule description file 32 shown in FIG. 5 represents the overall design criteria, and an experimental location is provided for each layer design criteria. As an example, the verification rule description file 32 may be divided into lines to generate one or more verification rules 33.

  Next, for each of the above-described verification rules, layout data is generated by excluding the experimental part included in the verification rule from the verification target (step S22).

  FIG. 6 is a diagram illustrating layout data in which experimental locations are excluded from verification targets in the present embodiment. For example, in the basic standard of METAL, TEG_ [1-5] is excluded, so that layout data lacking a portion corresponding to TEG_ [1-5] is generated as shown in FIG. Similarly for I / I (ion implantation pattern), POLY (polysilicon wiring pattern), and VIA (through hole pattern), layout data excluding the experimental part from the verification target is generated.

  Next, verification (ie, DRC (Design Rule Check)) is performed on the layout data excluding the experimental part from the verification target, and defects are extracted (step S23). This defect extraction process is the same as the defect extraction process in the prior art. However, in this embodiment, since the experimental part (for example, the part defined by the recognition layer) is deleted in correspondence with the verification rule, only the original defect introduced by the designer is selectively selected. Can be detected.

  Next, the extracted defects are merged (integrated) and displayed (step S24). The integrated defect obtained for each verification rule 33 corresponds to the verification result for the entire layout data of the semiconductor integrated circuit.

  Next, the designer analyzes a defect (step S25). If there is a defect that does not satisfy the design criteria, the designer corrects the defect (step S26).

  On the other hand, if there is no defect, the layout data verification is completed (step S28).

  Furthermore, when design criteria or experiment locations are insufficient (for example, when an experiment location is forgotten to be specified for the verification rule description file 32), these are added to the verification rule description file 32 (step S27).

  10 to 12 are diagrams showing other examples of the verification rule description file 32 in the present embodiment. FIG. 10 describes the verification rules collectively for each layer to be verified. Referring to FIG. 10, the width and spacing for each layer is described in one line. Note that the description method may be one line or a plurality of lines. Since the width and interval of the wiring are almost constant because they are determined by the processing performance of the exposure machine, the verification rules are listed for each layer as shown in FIG. 10 to facilitate confirmation by the designer.

  On the other hand, FIG. 11 shows an example of a verification rule description file including a comprehensive margin / two-layer interval check. FIG. 12 shows an example of the verification rule description file 32 including an area check.

  According to the present embodiment, it is possible to distinguish an experimental place intentionally introduced from an original defect introduced due to a designer's error. At this time, only the original defect can be extracted as a portion to be corrected in the layout data. Therefore, the time and man-hour required for layout verification and layout correction can be greatly reduced.

  Also, according to the present embodiment, the verification rule description file 32 is represented by a set of design criteria and experimental locations, so that it can be easily generated and easily modified. Further, the verification rule description file 32 makes it easy to confirm the experimental location and design criteria, and it is also possible to easily confirm whether the designer's intention is reflected.

  A second embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a flowchart showing the operation of the verification apparatus in the present embodiment.

  The basic process is the same as the process in the first embodiment. However, if the layout data excluding the experimental portion includes overlapping data, defect extraction is performed on any of the overlapping layout data (step S33).

  FIG. 13 shows a case where the layout data excluding the experimental part included in the verification rule 1 from the verification target and the layout data excluding the experimental part included in the verification rule 2 from the verification target are the same. In this case, defect extraction is performed on any one of these layout data. As a result, the time required for verification can be shortened.

  Referring to FIGS. 5 and 6, the layout data generated for “METAL, basic standard” and “VIA, basic standard 2” is the same. Also, the layout data generated for “METAL, experimental standard”, “I / I, basic standard 2”, “POLY, experimental standard” and “VIA, experimental standard” are the same. Therefore, for these overlapping layout data, it is sufficient to extract defects for any one of the layout data. For “POLY, basic standard” and “POLY, basic standard 2”, layout data different from other layout data is generated.

  Although the above description has been made based on examples, the present invention is not limited to the above examples.

It is a block diagram which shows the structure of the verification apparatus which concerns on the 1st Embodiment of this invention. It is a flowchart which shows operation | movement of the verification apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the computer which performs the verification program which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows operation | movement of the verification apparatus in 1st Example of this invention. It is a figure which shows an example of the verification rule description file in 1st Example of this invention. It is a figure which shows an example of the layout data which excluded the experiment location from the object of verification in 1st Example of this invention. It is a figure for demonstrating the experimental location and the original defect in 1st Example of this invention. It is a figure which shows the example of the experiment location in the 1st Example of this invention. FIG. 5 is a diagram showing an example of an experimental part in the first example of the present invention. It is a figure which shows an example of the verification rule description file in 1st Example of this invention. It is a figure which shows an example of the verification rule description file in 1st Example of this invention. It is a figure which shows an example of the verification rule description file in 1st Example of this invention. It is a flowchart which shows operation | movement of the verification apparatus in 2nd Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Verification apparatus 11 Verification rule generation part 12 Layout data generation part 13 Defect extraction part 14, 24 Defect display part 20 Computer 21 CPU
22 Storage unit 23 Input unit 31, 41 Layout data 32, 42 Verification rule description file 33, 34 Verification rule

Claims (24)

An apparatus for verifying layout data of a semiconductor integrated circuit including an experimental part intentionally introduced by a designer,
A verification rule generation unit that generates one or more verification rules including a design standard for the semiconductor integrated circuit and the experiment location;
A layout data generation unit that generates layout data for each of the verification rules, excluding the experimental part included in the verification rule from the verification target;
A verification apparatus comprising: a defect extraction unit that extracts, for each of the verification rules, a defect that is a location that does not satisfy the design criteria in layout data in which an experimental location is excluded from verification targets.   The verification apparatus according to claim 1, wherein the layout data generation unit excludes a cell hierarchy having an experiment location included in the verification rule from a verification target.   The verification apparatus according to claim 1, wherein the layout data generation unit excludes a cell region having an experimental location included in the verification rule from a verification target.   The verification apparatus according to claim 1, wherein the layout data generation unit excludes an experiment location included in the verification rule from a verification target by overlapping recognition layers. The experimental part is described by a regular expression,
The verification apparatus according to claim 1, wherein the layout data generation unit expands the regular expression.   6. The defect extraction unit according to claim 1, wherein when the layout data excluding the experimental portion from the verification target overlaps, a defect is extracted from any of the overlapping layout data. The verification apparatus according to item 1.   The verification apparatus according to claim 1, further comprising a defect display unit that displays the defects extracted in the defect extraction unit.   The verification apparatus according to claim 7, wherein the defect display unit integrally displays defects extracted for each of the verification rules. A method for verifying layout data of a semiconductor integrated circuit including an experimental part intentionally introduced by a designer,
Generating one or more verification rules including design criteria for the semiconductor integrated circuit and the experiment location;
A layout data generation step for generating, for each of the verification rules, layout data excluding the experiment location included in the verification rule from the verification target;
A verification method including a defect extraction step of extracting, for each of the verification rules, a defect that is a location that does not satisfy the design criteria in layout data in which an experimental location is excluded from verification targets.   The verification method according to claim 9, wherein, in the layout data generation step, a cell hierarchy having an experiment location included in the verification rule is excluded from verification targets.   The verification method according to claim 9 or 10, wherein, in the layout data generation step, a cell region having an experimental location included in the verification rule is excluded from a verification target.   The verification method according to any one of claims 9 to 11, wherein in the layout data generation step, an experiment location included in the verification rule is excluded from verification targets by overlapping recognition layers. The experimental part is described by a regular expression,
The verification method according to claim 9, wherein the regular expression is expanded in the layout data generation step.   14. The defect extraction step according to claim 9, wherein, when the layout data excluding the experimental part from the verification target overlaps, a defect is extracted from any of the overlapping layout data. 2. The verification method according to item 1.   The verification method according to any one of claims 9 to 14, further comprising a defect display step of displaying the defects extracted in the defect extraction step.   The verification method according to claim 15, wherein in the defect display step, defects extracted for each of the verification rules are integrated and displayed. A program for verifying layout data of a semiconductor integrated circuit including an experimental part intentionally introduced by a designer,
Processing for generating one or more verification rules including design criteria for the semiconductor integrated circuit and the experiment location;
Layout data generation processing for generating, for each of the verification rules, layout data excluding the experimental part included in the verification rule from the target of verification;
A verification program that causes a computer to execute a defect extraction process for extracting a defect that is a location that does not satisfy the design criteria in layout data in which an experimental location is excluded from verification targets for each of the verification rules.   18. The verification program according to claim 17, wherein in the layout data generation process, the computer executes a process of excluding a cell hierarchy having an experiment location included in the verification rule from a verification target.   19. The verification program according to claim 17 or 18, characterized in that, in the layout data generation processing, the computer executes processing for excluding a cell region having an experimental location included in the verification rule from a verification target.   20. The layout data generation process causes a computer to execute a process of excluding an experiment location included in the verification rule from a verification target by overlapping recognition layers. The verification program described in. The experimental part is described by a regular expression,
21. The verification program according to claim 17, further comprising causing a computer to execute a process of expanding the regular expression in the layout data generation process.   In the defect extraction process, if layout data excluding an experimental part from a verification target overlaps, the computer is caused to execute a process of extracting defects in any of the overlapping layout data. The verification program according to any one of 17 to 21.   23. The verification program according to claim 17, further causing a computer to execute a defect display process for displaying defects extracted in the defect extraction process.   24. The verification program according to claim 23, wherein in the defect display processing, the computer executes processing for integrating and displaying the defects extracted for each of the verification rules.

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