JP2010130554A - Follower circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a follower circuit enabling a level shift, wherein the amount of level shift becomes an opposite sign to that of a source follower circuit. <P>SOLUTION: MOS transistors 1, 11 are PMOS transistors, and a MOS transistor 2 is an NMOS transistor. A source 1S of the MOS transistor 1 is connected to a positive power terminal 8, a gate 1G is connected to a first bias terminal 6 to which a first bias voltage is supplied, and a drain 1D is connected to an input terminal 4 and is also connected to a source 11S of the MOS transistor 11. A gate 11G and a drain 11D of the MOS transistor 11 are connected in common, and are also connected to a drain 2D and an output terminal 5 of the MOS transistor 2. A source 2S of the MOS transistor 2 is connected to a negative power terminal 9, and a gate 2G is connected to a second bias terminal 7 to which a second bias voltage is supplied. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a follower circuit, and more particularly to a follower circuit that enables a level shifter in which a level shift amount has an opposite sign to a source follower circuit.

  Generally, various circuits have been proposed as level shifter circuits used for the purpose of shifting the voltage level of a signal to another voltage level in an analog circuit. As one of typical circuits, one that converts a DC level of capacitive coupling, one that converts a signal level by passing a current through a resistor, and a gate-source of a MOS transistor such as a source follower shown in FIG. Some convert the voltage level by the voltage difference between them.

  In the case of converting a capacitively coupled DC level, a large capacity is required to pass a low-frequency signal. In addition, when a signal level is converted by passing a current through a resistor, the current is increased or the resistance value is increased when a large level shift is required. When a large resistance value is used, it becomes difficult to pass a high frequency signal due to the presence of the parasitic capacitance of the terminal. The source follower circuit has a feature that a signal level shift can be easily realized with a low current consumption ranging from a DC signal to a high-frequency signal.

  FIG. 7 is a circuit diagram for explaining a conventional source follower circuit. This source follower circuit supplies P-type MOS transistors 51 and 52, an input terminal 53, an output terminal 54, a bias terminal 55, a negative power supply terminal 56 for supplying a negative power supply, and a positive power supply. And a positive power supply terminal 57.

  The gate 52G of the PMOS transistor 52 is connected to the input terminal 53, and the drain 52D is connected to the negative power supply terminal 56. The source 52S of the PMOS transistor 52 is connected to the drain 51D of the PMOS transistor 51 and also to the output terminal 54. The gate 51G of the PMOS transistor 51 is connected to the bias terminal 55, to which a bias voltage is supplied, and the source 51S is connected to the positive power supply terminal 57.

Next, the operation of the source follower circuit (level shifter circuit) shown in FIG. 7 will be described. (See Patent Document 1) The PMOS transistor 51 operates as a constant current source, and the current value can be controlled by a bias voltage supplied to the gate terminal 55. A relational expression between the voltage Vin of the gate terminal 53 of the PMOS transistor 52, that is, the input terminal 53, and the voltage Vout of the source 52S, that is, the output terminal 54 is given by the following expression (1).
Ip = (Wp / 2Lp) μpCoxp (Vin−Vout−Vthp) ²
... (1)

Here, Ip is the current flowing between the source and drain of the PMOS transistor 52, Wp, Lp, μp, Coxp, and Vthp are the channel width, channel length, carrier mobility, and gate capacitance per unit area of the PMOS transistor 52, respectively. , The threshold voltage. The above-described expression (1) can be modified and rewritten as the following expression (2).
Vout = Vin−Vthp + √ {Ip / (Wp / 2Lp) μpCoxp}
... (2)

  Here, since the current Ip is constant, √ {Ip / (Wp / 2Lp) μpCoxp} is also a constant value, and the threshold voltage Vthp is also constant. Thus, it becomes a value obtained by adding a constant value to the input voltage Vin, and it is understood that the level shifts.

Except for special cases, enhancement type transistors are generally used for MOS transistors. According to this, in the case of PMOS, the threshold voltage Vthp has a negative value. That is, the level shift is always in the positive direction from the above-described equation (2). When it is desired to shift the level in the negative direction, the circuit can be configured in the same manner by using an NMOS transistor. The expression of the output voltage in this case can be given by the following expression (3).
Vout = Vin−Vthn−√ {In / (Wn / 2Ln) μnCoxn}
... (3)

  Here, In is the current flowing between the source and drain of the NMOS transistor, Wn, Ln, μn, Coxn, and Vthn are the channel width, channel length, carrier mobility, gate capacitance per unit area, and threshold value, respectively. Voltage. In the case of an enhancement type MOS transistor, Vthn has a positive sign, so that the level shift is always in the negative direction according to the above-described equation (3).

  Once again, regarding the source follower circuit, the source follower is characterized in that the level of the signal can be shifted with low current consumption from a DC (direct current) signal to a high frequency signal. In the source follower circuit, the NMOS transistor can be used to lower the signal to the negative power supply side, or the PMOS transistor can be used to raise the signal to the positive power supply side. In addition, the magnitude of the level shift corresponds to the threshold value of the MOS transistor, and is suitable when it is desired to shift the level by the threshold voltage.

  1 and 5 of Patent Document 1 also show an example of the source follower circuit shown in FIG.

Japanese Patent Application Laid-Open No. 2004-296741 Behzad Razavi / Translated by Tadahiro Kuroda, Analog CMOS integrated circuit design basics, Maruzen Co., Ltd., July 2000, page 82

  However, in the prior art, the signal cannot be raised to the positive power supply side using the (enhancement type) NMOS transistor, or the signal cannot be lowered to the negative power supply side using the PMOS transistor. In particular, there has been no circuit that increases the signal level by the threshold voltage of the NMOS transistor or decreases the signal level by the threshold voltage of the PMOS transistor.

  The present invention has been made in view of such problems, and the object of the present invention is to use a NMOS transistor with a low current consumption from a DC (direct current) signal to a high-frequency signal in the same manner as a source follower circuit. It is an object of the present invention to provide a follower circuit capable of raising the signal to the positive power supply voltage side or lowering the signal to the negative power supply voltage side using a PMOS transistor.

  The present invention has been made to achieve such an object. The invention according to claim 1 has a source (11S) for inputting an input signal (Vin) from an input terminal (4), and a gate. A first MOS transistor (11) that outputs an output signal (Vout) from an output terminal (5) in which a drain (11G) and a drain (11D) are connected in common; and the source of the first MOS transistor (11) ( 11S), and a first current source (1) connected to the drain (11D) of the first MOS transistor (11), and a second current source (2) connected to the drain (11D) of the first MOS transistor (11). Features. (Fig. 1, Example 1)

  According to a second aspect of the present invention, in the first aspect of the present invention, the first MOS transistor is provided between the first MOS transistor (11) and the second current source (2). The drain (11D) and source (12S) of (11) are connected in common, and the output signal (Vout) is output from the output terminal (5) in which the gate (12G) and drain (12D) are connected in common. The MOS transistor (12) is provided. (Fig. 2, Example 2)

  According to a third aspect of the present invention, in the first aspect of the present invention, between the first current source (1) and the second current source (2), the (n-1) -th The drain terminal (1n-1D) and the nth source (1nS) of the MOS transistor (1n-1) are commonly connected, and the nth gate (1nG) and the drain (1nD) are commonly connected. 5), an n-th MOS transistor (1n) that outputs an output signal (Vout) is provided. (FIG. 4, Example 4)

  According to the present invention, from a DC (direct current) signal to a high frequency signal, the signal can be lowered to the negative power supply voltage side using the PMOS transistor, or the signal can be raised to the positive power supply voltage using the NMOS transistor. A follower circuit can be provided. Further, current consumption can be sufficiently reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

<Example 1>
FIG. 1 is a circuit diagram for explaining a first embodiment of the follower circuit according to the present invention, and is a circuit diagram of the first embodiment of the drain follower. The reason why it is called a drain follower is that the voltage appearing at the drain terminal 11D is used as an output signal as shown in FIG. The drain follower circuit according to the first embodiment includes MOS transistors 1, 2, 11, an input terminal 4, an output terminal 5, bias terminals 6, 7, and positive and negative power supply terminals 8, 9. Yes.

  MOS transistors 1 and 11 are PMOS transistors, and MOS transistor 2 is an NMOS transistor. The source 1S of the MOS transistor 1 is connected to the positive power supply terminal 8, the gate 1G is connected to the first bias terminal 6 to which the first bias voltage is supplied, and the drain 1D is connected to the input terminal 4. And connected to the source 11S of the MOS transistor 11.

  The gate 11G and the drain 11D of the MOS transistor 11 are commonly connected, and are connected to the drain 2D and the output terminal 5 of the MOS transistor 2. The source 2S of the MOS transistor 2 is connected to a negative power supply terminal 9, and the gate 2G is connected to a second bias terminal 7 to which a second bias voltage is supplied.

  That is, the follower circuit according to the first embodiment of the present invention includes the source 11S that inputs the input signal Vin from the input terminal 4, and outputs the output signal Vout from the output terminal 5 that commonly connects the gate 11G and the drain 11D. A first MOS transistor 11; a first current source 1 connected to the source 11S of the first MOS transistor 11; a second current source 2 connected to the drain 11D of the first MOS transistor 11; It is composed of

Next, the operation of the drain follower shown in FIG. 1 will be described.
MOS transistors 1 and 2 operate as current source circuits, and their current values depend on the bias voltage supplied to their respective gates. Usually, these two current values are set to have the same value Ip. Keep it. A signal voltage Vin is supplied to the input terminal 4, and an output voltage Vout is generated at the output terminal 5. The relational expression between the input voltage Vin and the output voltage Vout in this case can be expressed as the following expression (4) when the current supplied from the input terminal is sufficiently smaller than the current value Ip of the current source. .
Ip = (Wp / 2Lp) μpCoxp (Vout−Vin−Vthp) ²
... (4)

Here, Ip is the current flowing between the source and drain of the PMOS transistor 11, Wp, Lp, μp, Coxp, and Vthp are the channel width, channel length, carrier mobility, and gate capacitance per unit area of the PMOS transistor 11, respectively. , The threshold voltage. The above equation (4) can be modified and rewritten as the following equation (5).
Vout = Vin + Vthp−√ {Ip / (Wp / 2Lp) μpCoxp}
... (5)

  Here, since the current Ip is constant, the overdrive voltage √ {Ip / (Wp / 2Lp) μpCoxp} of the PMOS transistor is also a constant value, and the threshold voltage Vthp is also constant. Thus, it can be seen that the output voltage Vout becomes a value obtained by adding a constant value to the input voltage Vin and is level-shifted.

  Except for special cases, enhancement type transistors are generally used for MOS transistors. According to this, in the case of PMOS, the threshold voltage Vthp has a negative value. That is, the level shift voltage amount is always in the negative direction from the above-described equation (5). In other words, by using the drain follower circuit shown in FIG. 1, the enhancement type PMOS transistor can be level shifted in the negative direction. Since this level shift amount depends on the threshold value Vthp of the PMOS transistor, it is possible to shift the level in the negative direction by a value obtained by adding the overdrive voltage to the threshold value Vthp of the PMOS transistor.

<Example 2>
FIG. 2 is a circuit diagram for explaining a second embodiment of the follower circuit according to the present invention, and is a circuit diagram of the second embodiment of the drain follower. The difference between the drain follower shown in FIG. 2 and the drain follower shown in FIG. 1 is that only one PMOS transistor 11 is provided between the input terminal 4 and the output terminal 5 in FIG. In FIG. 2, the rest is the same except that there are two PMOS transistors 11 and 12.

  That is, the follower circuit according to the second embodiment of the present invention includes a source 11S that inputs an input signal Vin from an input terminal 4, a first MOS transistor 11 that commonly connects a gate 11G and a drain 11D, a source 12S, The second MOS transistor 12 that outputs the output signal Vout from the output terminal 5 that is commonly connected to the drain 11D of the first MOS transistor 11 and is commonly connected to the gate 12G and the drain 12D, and the first MOS transistor 11 The first current source 1 is connected to the source 11S, and the second current source 2 is connected to the drain 12D of the second MOS transistor 12.

As the number of PMOS transistors increases from one to two, the amount of level shift increases. The amount of this level shift can be obtained by calculating in the same manner as in the first embodiment. When the sizes of the two PMOS transistors are the same, the relationship between the output voltage Vout and the input voltage Vin is shown in the following equation (6).
Vout = Vin + 2Vthp-2√ {Ip / (Wp / 2Lp) μpCoxp}
... (6)

  In this case, the level shift amount is doubled compared to the drain follower shown in FIG. Similarly, when the number of PMOS transistors inserted between the input terminal and the output terminal is increased, the level shift amount also increases in accordance with the number of transistors.

<Example 3>
FIG. 3 is a circuit diagram for explaining a third embodiment of the follower circuit according to the present invention, and is a circuit diagram of the third embodiment of the drain follower. The difference between the drain follower shown in FIG. 3 and the drain follower shown in FIG. 1 is that, in FIG. 1, only one PMOS transistor 11 is provided between the input terminal 4 and the output terminal 5. In FIG. 3, the rest is the same except that there are three PMOS transistors 11, 12, and 13.

  That is, the follower circuit according to the third embodiment of the present invention includes the source 11S that receives the input signal Vin from the input terminal 4, the first MOS transistor 11 that commonly connects the gate 11G and the drain 11D, and the source 12S. And the drain 11D of the first MOS transistor 11 are commonly connected, the second MOS transistor 12 is commonly connected to the gate 12G and the drain 12D, and the source 13S is commonly connected to the drain 12D of the second MOS transistor 12. The third MOS transistor 13 that outputs the output signal Vout from the output terminal 5 that commonly connects the gate 13G and the drain 13D, and the first current source 1 that is connected to the source 11S of the first MOS transistor 11 The second current source 2 connected to the drain 13D of the third MOS transistor 13 It is configured.

As the number of PMOS transistors increases from one to three, the amount of level shift increases. The amount of this level shift can be obtained by calculating in the same manner as in the first embodiment. When the sizes of the three PMOS transistors are the same, the relationship between the output voltage Vout and the input voltage Vin is shown in the following equation (7).
Vout = Vin + 3Vthp-3√ {Ip / (Wp / 2Lp) μpCoxp}
... (7)

  In this case, the level shift amount is three times that of the drain follower shown in FIG. Similarly, when the number of PMOS transistors inserted between the input terminal and the output terminal is increased, the level shift amount also increases in accordance with the number of transistors.

<Example 4>
FIG. 4 is a circuit diagram for explaining a fourth embodiment of the follower circuit according to the present invention, and is a circuit diagram of the fourth embodiment of the drain follower. The difference between the drain follower shown in FIG. 4 and the drain follower shown in FIG. 1 is that only one PMOS transistor 11 is provided between the input terminal 4 and the output terminal 5 in FIG. In FIG. 4, the rest is the same except that there are n PMOS transistors 11, 12, 13... 1n.

  That is, the follower circuit according to the fifth embodiment of the present invention includes a first current source 1, a second current source 2, n source terminals 1nS, a gate terminal 1nG, and a common terminal obtained by commonly connecting a drain 1nD. Each of the n transistors includes a source group 1nS and a common terminal connected to each other, and a group of MOS transistors connected in cascade between the first current source 1 and the second current source 2; Current source 1 and an input terminal 4 for inputting an input signal Vin to a terminal to which the source 11S of the first MOS transistor 11 of the n MOS transistors connected to the first current source 1 is connected. The output signal V is connected to a terminal to which the second current source 2 and the common terminal of the nth MOS transistor 1n among the n MOS transistors connected to the second current source 2 are connected. And an output terminal 5 which for outputting ut.

As the number of PMOS transistors increases from 1 to n, the amount of level shift increases dramatically. The amount of this level shift can be obtained by calculating in the same manner as in the first embodiment. When n PMOS transistors have the same size, the following equation (8) shows the relationship between the output voltage Vout and the input voltage Vin.
Vout = Vin + nVthp-n√ {Ip / (Wp / 2Lp) μpCoxp}
... (8)

  In this case, the level shift amount is n times that of the drain follower shown in FIG. As described above, when the number of PMOS transistors inserted between the input terminal and the output terminal is increased, the level shift amount also increases in accordance with the number of transistors.

<Example 5>
FIG. 5 is a circuit diagram for explaining a fifth embodiment of the follower circuit according to the present invention, and is a circuit diagram of the fifth embodiment of the drain follower. The difference between the drain follower shown in FIG. 5 and the drain follower shown in FIG. 1 is that the PMOS transistor 11 in FIG. 1 is replaced with the NMOS transistor 21 and the positions of the input terminal 4 and the output terminal 5 are switched. Other than that, it is the same.

  That is, the follower circuit according to the fifth embodiment of the present invention includes a source 21S that receives an input signal Vin from an input terminal 4, and a MOS that outputs an output signal Vout from an output terminal 5 that commonly connects a gate 21G and a drain 21D. The transistor 21 is composed of a first current source 1 connected to the drain 21D of the MOS transistor 21 and a second current source 2 connected to the source 21S of the MOS transistor 21.

  In the following description, the drain follower of the fifth embodiment has a lot in common with the drain follower described in the first embodiment.

The MOS transistors 1 and 2 operate as current source circuits, and their current values depend on the bias voltages supplied to the respective gate terminals 6 and 7, but normally these two current values have the same value In. Set to. A signal voltage Vin is supplied to the input terminal 4, and an output voltage Vout is generated at the output terminal 5. The relational expression between the input voltage Vin and the output voltage Vout in this case can be expressed as the following expression (9) when the current supplied from the input terminal is sufficiently smaller than the current value In of the current source. .
In = (Wn / 2Ln) μnCoxn (Vout−Vin−Vthn) ²
... (9)

Here, In is the current flowing between the source and drain of the NMOS transistor 21, Wn, Ln, μn, Coxn, and Vthn are the channel width, channel length, carrier mobility, and gate capacitance per unit area of the NMOS transistor 21, respectively. , The threshold voltage. The above equation (9) can be modified and rewritten as the following equation (10).
Vout = Vin + Vthn + √ {In / (Wn / 2Ln) μnCoxn}
... (10)

  Here, since the current In is constant, the overdrive voltage √ {In / (Wn / 2Ln) μnCoxn} of the NMOS transistor is also a constant value, and the threshold voltage Vthn is also constant. Thus, it can be seen that the output voltage Vout becomes a value obtained by adding a constant value to the input voltage Vin and is level-shifted.

  Except for special cases, enhancement type transistors are generally used for MOS transistors. According to this, in the case of NMOS, the threshold voltage Vthn has a positive value. That is, the level shift voltage amount is always in the positive direction from the above-described equation (10). That is, by using the drain follower circuit shown in FIG. 5, the enhancement type NMOS transistor can be level shifted in the positive direction. Since this level shift amount depends on the threshold value Vthn of the NMOS transistor, it is possible to shift the level in the positive direction by a value obtained by adding the overdrive voltage to the threshold value Vthn of the NMOS transistor.

<Example 6>
FIG. 6 is a circuit diagram for explaining a sixth embodiment of the follower circuit according to the present invention, and is a circuit diagram of the sixth embodiment of the drain follower. The difference between the drain follower shown in FIG. 6 and the drain follower shown in FIG. 5 is that only one NMOS transistor 21 is provided between the input terminal 4 and the output terminal 5 in FIG. 6 is the same except that there are n NMOS transistors 21... 2n.

  That is, the follower circuit according to the sixth embodiment of the present invention includes a drain 2n-1D and a source of the n-1th MOS transistor 2n-1 between the first current source 1 and the second current source 2. 2nS is commonly connected, and an nth MOS transistor 2n that outputs an output signal Vout from an output terminal 5 that is commonly connected to an nth gate 2nG and a drain 2nD is provided. Also in this case, the level shift amount is n times that of the drain follower shown in FIG. As described above, when the number of NMOS transistors inserted between the input terminal and the output terminal is increased, the level shift amount also increases in accordance with the number of transistors.

  The drain follower of the present invention uses an NMOS transistor to raise a signal to a positive power supply voltage side from a DC (direct current) signal to a high frequency signal, or to lower a signal to a negative power supply voltage side using a PMOS transistor. It is possible to provide a level shifter capable of By providing this circuit, the variation of the level shift circuit becomes richer. For example, the possibility of using an inexpensive process increases because the use of an NMOS or PMOS process that can be provided at a lower cost rather than a CMOS process is expanded.

1 is a circuit diagram for explaining a first embodiment of a follower circuit according to the present invention; FIG. It is a circuit diagram for demonstrating Example 2 of the follower circuit based on this invention. It is a circuit diagram for demonstrating Example 3 of the follower circuit based on this invention. It is a circuit diagram for demonstrating Example 4 of the follower circuit based on this invention. FIG. 6 is a circuit diagram for explaining a fifth embodiment of the follower circuit according to the present invention. It is a circuit diagram for demonstrating Example 6 of the follower circuit based on this invention. It is a circuit diagram for demonstrating the conventional source follower circuit.

Explanation of symbols

1, 2, 11, 12, 13, 21 MOS transistor 4, 53 Input terminal 5, 54 Output terminal 6, 7, 55 Bias terminal 9, 56 Negative power supply terminal 8, 57 Positive power supply terminal

Claims (3)

A first MOS transistor having a source for inputting an input signal from an input terminal and outputting an output signal from an output terminal having a gate and a drain connected in common;
A first current source connected to the source of the first MOS transistor;
And a second current source connected to the drain of the first MOS transistor.   The drain and source of the first MOS transistor are connected in common between the first MOS transistor and the second current source, and an output signal is output from an output terminal in which the gate and drain are connected in common. The follower circuit according to claim 1, further comprising a second MOS transistor.   Between the first current source and the second current source, the drain and the nth source of the (n-1) th MOS transistor are connected in common, and the nth gate and the drain are shared. 2. The follower circuit according to claim 1, further comprising an nth MOS transistor that outputs an output signal from a connected output terminal.

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