JP2010129696A - Method of manufacturing wiring circuit board - Google Patents

Method of manufacturing wiring circuit board Download PDF

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JP2010129696A
JP2010129696A JP2008301527A JP2008301527A JP2010129696A JP 2010129696 A JP2010129696 A JP 2010129696A JP 2008301527 A JP2008301527 A JP 2008301527A JP 2008301527 A JP2008301527 A JP 2008301527A JP 2010129696 A JP2010129696 A JP 2010129696A
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wiring pattern
defect
circuit board
surface treatment
printed circuit
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JP5127681B2 (en
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Teruichi Ihara
輝一 井原
Kei Nakamura
圭 中村
Norihiko Okamoto
憲彦 岡本
Atsushi Yoshida
敦志 吉田
Kosuke Murakami
巧丞 村上
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Nitto Denko Corp
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Nitto Denko Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring circuit board capable of accurately determining the existence of the defects of wiring patterns. <P>SOLUTION: A predetermined wiring pattern is formed (step S1). Subsequently, the automatic optical inspection of the wiring patterns is performed by an appearance inspection device (step S2). Successively, an electroless tin plating layer is formed, in such a manner as to cover the wiring pattern to perform the surface treatment of the wiring pattern (step S3). Then, the part of the defect of the wiring pattern detected by an AOI is imaged by an imaging device, such as CCD, and an operator verifies the result of the AOI on the basis of the image (step S4). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、配線回路基板の製造方法に関する。   The present invention relates to a method for manufacturing a printed circuit board.

従来、配線回路基板の製造時には、配線パターンが形成された後、半製品の段階で配線パターンの欠陥を検出するための自動光学検査(AOI; automatic optical inspection)が行われる。AOI後には、オペレータによる検査結果の確認(ベリファイ)が行われる(例えば特許文献1参照)。具体的には、AOIにおいて欠陥が検出された配線パターンの部分がCCD(電荷結合素子)等によって撮像される。その画像に基づいて、欠陥が検出された部分に実際に欠陥があるか否かをオペレータが目視によって判定する。実際に欠陥があればその半製品は不良品と認識され、廃棄または修理等の対象となる。欠陥がなければその半製品は良品と認識され、引き続き処理が行われる。
特開2001−356099号公報
Conventionally, when a printed circuit board is manufactured, an automatic optical inspection (AOI) for detecting a defect in the wiring pattern is performed at a semi-finished product stage after the wiring pattern is formed. After the AOI, the operator confirms (verifies) the inspection result (see, for example, Patent Document 1). Specifically, the part of the wiring pattern in which a defect is detected in the AOI is imaged by a CCD (charge coupled device) or the like. Based on the image, the operator visually determines whether or not the portion where the defect is detected actually has a defect. If there is actually a defect, the semi-finished product is recognized as a defective product and is subject to disposal or repair. If there are no defects, the semi-finished product is recognized as a non-defective product, and processing continues.
JP 2001-356099 A

配線パターンの材料として例えば銅を用いた場合、配線パターンの表面の一部が酸化して変色することがある。通常、このような変色は配線パターンの特性に影響を与えることはなく、欠陥とはならない。   When, for example, copper is used as the wiring pattern material, a part of the surface of the wiring pattern may be oxidized and discolored. Usually, such discoloration does not affect the characteristics of the wiring pattern and does not cause a defect.

AOIにおいては、配線パターンの酸化による変色が欠陥として検出される。この場合、AOI後のベリファイにおいても、オペレータが誤って酸化による変色を欠陥であると判定することがある。これは、ベリファイのための画像上では、酸化による変色と、凹み、欠けまたは断線等の実際の欠陥との判別が困難なためである。その結果、不良品と認識される半製品が過剰に発生し、生産性が低下する。   In AOI, discoloration due to oxidation of the wiring pattern is detected as a defect. In this case, even in the verification after AOI, the operator may erroneously determine that the discoloration due to oxidation is a defect. This is because it is difficult to distinguish discoloration due to oxidation from actual defects such as dents, chips, or disconnections on an image for verification. As a result, an excessive number of semi-finished products that are recognized as defective products are generated, and productivity is reduced.

本発明の目的は、配線パターンの欠陥の有無を正確に認識することが可能な配線回路基板の製造方法を提供することである。   The objective of this invention is providing the manufacturing method of the printed circuit board which can recognize correctly the presence or absence of the defect of a wiring pattern.

(1)本発明に係る配線回路基板の製造方法は、基板上に配線パターンを形成する工程と、検査装置によって配線パターンの外観検査を行うことにより配線パターンにおいて欠陥の可能性がある部分を検出する工程と、外観検査後に配線パターン上に表面処理層を形成する工程と、表面処理層の形成後に、外観検査により検出された配線パターンの部分を撮像する工程と、撮像する工程で得られた画像上において、外観検査により検出された配線パターンの部分に実際に欠陥があるか否かを目視により確認する工程とを備えるものである。   (1) In the method for manufacturing a printed circuit board according to the present invention, a step of forming a wiring pattern on the substrate and a visual inspection of the wiring pattern by an inspection apparatus are performed to detect a possible defect in the wiring pattern. Obtained by the step of forming, the step of forming the surface treatment layer on the wiring pattern after the appearance inspection, the step of imaging the portion of the wiring pattern detected by the appearance inspection after the formation of the surface treatment layer, and the step of imaging A step of visually checking whether or not the wiring pattern portion detected by the appearance inspection actually has a defect on the image.

この配線回路基板の製造方法においては、基板上に配線パターンが形成された後、外観検査により配線パターンの外観検査が行われる。これにより、配線パターンにおいて欠陥の可能性がある部分が検出される。外観検査による外観検査の後、配線パターン上に表面処理層が形成される。その後、外観検査により検出された配線パターンの部分が撮像され、その画像上において、外観検査により検出された配線パターンの部分に実際に欠陥があるか否かが目視により確認される。   In this method of manufacturing a printed circuit board, after a wiring pattern is formed on the substrate, an appearance inspection of the wiring pattern is performed by an appearance inspection. Thereby, the part with the possibility of a defect in a wiring pattern is detected. After the appearance inspection by the appearance inspection, a surface treatment layer is formed on the wiring pattern. Thereafter, the portion of the wiring pattern detected by the appearance inspection is imaged, and it is visually confirmed on the image whether or not the portion of the wiring pattern detected by the appearance inspection is actually defective.

この場合、検査装置による外観検査時には、配線パターンが露出する状態である。これにより、精細な検査を行うことができ、欠陥の検出漏れを防止することができる。   In this case, the wiring pattern is exposed during the appearance inspection by the inspection apparatus. Thereby, a fine inspection can be performed and a defect detection failure can be prevented.

また、目視による確認は、配線パターンが表面処理層によって覆われた状態の画像に基づいて行われる。そのため、配線パターンが酸化によって変色していても、目視による確認時に、その部分が欠陥として認識されることはない。   The visual confirmation is performed based on an image in a state where the wiring pattern is covered with the surface treatment layer. Therefore, even if the wiring pattern is discolored due to oxidation, the portion is not recognized as a defect when visually confirmed.

したがって、検査装置による外観検査時に、酸化によって変色した配線パターンの部分が、欠陥の可能性がある部分として検出されても、目視による確認時に、その部分に欠陥がないことが認識される。その結果、実際には欠陥がない状態の半製品が不良品として処理されることが防止され、配線回路基板の生産性が向上される。   Therefore, even if the portion of the wiring pattern discolored due to oxidation is detected as a portion having a possibility of defect during the appearance inspection by the inspection apparatus, it is recognized that the portion is free of defects when visually confirmed. As a result, a semi-finished product that is actually free of defects is prevented from being processed as a defective product, and the productivity of the printed circuit board is improved.

(2)表面処理層の材料は、配線パターンの材料よりも高い耐酸化性を有してもよい。   (2) The material of the surface treatment layer may have higher oxidation resistance than the material of the wiring pattern.

この場合、目視による確認の前に、表面処理層が酸化して変色することが防止される。それにより、酸化して変色した表面処理層の部分が欠陥と誤認識されることが防止される。   In this case, the surface treatment layer is prevented from being oxidized and discolored before visual confirmation. This prevents the portion of the surface treatment layer that has been oxidized and discolored from being erroneously recognized as a defect.

また、高い耐酸化性を有する表面処理層によって配線パターンが覆われることにより、配線パターンの酸化が防止されるので、配線パターンの特性の低下が防止される。   Further, since the wiring pattern is covered with the surface treatment layer having high oxidation resistance, the wiring pattern is prevented from being oxidized, and thus the deterioration of the characteristics of the wiring pattern is prevented.

(3)配線パターンは銅を含み、表面処理層は錫およびニッケルのうち少なくとも1つを含んでもよい。   (3) The wiring pattern may include copper, and the surface treatment layer may include at least one of tin and nickel.

この場合、表面処理層および配線パターンの酸化が防止される。また、配線パターンと他の電子部品との電気的接続性を向上させることができる。   In this case, oxidation of the surface treatment layer and the wiring pattern is prevented. In addition, electrical connectivity between the wiring pattern and other electronic components can be improved.

(4)配線回路基板の製造方法は、基板として第1の絶縁層を準備する工程と、目視により確認する工程後に、配線パターンを覆うように第2の絶縁層を形成する工程とをさらに備えてもよい。   (4) The method for manufacturing a printed circuit board further includes a step of preparing a first insulating layer as a substrate and a step of forming a second insulating layer so as to cover the wiring pattern after the step of visual confirmation. May be.

この場合、第2の絶縁層によって配線パターンが外部環境から保護される。それにより、配線パターンの特性の低下が防止される。   In this case, the wiring pattern is protected from the external environment by the second insulating layer. Thereby, deterioration of the characteristics of the wiring pattern is prevented.

本発明によれば、検査装置による外観検査時に、酸化によって変色した配線パターンの部分が、欠陥の可能性がある部分として検出されても、目視による確認時に、その部分に欠陥がないことが認識される。その結果、実際には欠陥がない状態の半製品が不良品として処理されることが防止され、配線回路基板の生産性が向上される。   According to the present invention, even when a portion of the wiring pattern discolored due to oxidation is detected as a portion having a possibility of defect at the time of appearance inspection by the inspection apparatus, it is recognized that the portion is not defective at the time of visual confirmation. Is done. As a result, a semi-finished product that is actually free of defects is prevented from being processed as a defective product, and the productivity of the printed circuit board is improved.

以下、本発明の一実施の形態に係る配線回路基板の製造方法について図面を参照しながら説明する。   Hereinafter, a method for manufacturing a printed circuit board according to an embodiment of the present invention will be described with reference to the drawings.

図1は、本実施の形態に係る配線回路基板の製造方法の概要を示すフローチャートである。図2は、本実施の形態に係る配線回路基板の製造工程の一例を示す断面図である。   FIG. 1 is a flowchart showing an outline of a method for manufacturing a printed circuit board according to the present embodiment. FIG. 2 is a cross-sectional view showing an example of a manufacturing process of the printed circuit board according to the present embodiment.

まず、所定の配線パターンを形成する(図1のステップS1)。   First, a predetermined wiring pattern is formed (step S1 in FIG. 1).

具体的には、図2(a)に示すように、例えばステンレスからなる金属基板10を用意する。金属基板10の厚みは例えば5μm以上50μm以下であり、10μm以上30μm以下であることが好ましい。金属基板10の材料としては、ステンレスに代えてアルミニウム等の他の金属または合金等を用いてもよい。   Specifically, as shown in FIG. 2A, a metal substrate 10 made of, for example, stainless steel is prepared. The thickness of the metal substrate 10 is, for example, 5 μm or more and 50 μm or less, and preferably 10 μm or more and 30 μm or less. As a material of the metal substrate 10, other metal such as aluminum or an alloy may be used instead of stainless steel.

次に、図2(b)に示すように、金属基板10上に例えばポリイミドからなるベース絶縁層12を形成する。ベース絶縁層12は、第1の絶縁層の一例である。ベース絶縁層12の厚みは例えば1μm以上15μm以下であり、2μm以上5μm以下であることが好ましい。ベース絶縁層12の材料としては、ポリイミドに代えてエポキシ等の他の絶縁材料を用いてもよい。   Next, as shown in FIG. 2B, a base insulating layer 12 made of, for example, polyimide is formed on the metal substrate 10. The base insulating layer 12 is an example of a first insulating layer. The thickness of the base insulating layer 12 is, for example, not less than 1 μm and not more than 15 μm, and preferably not less than 2 μm and not more than 5 μm. As the material of the base insulating layer 12, other insulating materials such as epoxy may be used instead of polyimide.

次に、図2(c)に示すように、ベース絶縁層12上に例えば銅からなる所定の配線パターン13を形成する。配線パターン13の厚みは例えば3μm以上16μm以下であり、6μm以上13μm以下であることが好ましい。配線パターン13は、例えばセミアディティブ法を用いて形成してもよく、サブトラクティブ法等の他の方法を用いて形成してもよい。また、配線パターン13の材料としては、銅に限らず、金(Au)、アルミニウム等の他の金属、または銅合金、アルミニウム合金等の合金を用いてもよい。   Next, as shown in FIG. 2C, a predetermined wiring pattern 13 made of, for example, copper is formed on the base insulating layer 12. The thickness of the wiring pattern 13 is, for example, 3 μm or more and 16 μm or less, and preferably 6 μm or more and 13 μm or less. The wiring pattern 13 may be formed using, for example, a semi-additive method, or may be formed using another method such as a subtractive method. The material of the wiring pattern 13 is not limited to copper, and other metals such as gold (Au) and aluminum, or alloys such as copper alloy and aluminum alloy may be used.

このようにして所定の配線パターン13を形成した後、図示しない外観検査装置により、配線パターン13の自動光学検査(AOI; automatic optical inspection)を行う(図1のステップS2)。   After the predetermined wiring pattern 13 is formed in this way, automatic optical inspection (AOI) is performed on the wiring pattern 13 by an appearance inspection apparatus (not shown) (step S2 in FIG. 1).

具体的には、予め配線パターン13の正常な状態を示す画像が画像データとして外観検査装置に記憶される。この記憶された画像データによって示される状態と色および形状等が異なる配線パターン13の部分が、欠陥として検出される。   Specifically, an image indicating the normal state of the wiring pattern 13 is stored in advance in the appearance inspection apparatus as image data. A portion of the wiring pattern 13 that is different in color, shape, etc. from the state indicated by the stored image data is detected as a defect.

続いて、図2(d)に示すように、配線パターン13を覆うように無電解錫めっき層14を形成し、配線パターン13の表面処理を行う(図1のステップS3)。この表面処理により、配線回路基板上に図示しない電子部品を実装する際において、配線パターン13と電子部品との接続性を十分に確保することができる。   Subsequently, as shown in FIG. 2D, an electroless tin plating layer 14 is formed so as to cover the wiring pattern 13, and the surface treatment of the wiring pattern 13 is performed (step S3 in FIG. 1). With this surface treatment, when an electronic component (not shown) is mounted on the printed circuit board, the connectivity between the wiring pattern 13 and the electronic component can be sufficiently ensured.

錫めっき層14は、表面処理層の一例である。ここで、表面処理層の材料としては、銅からなる配線パターン3の材料よりも高い耐酸化性を有する金属または合金を用いることが好ましい。錫めっき層14の厚みは例えば2μm以下であり、0.1μm以上1μm以下であることが好ましい。なお、錫めっき層14の代わりに、ニッケルめっき層等の他の材料からなる層を形成してもよい。   The tin plating layer 14 is an example of a surface treatment layer. Here, as the material of the surface treatment layer, it is preferable to use a metal or alloy having higher oxidation resistance than the material of the wiring pattern 3 made of copper. The thickness of the tin plating layer 14 is, for example, 2 μm or less, and preferably 0.1 μm or more and 1 μm or less. Instead of the tin plating layer 14, a layer made of another material such as a nickel plating layer may be formed.

次に、図示しないCCD(電荷結合素子)等の撮像装置により、AOIにおいて検出された配線パターン13の欠陥の部分を撮像し、オペレータがその画像に基づいてAOIの結果の確認(ベリファイ)を行う(図1のステップS4)。   Next, a defective portion of the wiring pattern 13 detected in the AOI is imaged by an imaging device such as a CCD (Charge Coupled Device) (not shown), and the operator confirms (verifies) the AOI result based on the image. (Step S4 in FIG. 1).

AOIにおいては、実際には欠陥でない擬似欠陥も欠陥として検出されることがある。ここで、擬似欠陥とは、特性に影響を与えない外観上の欠陥をいう。例えば、配線パターン13の酸化による変色は擬似欠陥であり、実際の欠陥ではないが、AOIにおいては欠陥として検出される。   In the AOI, a pseudo defect that is not actually a defect may be detected as a defect. Here, the pseudo defect refers to an appearance defect that does not affect the characteristics. For example, discoloration due to oxidation of the wiring pattern 13 is a pseudo defect and not an actual defect, but is detected as a defect in the AOI.

ベリファイ時には、オペレータが、AOIにおいて検出された欠陥が実際の欠陥であるか擬似欠陥であるかを目視によって判定する。そして、オペレータは、実際の欠陥でないと判定した半製品(図2(d)の状態)を良品として振り分け、実際の欠陥であると判定した半製品を不良品として振り分ける(図1のステップS5)。   At the time of verification, the operator visually determines whether the defect detected in the AOI is an actual defect or a pseudo defect. Then, the operator distributes the semi-finished product determined as not an actual defect (the state shown in FIG. 2D) as a non-defective product, and distributes the semi-finished product determined as an actual defect as a defective product (step S5 in FIG. 1). .

良品として振り分けられた半製品に対しては、引き続き製造工程に準じた処理を行う(図1のステップS6)。例えば、図2(e)に示すように、配線パターン13および無電解錫めっき層14を覆うようにベース絶縁層11上に例えばポリイミドからなるカバー絶縁層15を形成する。カバー絶縁層15は、第2の絶縁層の一例である。カバー絶縁層15の厚みは例えば4μm以上26μm以下であり、5μm以上21μm以下であることが好ましい。カバー絶縁層15の材料としては、ポリイミドに代えてエポキシ等の他の絶縁材料を用いてもよい。これにより、配線回路基板1が完成する。   The semi-finished product that has been distributed as a non-defective product is subsequently processed according to the manufacturing process (step S6 in FIG. 1). For example, as shown in FIG. 2E, a cover insulating layer 15 made of polyimide, for example, is formed on the base insulating layer 11 so as to cover the wiring pattern 13 and the electroless tin plating layer 14. The insulating cover layer 15 is an example of a second insulating layer. The thickness of the insulating cover layer 15 is, for example, 4 μm or more and 26 μm or less, and preferably 5 μm or more and 21 μm or less. As the material of the insulating cover layer 15, other insulating materials such as epoxy may be used instead of polyimide. Thereby, the printed circuit board 1 is completed.

一方、不良品として振り分けられた半製品に対しては、廃棄または修理等の処理を行う(図1のステップS7)。   On the other hand, processing such as disposal or repair is performed on the semi-finished product distributed as a defective product (step S7 in FIG. 1).

このように、本実施の形態では、AOIの結果のベリファイの前に、配線パターン13の表面処理が行われる。この場合、酸化によって変色した配線パターン13の部分が無電解錫めっき層14によって覆われる。そのため、オペレータが配線パターン13の変色を欠陥と誤認識することが防止される。したがって、誤って不良品に振り分けられる半製品の数を低減することができ、生産性を向上させることができる。   Thus, in the present embodiment, the surface treatment of the wiring pattern 13 is performed before the verification of the AOI result. In this case, the portion of the wiring pattern 13 discolored by oxidation is covered with the electroless tin plating layer 14. This prevents the operator from erroneously recognizing the discoloration of the wiring pattern 13 as a defect. Therefore, the number of semi-finished products that are mistakenly assigned to defective products can be reduced, and productivity can be improved.

また、配線パターン13の表面処理は、AOIの後に行われる。すなわち、AOI時には、配線パターン13が露出する。この場合、配線パターン13の露出面が鏡面状態となるため、AOIにおいて、より精細な検査を行うことが可能になる。それにより、欠陥の検出漏れが発生することを確実に防止することができる。   Further, the surface treatment of the wiring pattern 13 is performed after the AOI. That is, at the time of AOI, the wiring pattern 13 is exposed. In this case, since the exposed surface of the wiring pattern 13 is in a mirror surface state, it becomes possible to perform a finer inspection in the AOI. Thereby, it is possible to reliably prevent the occurrence of defect detection failure.

なお、複数の半製品が長尺状に連結されている場合等には、ベリファイ後に行う製造工程(本例ではカバー絶縁層11の形成)の前に、良品と不良品とを振り分けることが困難となる。その場合、例えば欠陥を有する半製品に識別マークを形成し、ベリファイ後の製造工程が終了した後に、識別マークに基づいて良品と不良品とを振り分けてもよい。   In addition, when a plurality of semi-finished products are connected in a long shape, it is difficult to sort good products from defective products before the manufacturing process (in this example, the formation of the cover insulating layer 11) performed after verification. It becomes. In that case, for example, an identification mark may be formed on a semi-finished product having a defect, and after the manufacturing process after verification is completed, a non-defective product and a defective product may be sorted based on the identification mark.

また、この場合には、製造工程の終了後において、良品と不良品とを振り分けなくてもよい。すなわち、良品と不良品とが連結された状態の製品が完成する。その場合、識別マークによって良品と不良品とを判断することができるので、良品のみを選別して使用することができる。   In this case, it is not necessary to distribute the non-defective product and the defective product after completion of the manufacturing process. That is, a product in a state where a good product and a defective product are connected is completed. In this case, since the non-defective product and the defective product can be determined by the identification mark, only the non-defective product can be selected and used.

本発明は、フレキシブル配線回路基板またはリジッド配線回路基板等の種々の配線回路基板の製造に適用することができる。   The present invention can be applied to the manufacture of various printed circuit boards such as a flexible printed circuit board or a rigid printed circuit board.

本発明は、種々の配線回路基板の製造に有効に利用することができる。   The present invention can be effectively used for manufacturing various printed circuit boards.

本実施の形態に係る配線回路基板の製造方法の概要を示すフローチャートである。It is a flowchart which shows the outline | summary of the manufacturing method of the printed circuit board which concerns on this Embodiment. 本実施の形態に係る配線回路基板の製造工程の一例を示す断面図である。It is sectional drawing which shows an example of the manufacturing process of the printed circuit board which concerns on this Embodiment.

符号の説明Explanation of symbols

1 配線回路基板
10 金属基板
12 ベース絶縁層
13 配線パターン
14 錫めっき層
15 カバー絶縁層
DESCRIPTION OF SYMBOLS 1 Wiring circuit board 10 Metal substrate 12 Base insulating layer 13 Wiring pattern 14 Tin plating layer 15 Cover insulating layer

Claims (4)

基板上に配線パターンを形成する工程と、
検査装置によって前記配線パターンの外観検査を行うことにより前記配線パターンにおいて欠陥の可能性がある部分を検出する工程と、
外観検査後に前記配線パターン上に表面処理層を形成する工程と、
前記表面処理層の形成後に、外観検査により検出された前記配線パターンの部分を撮像する工程と、
前記撮像する工程で得られた画像上において、外観検査により検出された前記配線パターンの部分に実際に欠陥があるか否かを目視により確認する工程とを備えることを特徴とする配線回路基板の製造方法。
Forming a wiring pattern on the substrate;
A step of detecting a possible defect in the wiring pattern by performing an appearance inspection of the wiring pattern by an inspection device;
Forming a surface treatment layer on the wiring pattern after appearance inspection;
Imaging the portion of the wiring pattern detected by appearance inspection after the surface treatment layer is formed;
And a step of visually checking whether or not the portion of the wiring pattern detected by the appearance inspection actually has a defect on the image obtained in the imaging step. Production method.
前記表面処理層の材料は、前記配線パターンの材料よりも高い耐酸化性を有することを特徴とする請求項1記載の配線回路基板の製造方法。 2. The method of manufacturing a printed circuit board according to claim 1, wherein the material of the surface treatment layer has higher oxidation resistance than the material of the wiring pattern. 前記配線パターンは銅を含み、前記表面処理層は錫およびニッケルのうち少なくとも1つを含むことを特徴とする請求項2記載の配線回路基板の製造方法。 3. The method for manufacturing a printed circuit board according to claim 2, wherein the wiring pattern includes copper, and the surface treatment layer includes at least one of tin and nickel. 前記基板として第1の絶縁層を準備する工程と、
前記目視により確認する工程後に、前記配線パターンを覆うように第2の絶縁層を形成する工程とをさらに備えることを特徴とする請求項1〜3のいずれかに記載の配線回路基板の製造方法。
Preparing a first insulating layer as the substrate;
The method for manufacturing a printed circuit board according to claim 1, further comprising a step of forming a second insulating layer so as to cover the wiring pattern after the visual confirmation step. .
JP2008301527A 2008-11-26 2008-11-26 Method for manufacturing printed circuit board Active JP5127681B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105979706A (en) * 2015-03-12 2016-09-28 日东电工株式会社 Method of manufacturing printed circuit board and method of inspecting printed circuit board
US10067073B2 (en) 2015-03-12 2018-09-04 Nitto Denko Corporation Method of manufacturing printed circuit board and method of inspecting printed circuit board
CN109451652A (en) * 2018-10-25 2019-03-08 东莞泰山电子有限公司 The test method of back-shaped route PCB line anomalies
JP2020073922A (en) * 2020-01-31 2020-05-14 日東電工株式会社 Manufacturing method and inspection method for wiring circuit board

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005019469A (en) * 2003-06-23 2005-01-20 Mitsui Mining & Smelting Co Ltd Method of manufacturing flexible printed wiring board
JP2006066624A (en) * 2004-08-26 2006-03-09 Mitsui Mining & Smelting Co Ltd Pre-processing method for electric inspection of conductor pattern, electric inspection method and apparatus of conductor pattern, pre-processing apparatus for electric inspection of conductor pattern, inspected printed wiring board, and inspected semiconductor device

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2005019469A (en) * 2003-06-23 2005-01-20 Mitsui Mining & Smelting Co Ltd Method of manufacturing flexible printed wiring board
JP2006066624A (en) * 2004-08-26 2006-03-09 Mitsui Mining & Smelting Co Ltd Pre-processing method for electric inspection of conductor pattern, electric inspection method and apparatus of conductor pattern, pre-processing apparatus for electric inspection of conductor pattern, inspected printed wiring board, and inspected semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105979706A (en) * 2015-03-12 2016-09-28 日东电工株式会社 Method of manufacturing printed circuit board and method of inspecting printed circuit board
US10067073B2 (en) 2015-03-12 2018-09-04 Nitto Denko Corporation Method of manufacturing printed circuit board and method of inspecting printed circuit board
US10212869B2 (en) 2015-03-12 2019-02-19 Nitto Denko Corporation Method of manufacturing printed circuit board and method of inspecting printed circuit board
CN109451652A (en) * 2018-10-25 2019-03-08 东莞泰山电子有限公司 The test method of back-shaped route PCB line anomalies
JP2020073922A (en) * 2020-01-31 2020-05-14 日東電工株式会社 Manufacturing method and inspection method for wiring circuit board

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