JP2010123925A - Thin-film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor that controls threshold voltages, and has high on currents and low off currents. <P>SOLUTION: The thin-film transistor includes: a gate electrode; a first gate insulating layer formed on the gate electrode; a microcrystalline semiconductor layer formed on the first gate insulating layer; a pair of buffer layers formed on the microcrystalline semiconductor layer; an impurity semiconductor layer formed on the pair of buffer layers; wiring formed on a pair of impurity semiconductor layers; a second gate insulating layer formed on the microcrystalline semiconductor layer and the wiring; and a back gate electrode formed on the second gate insulating layer. In this case, a surface, which is at a side abutting on the pair of buffer layers on the microcrystalline semiconductor layer, is irregular. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a thin film transistor.

As a kind of field effect transistor, a thin film transistor in which a channel formation region is formed in a semiconductor layer formed over a substrate having an insulating surface is known. A technique using amorphous silicon, microcrystalline silicon, or polycrystalline silicon as a semiconductor layer used in a thin film transistor is disclosed (see Patent Documents 1 to 5). A typical application example of a thin film transistor is a liquid crystal television device, which is put into practical use as a switching transistor of each pixel constituting a display screen.

The thin film transistor is turned on when the gate voltage (potential difference from the gate potential with respect to the source potential) becomes equal to or higher than the threshold voltage. The threshold voltage is determined by the structure of the thin film transistor, the film forming conditions of each layer constituting the thin film transistor, and the like. In order to control the threshold voltage of such a thin film transistor, a technique of providing a further gate electrode (referred to as a back gate electrode) at a position facing the gate electrode is known (for example, see Non-Patent Document 1). reference). In Non-Patent Document 1, an insulating film is provided so as to cover the thin film transistor, and a back gate electrode is provided in a region overlapping with the back channel on the insulating film. The drain current (current flowing between the source and drain) is increased by the back gate electrode, and the on-current is increased accordingly.

JP 2001-053283 A JP-A-5-129608 JP 2005-049832 A Japanese Patent Laid-Open No. 7-131030 JP 2005-191546 A

Yong-Soo Cho et al., "Characteristics of a-Si: H Dual-Gate TFTs Using ITO Electrode for LCD Driver", AM-FPD'08 DIGIEST OF TECHNICAL PAPERS, pp. 229-232

A thin film transistor in which a channel formation region is formed using an amorphous silicon layer has a problem of low field-effect mobility and on-state current. On the other hand, a thin film transistor in which a channel formation region is formed using a microcrystalline silicon layer has improved field-effect mobility but higher off-state current than an amorphous silicon thin film transistor, and thus has sufficient switching characteristics. There is a problem that it is not possible.

A thin film transistor in which a channel formation region is formed using a polycrystalline silicon layer has characteristics that field effect mobility is significantly higher than that of the above two types of thin film transistors, and a high on-state current can be obtained. Due to the above-described characteristics, this thin film transistor can constitute not only a switching transistor provided in a pixel but also a driver circuit that requires high-speed operation.

However, a thin film transistor in which a channel formation region is formed of a polycrystalline silicon layer requires a semiconductor layer crystallization step as compared with a case where a thin film transistor is formed of an amorphous silicon layer, which increases the manufacturing cost. ing. For example, a laser annealing technique necessary for manufacturing a polycrystalline silicon layer has a problem that a large area liquid crystal panel cannot be efficiently produced with a small laser beam irradiation area.

By the way, the glass substrate used for manufacturing the display panel is the third generation (550 mm × 650 mm), the 3.5th generation (600 mm × 720 mm, or 620 mm × 750 mm), the fourth generation (680 mm × 880 mm, or 730 mm). × 920mm), 5th generation (1100mm × 1300mm), 6th generation (1500mm × 1850mm), 7th generation (1870mm × 2200mm), 8th generation (2200mm × 2400mm) It is predicted that the area will increase toward the ninth generation (2400 mm × 2800 mm, 2450 mm × 3050 mm) and the tenth generation (2950 mm × 3400 mm). The increase in size of the glass substrate is based on the idea of cost minimum design.

On the other hand, a technology capable of manufacturing a thin film transistor capable of high-speed operation with high productivity on a mother glass substrate having a large area as in the 10th generation (2950 mm × 3400 mm) has not yet been established. This is a problem for industry.

Thus, an object is to provide a thin film transistor which can control a threshold voltage and has high on-state current and low off-state current.

Further, an object is to manufacture a thin film transistor having the above characteristics by a simple manufacturing process, which can be applied to a display device.

As an exemplary embodiment of the present invention, a gate electrode, a first gate insulating layer formed over the gate electrode, a microcrystalline semiconductor layer formed over the first gate insulating layer, and a microcrystalline semiconductor A pair of buffer layers formed over the layer, an impurity semiconductor layer formed over the pair of buffer layers, a wiring formed over the pair of impurity semiconductor layers, a microcrystalline semiconductor layer, and the wiring The thin film transistor includes a second gate insulating layer and a back gate electrode formed over the second gate insulating layer. In the microcrystalline semiconductor layer, a surface in contact with the pair of buffer layers is uneven. Further, the gate electrode, the first gate insulating layer, the microcrystalline semiconductor layer, the second gate insulating layer, and the back gate electrode overlap with each other. Further, the microcrystalline semiconductor layer is a surface in contact with the pair of buffer layers and is in contact with the insulating layer in a region where the pair of buffer layers is not formed. Therefore, the off current can be suppressed while increasing the on current of the thin film transistor.

As an exemplary embodiment of the present invention, a gate electrode, a first gate insulating layer formed over the gate electrode, a first microcrystalline semiconductor layer formed over the first gate insulating layer, A second microcrystalline semiconductor layer having a plurality of conical protrusions formed on the first microcrystalline semiconductor layer; and a pair of buffer layers formed on the second microcrystalline semiconductor layer. In addition, a pair of impurity semiconductor layers functioning as a source region and a drain region formed over the pair of buffer layers, a wiring formed over the pair of impurity semiconductor layers, a second microcrystalline semiconductor layer, and the wiring A thin film transistor having a second gate insulating layer to be formed and a back gate electrode formed over the second gate insulating layer, the gate electrode, the first gate insulating layer, the first microcrystalline semiconductor layer, the first The two microcrystalline semiconductor layers, the second gate insulating layer, and the back gate electrode overlap with each other. Further, the second microcrystalline semiconductor layer is a surface in contact with the pair of buffer layers, and is in contact with the second gate insulating layer in a region where the pair of buffer layers is not formed. Therefore, the off current can be suppressed while increasing the on current of the thin film transistor.

Note that the pair of buffer layers are formed of an amorphous silicon layer.

In the case where the impurity semiconductor layer functioning as a source region and a drain region is formed using a microcrystalline semiconductor layer to which an impurity element imparting one conductivity type is added, a microscopic semiconductor layer is interposed between the pair of buffer layers and the impurity semiconductor layer. A crystalline semiconductor layer may be formed.

The on-state current refers to a current that flows between the source electrode and the drain electrode when the thin film transistor is on. For example, in the case of an n-type thin film transistor, the current flows between the source electrode and the drain electrode when the gate voltage is higher than the threshold voltage of the thin film transistor.

An off-state current is a current that flows between a source electrode and a drain electrode when a transistor is off. For example, in the case of an n-type thin film transistor, the current flows between the source electrode and the drain electrode when the gate voltage is lower than the threshold voltage of the thin film transistor.

Compared with a thin film transistor having an amorphous semiconductor in a channel formation region, the on-state current of the thin film transistor is increased and a thin film transistor having a microcrystalline semiconductor in a channel formation region can be controlled. Thus, the off-state current of the thin film transistor can be reduced.

FIG. 10 is a cross-sectional view illustrating a thin film transistor according to an embodiment mode. It is a top view explaining the thin-film transistor which concerns on this Embodiment. FIG. 10 is a cross-sectional view illustrating a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. FIG. 10 is a plan view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. FIG. 10 is a cross-sectional view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. FIG. 10 is a plan view illustrating a manufacturing process of a thin film transistor according to an embodiment mode. 10A to 10D illustrate a multi-tone mask applicable to the method for manufacturing a thin film transistor according to this embodiment. 5A and 5B are a plan view and a cross-sectional view illustrating a thin film transistor according to an embodiment mode. It is a top view explaining the thin-film transistor which concerns on this Embodiment. 5A and 5B are a plan view and a cross-sectional view illustrating a thin film transistor according to an embodiment mode.

Hereinafter, embodiments will be described with reference to the drawings. However, the disclosed invention is not limited to the following description. Those skilled in the art will readily understand that various changes can be made in form and details without departing from the spirit and scope of the disclosed invention. Therefore, the disclosed invention is not construed as being limited to the description of the embodiments and examples below. Note that in describing the structure of the disclosed invention with reference to the drawings, the same portions are denoted by the same reference numerals in different drawings.

(Embodiment 1)
In this embodiment, an example of a thin film transistor is described with reference to drawings.

FIG. 1 is a sectional view of a thin film transistor according to this embodiment. 1 includes a gate electrode 103 over a substrate 101, a first gate insulating layer 107 covering the gate electrode 103, and a first microcrystalline semiconductor layer in contact with the first gate insulating layer 107. A microcrystalline semiconductor layer 117 in which the first microcrystalline semiconductor layer 117b and the second microcrystalline semiconductor layer 117b are stacked; the microcrystalline semiconductor layer 117 includes a pair of buffer layers 135; An impurity semiconductor layer 131 which functions as a region is included. In addition, wirings 125 and 127 are provided in contact with the impurity semiconductor layer 131. The wirings 125 and 127 function as a source electrode and a drain electrode. The wirings 125 and 127 are in contact with the side surfaces of the microcrystalline semiconductor layer 117 and the pair of buffer layers 135. A first insulating layer 136a is formed on the surface of the second microcrystalline semiconductor layer 117b. In addition, a second insulating layer 136 c is formed in the pair of buffer layers 135 and the impurity semiconductor layer 131. A third insulating layer 136e is formed on the wirings 125 and 127. Further, the second gate insulating layer 137 covering the first insulating layer 136a, the second insulating layer 136c, and the third insulating layer 136e, and the back gate electrode 145 formed over the second gate insulating layer 137 are provided. Have

As the substrate 101, a glass substrate, a ceramic substrate, a plastic substrate having heat resistance enough to withstand the processing temperature of the manufacturing process, or the like can be used. In the case where the substrate does not require translucency, a metal substrate such as a stainless alloy provided with an insulating layer on the surface may be used. As the glass substrate, for example, an alkali-free glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass may be used. Further, as the substrate 101, the third generation (550 mm × 650 mm), the 3.5th generation (600 mm × 720 mm, or 620 mm × 750 mm), the fourth generation (680 mm × 880 mm, or 730 mm × 920 mm), the fifth generation (1100 mm). × 1300mm), 6th generation (1500mm × 1850mm), 7th generation (1870mm × 2200mm), 8th generation (2200mm × 2400mm), 9th generation (2400mm × 2800mm, 2450mm × 3050mm), 10th generation (2950mm × A glass substrate such as 3400 mm) can be used.

The gate electrode 103 may be formed as a single layer or a stack using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium, or an alloy material containing any of these materials as its main component. it can. Alternatively, a semiconductor layer typified by polycrystalline silicon doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used.

For example, a two-layer structure of the gate electrode 103 includes a two-layer structure in which a molybdenum layer is stacked on an aluminum layer, a two-layer structure in which a molybdenum layer is stacked on a copper layer, or a nitridation on a copper layer. A two-layer structure in which a titanium layer or a tantalum nitride layer is stacked, or a two-layer structure in which a titanium nitride layer and a molybdenum layer are stacked is preferable. The three-layer structure is preferably a stack in which a tungsten layer or a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer are stacked. When a metal layer functioning as a barrier layer is stacked over a layer with low electrical resistance, electrical resistance is low and diffusion of a metal element from the metal layer to the semiconductor layer can be prevented.

The first gate insulating layer 107 can be formed using a single layer or stacked layers of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer by a CVD method, a sputtering method, or the like. In addition, when the first gate insulating layer 107 is formed using silicon oxide or silicon oxynitride, variation in threshold voltage of the thin film transistor can be reduced.

The first gate insulating layer 107 is formed with a thickness of 50 nm to 550 nm, preferably a thickness of 50 nm to 300 nm. In particular, when the gate electrode 103 is formed by a sputtering method, irregularities are often generated on the surface thereof. With such a thickness, reduction in coverage of the first gate insulating layer 107 due to unevenness of the gate electrode 103 can be reduced.

Note that in this specification, silicon oxynitride has a higher oxygen content than nitrogen as a composition, and preferably Rutherford Backscattering Spectroscopy (RBS) and hydrogen forward scattering. When measured by the method (HFS: Hydrogen Forward Scattering), the composition ranges from 50 to 70 atomic% for oxygen, 0.5 to 15 atomic% for nitrogen, 25 to 35 atomic% for silicon, and 0.1 for hydrogen. The thing contained in the range of -10 atomic%. In addition, silicon nitride oxide has a composition containing more nitrogen than oxygen, and preferably has a composition range of 5 to 30 atomic% when measured using RBS and HFS. Nitrogen is contained in the range of 20 to 55 atomic%, silicon is contained in the range of 25 to 35 atomic%, and hydrogen is contained in the range of 10 to 30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, silicon, and hydrogen is included in the above range.

The microcrystalline semiconductor layer 117 includes a first microcrystalline semiconductor layer 117a in contact with the first gate insulating layer 107, and a second microcrystalline semiconductor layer 117b having a plurality of conical protrusions (convex portions).

The microcrystalline semiconductor layer 117 is formed using a microcrystalline semiconductor layer. A microcrystalline semiconductor is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). A microcrystalline semiconductor is a semiconductor having a third state which is stable in terms of free energy, is a crystalline semiconductor having a short-range order and lattice distortion, and has a crystal grain size of 2 nm to 200 nm, preferably 10 nm. Columnar crystals or needle-like crystals having a thickness of 80 nm or more and more preferably 20 nm or more and 50 nm or less grow in the normal direction with respect to the substrate surface. For this reason, a crystal grain boundary may be formed at the interface between the columnar crystal or the needle crystal.

Typical examples of the microcrystalline semiconductor layer include a microcrystalline silicon layer, a microcrystalline germanium layer, and a microcrystalline silicon germanium layer.

Microcrystalline silicon which is a typical example of a microcrystalline semiconductor has a Raman spectrum shifted to a lower wave number side than 520 cm ⁻¹ indicating single crystal silicon. That is, the peak of the Raman spectrum of microcrystalline silicon is between 520 cm ⁻¹ indicating single crystal silicon and 480 cm ⁻¹ indicating amorphous silicon. In addition, at least 1 atomic% or more of hydrogen or halogen is contained to terminate dangling bonds (dangling bonds). Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote the lattice distortion, the stability can be improved and a good microcrystalline semiconductor can be obtained. A description of such a microcrystalline semiconductor is disclosed, for example, in US Pat. No. 4,409,134.

The concentration of oxygen and nitrogen contained in the microcrystalline semiconductor layer 117 measured by secondary ion mass spectrometry is less than 1 × 10 ¹⁸ atoms / cm ³ , so that the crystallinity of the microcrystalline semiconductor layer 117 can be increased. Since it can raise, it is preferable.

The pair of buffer layers 135 is formed using an amorphous semiconductor layer, an amorphous semiconductor layer containing halogen, or an amorphous semiconductor layer containing nitrogen. Nitrogen contained in the amorphous semiconductor layer containing nitrogen may exist as, for example, an NH group or an NH ₂ group. The amorphous semiconductor layer is formed using amorphous silicon.

Between the impurity semiconductor layer 131 and the first microcrystalline semiconductor layer 117a, a second microcrystalline semiconductor layer 117b in contact with the first microcrystalline semiconductor layer 117a and a pair of contacts in contact with the second microcrystalline semiconductor layer 117b A buffer layer 135 is provided.

The pair of buffer layers 135 are formed using an amorphous semiconductor layer with low electrical conductivity and high resistivity, an amorphous semiconductor layer containing halogen, and an amorphous semiconductor layer containing nitrogen; Can be reduced. In addition, when the pair of buffer layers 135 are formed using an amorphous semiconductor layer containing nitrogen, the slope becomes steeper and the band gap becomes wider than the band tail of the band gap of the amorphous semiconductor layer. Becomes difficult to flow. As a result, the off-state current of the thin film transistor can be reduced.

The second microcrystalline semiconductor layer 117b is formed of a microcrystalline semiconductor layer having a plurality of conical protrusions (convex portions). Here, the “conical shape” means a convex shape whose tip is narrowed from the first gate insulating layer 107 toward the pair of buffer layers 135, and includes a needle-like shape. Note that the plurality of conical protrusions (convex portions) may have a convex shape whose width extends from the first gate insulating layer 107 toward the pair of buffer layers 135. Since the second microcrystalline semiconductor layer 117b is formed using a conical microcrystalline semiconductor layer, resistance in the vertical direction (film thickness direction) when the thin film transistor is on, that is, the first microcrystalline semiconductor layer 117a. Between the source region and the drain region and the on-state current of the thin film transistor can be increased.

The second microcrystalline semiconductor layer 117b preferably contains nitrogen. This is because nitrogen, typically an NH group or an NH ₂ group, is present at the interface between crystal grains included in the second microcrystalline semiconductor layer 117b or the interface between the second microcrystalline semiconductor layer 117b and the pair of buffer layers 135. This is because defects are reduced when bonded to dangling bonds of silicon atoms. Therefore, the nitrogen concentration of the second microcrystalline semiconductor layer 117b is 1 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / cm ³ or less, 1 × 10 ²⁰ atoms / cm ^{3 to} 1 × 10 ²¹ atoms / cm. ^By setting it to ³ , dangling bonds of silicon atoms are easily cross-linked with nitrogen, preferably NH groups, and carriers can easily flow. Alternatively, the dangling bonds of the semiconductor atoms at the interface described above are terminated with NH ₂ groups, and the defect level disappears. As a result, resistance in the vertical direction (thickness direction) when a voltage is applied between the source electrode and the drain electrode in the on state is reduced. That is, the field effect mobility and the on-current of the thin film transistor are increased.

Note that the first microcrystalline semiconductor layer 117a and the second microcrystalline semiconductor layer 117b may have different contents of nitrogen or hydrogen. This is because film formation conditions of the first microcrystalline semiconductor layer 117a and the second microcrystalline semiconductor layer 117b are different, and the second microcrystalline semiconductor layer 117b contains more nitrogen or hydrogen. May be.

The sum of the thicknesses of the first microcrystalline semiconductor layer 117a and the second microcrystalline semiconductor layer 117b, that is, from the interface between the first gate insulating layer 107 and the tip of the convex portion of the second microcrystalline semiconductor layer 117b. When the distance is 3 nm to 80 nm, preferably 5 nm to 30 nm, the off-state current of the thin film transistor can be reduced.

The first insulating layer 136a is formed using an oxide layer obtained by oxidizing the second microcrystalline semiconductor layer 117b or a nitride layer obtained by nitriding the second microcrystalline semiconductor layer 117b.

The second insulating layer 136c is formed of an oxide layer obtained by oxidizing the pair of buffer layers 135 and the impurity semiconductor layer 131, or a nitride layer obtained by nitriding the pair of buffer layers 135 and the impurity semiconductor layer 131.

The third insulating layer 136e is formed of an oxide layer obtained by oxidizing the wirings 125 and 127 or a nitride layer obtained by nitriding the wirings 125 and 127. Note that here, the third insulating layer 136e is formed over the top surfaces and side surfaces of the wirings 125 and 127, but is formed only over the side surfaces of the wirings 125 and 127, and may not be formed over the top surfaces of the wirings 125 and 127. is there.

The amorphous semiconductor layer has a weak n-type. In addition, the density is lower than that of the microcrystalline semiconductor layer. Therefore, the second insulating layer 136c obtained by oxidizing or nitriding the amorphous semiconductor layer has a low density, is a sparse insulating layer, and has low insulating properties. However, in the thin film transistor described in this embodiment, a first insulating layer 136a obtained by oxidizing the second microcrystalline semiconductor layer 117b formed using a microcrystalline semiconductor layer is formed on the back channel side. Since the microcrystalline semiconductor layer has a higher density than the amorphous semiconductor layer, the first insulating layer 136a also has a higher density and higher insulating properties. Further, since the second microcrystalline semiconductor layer 117b includes a plurality of conical protrusions (convex portions), the surface is uneven. For this reason, the distance of the leak path from the source region to the drain region is long. From these results, leakage current and off-state current of the thin film transistor can be reduced.

The impurity semiconductor layer 131 is formed using amorphous silicon to which phosphorus is added, microcrystalline silicon to which phosphorus is added, or the like. Note that in the case where a p-channel thin film transistor is formed as the thin film transistor, the impurity semiconductor layer 131 is formed using microcrystalline silicon to which boron is added, amorphous silicon to which boron is added, or the like. Note that in the case where the second microcrystalline semiconductor layer 117b or the pair of buffer layers 135 and the wirings 125 and 127 are in ohmic contact, the impurity semiconductor layer 131 is not necessarily formed.

The wirings 125 and 127 can be formed of a single layer or a stacked layer using aluminum, copper, titanium, neodymium, scandium, molybdenum, chromium, tantalum, tungsten, or the like. Alternatively, an aluminum alloy to which a hillock prevention element is added (such as an Al—Nd alloy that can be used for the gate electrode 103) may be used. Crystalline silicon to which an impurity element which serves as a donor is added may be used. The layer on the side in contact with the crystalline silicon to which the impurity element to be a donor is added is formed of titanium, tantalum, molybdenum, tungsten, or nitride of these elements, and a laminated structure in which aluminum or an aluminum alloy is formed thereon Also good. Furthermore, a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements may be employed.

The second gate insulating layer 137 can be formed in a manner similar to that of the first gate insulating layer 107. The second gate insulating layer 137 is formed with a thickness of 50 nm to 550 nm, preferably 50 nm to 300 nm, as in the first gate insulating layer 107.

The back gate electrode 145 can be formed in a manner similar to that of the gate electrode 103 and the wirings 125 and 127. Further, the back gate electrode 145 is formed using indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, or indium zinc oxide. Or indium tin oxide to which silicon oxide is added can be used.

Here, the shape of the back gate electrode is described with reference to FIG. 2 which is a plan view of the thin film transistor described in this embodiment.

As shown in FIG. 2A, the back gate electrode 145 can be formed in parallel with the gate electrode 103. In this case, the potential applied to the back gate electrode 145 and the potential applied to the gate electrode 103 can be arbitrarily controlled. For this reason, the threshold voltage of the thin film transistor can be controlled.

In addition, as illustrated in FIG. 2B, the back gate electrode 145 can be connected to the gate electrode 103. That is, the gate electrode 103 and the back gate electrode 145 can be connected to each other in the opening 149 formed in the first gate insulating layer 107 and the second gate insulating layer 137. In this case, the potential applied to the back gate electrode 145 is equal to the potential applied to the gate electrode 103. As a result, in the microcrystalline semiconductor layer, a region where carriers flow, that is, a channel is formed on the first gate insulating layer 107 side and the second gate insulating layer 137 side, so that the on-state current of the thin film transistor can be increased. it can.

Further, as illustrated in FIG. 2C, the back gate electrode 145 may overlap with the wirings 125 and 127 with the second gate insulating layer 137 interposed therebetween. Although the back gate electrode 145 having the structure illustrated in FIG. 2A is described here, the back gate electrode 145 illustrated in FIG. 2B may overlap with the wirings 125 and 127 in the same manner.

The thin film transistor described in this embodiment includes a back gate electrode 145. The channel formation region is formed of a microcrystalline semiconductor layer having a plurality of conical protrusions, and has a pair of buffer layers in contact with the microcrystalline semiconductor layer. Therefore, the threshold voltage can be controlled, and the on-state current of the thin film transistor is increased as compared with the thin film transistor having an amorphous semiconductor in the channel formation region, and the thin film transistor having a microcrystalline semiconductor in the channel formation region Compared with, the off-state current of the thin film transistor can be reduced.

(Embodiment 2)
In this embodiment, a mode of a thin film transistor, which is different from that in Embodiment 1, is described with reference to FIGS.

FIG. 3 is a cross-sectional view of the thin film transistor according to this embodiment. 3 includes a gate electrode 103 over a substrate 101, a first gate insulating layer 107 covering the gate electrode 103, and a first microcrystalline semiconductor in contact with the first gate insulating layer 107. A microcrystalline semiconductor layer 153 in which the layer 153a and the microcrystalline semiconductor layer 153b are stacked, a pair of buffer layers 171 is provided over the microcrystalline semiconductor layer 153, and is in contact with the buffer layer 171 to serve as a source region and a drain region A functioning impurity semiconductor layer 168 is provided. Further, wirings 165 and 167 are provided in contact with the impurity semiconductor layer 168. The wirings 165 and 167 function as a source electrode and a drain electrode. The wirings 165 and 167 are not in contact with the side surface of the microcrystalline semiconductor layer 153 and the side surfaces of the pair of buffer layers 171 and are in contact only with the upper surface of the impurity semiconductor layer 168. A first insulating layer 154a is formed on the surface and side surfaces of the first microcrystalline semiconductor layer 153a and the second microcrystalline semiconductor layer 153b. A second insulating layer 154 c is formed on the side surfaces of the pair of buffer layers 171 and the impurity semiconductor layer 168. A third insulating layer 154e is formed on the side surfaces of the wirings 165 and 167. Further, the second gate insulating layer 137 covering the first insulating layer 136a, the second insulating layer 136c, and the third insulating layer 136e, and the back gate electrode 145 formed over the second gate insulating layer 137 are provided. Have

In the thin film transistor of this embodiment, as illustrated in FIG. 12A, the impurity semiconductor layer 168 and the second microcrystalline semiconductor layer 153b are exposed on the outer edges of the wirings 165 and 167 in the top surface shape. Features. Such a structure is formed by using a photolithography process using a multi-tone mask.

The first microcrystalline semiconductor layer 153a and the second microcrystalline semiconductor layer 153b have materials and structures similar to those of the first microcrystalline semiconductor layer 117a and the second microcrystalline semiconductor layer 117b described in Embodiment 1, respectively. It can be formed as appropriate. The pair of buffer layers 171 can be formed using a material and a structure which are similar to those of the pair of buffer layers 135 described in Embodiment 1, as appropriate. The impurity semiconductor layer 168 can be formed using a material and a structure similar to those of the impurity semiconductor layer 131 described in Embodiment 1, as appropriate. The wirings 165 and 167 can be formed using a material similar to that of the wirings 125 and 127 described in Embodiment 1 as appropriate. The insulating layers 154a, 154c, and 154e can be formed using a material similar to that of the insulating layers 136a, 136c, and 136e described in Embodiment 1 as appropriate.

The thin film transistor described in this embodiment includes a back gate electrode 145. In addition, the microcrystalline semiconductor layer 153 functioning as a channel formation region has a plurality of conical protrusions (convex portions). Since the second microcrystalline semiconductor layer 153b is formed using a microcrystalline semiconductor layer having a plurality of conical protrusions (convex portions), the resistance in the vertical direction (film thickness direction) when the thin film transistor is on, that is, The resistance between the first microcrystalline semiconductor layer 153a and the source region or the drain region can be reduced, and the on-state current of the thin film transistor can be increased. In addition, a highly insulating insulating layer 154a is formed on the surface of the second microcrystalline semiconductor layer 153b, and the distance of the leak path is long because the surface is uneven. A pair of buffer layers is formed between the second microcrystalline semiconductor layer 153 b and the impurity semiconductor layer 168. Therefore, the off-state current of the thin film transistor can be reduced.

As described above, the threshold voltage can be controlled and the on-state current of the thin film transistor is increased and the microcrystalline semiconductor is used in the channel formation region as compared with the thin film transistor including an amorphous semiconductor in the channel formation region. The off-state current of the thin film transistor can be reduced as compared with the thin film transistor having the thin film transistor.

(Embodiment 3)
In this embodiment mode, structures applicable to Embodiment Modes 1 and 2 are described with reference to FIGS. Note that although this embodiment mode is described using the thin film transistor described in Embodiment Mode 2, this embodiment mode can be applied to Embodiment Mode 1 as appropriate.

FIG. 4 is a cross-sectional view of the thin film transistor according to this embodiment. 4 has a microcrystalline semiconductor layer 173 between the impurity semiconductor layer 168 and the pair of buffer layers 171, as compared to the thin film transistor described in Embodiment 2, and the impurity semiconductor layer 168 includes: It is characterized by being formed of a microcrystalline semiconductor to which an impurity imparting one conductivity type is added.

As the microcrystalline semiconductor layer 173, a microcrystalline silicon layer, a microcrystalline silicon germanium layer, or a microcrystalline germanium layer can be formed. Further, the microcrystalline semiconductor layer 173 may be formed with inverted conical crystal grains or columnar crystal grains extending in the film thickness direction. Alternatively, crystal grains may be arranged randomly.

The microcrystalline semiconductor to which an impurity imparting one conductivity type is added to form the impurity semiconductor layer 168 includes microcrystalline silicon to which phosphorus is added, microcrystalline silicon germanium to which phosphorus is added, and microcrystal to which phosphorus is added Germanium etc. Alternatively, there is microcrystalline silicon to which boron is added, microcrystalline silicon germanium to which boron is added, microcrystalline germanium to which boron is added, or the like.

With this structure, crystal growth of the impurity semiconductor layer 168 starts using the crystal of the microcrystalline semiconductor layer 173 as a seed crystal, so that low density layers in the initial stage of formation of the impurity semiconductor layer 168 are reduced and interface characteristics are improved. be able to. Therefore, resistance generated at the interface between the impurity semiconductor layer 168 and the microcrystalline semiconductor layer 173 can be reduced. As a result, particularly in a thin film transistor having a short channel length, it is possible to increase the on-state current and the field-effect mobility flowing through the source region, the semiconductor layer, and the drain region.

(Embodiment 4)
Here, a method for manufacturing the thin film transistor illustrated in FIGS. 1A to 1C is described with reference to FIGS. Thin film transistors have higher carrier mobility in the n-type than in the p-type. In addition, it is preferable that all thin film transistors formed over the same substrate have the same polarity because the number of steps can be reduced. Therefore, in this embodiment, a method for manufacturing an n-type thin film transistor is described.

First, the gate electrode 103 and the capacitor wiring 105 are formed over the substrate 101 (see FIG. 5A).

As the substrate 101, the substrate 101 described in Embodiment 1 can be used as appropriate.

The gate electrode 103 and the capacitor wiring 105 are formed using any of the materials described for the gate electrode 103 described in Embodiment 1 as appropriate. For the gate electrode 103 and the capacitor wiring 105, a conductive layer is formed using the above-described material by a sputtering method or a vacuum evaporation method over the substrate 101, and a mask is formed over the conductive layer by a photolithography method, an inkjet method, or the like. The conductive layer can be formed by etching using the mask. Alternatively, a conductive nano paste such as silver, gold, or copper can be formed by discharging onto a substrate by an ink jet method and baking. Note that a nitride layer of the above metal material may be provided between the substrate 101 and the gate electrode 103 and the capacitor wiring 105 in order to improve adhesion between the gate electrode 103 and the capacitor wiring 105 and the substrate 101. Here, a conductive layer is formed over the substrate 101 and etched using a resist mask formed using a photomask.

Note that side surfaces of the gate electrode 103 and the capacitor wiring 105 are preferably tapered. This is because an insulating layer, a semiconductor layer, and a wiring layer are formed on the gate electrode 103 in a later step, so that they are not cut at the level difference. In order to taper the side surfaces of the gate electrode 103 and the capacitor wiring 105, etching may be performed while retracting the resist mask. For example, it is possible to perform etching while retracting the resist by including oxygen gas in the etching gas.

Further, the gate electrode 103 can also be formed to serve as a gate wiring (scanning line). Note that a scanning line refers to a wiring for selecting a pixel, and a capacitor wiring refers to a wiring connected to one electrode of a storage capacitor of the pixel. However, the present invention is not limited to this, and one or both of the gate wiring and the capacitor wiring may be provided separately from the gate electrode 103.

Next, a first gate insulating layer 107 and a first microcrystalline semiconductor layer 109 are formed so as to cover the gate electrode 103.

The first gate insulating layer 107 can be formed using the material of the first gate insulating layer 107 described in Embodiment 1 as appropriate. The first gate insulating layer 107 can be formed by a CVD method, a sputtering method, or the like. The first gate insulating layer 107 may be formed using a microwave plasma CVD apparatus with a high frequency (1 GHz or more). When the first gate insulating layer 107 is formed at a high frequency using a microwave plasma CVD apparatus, the breakdown voltage between the gate electrode, the drain electrode, and the source electrode can be improved; thus, a highly reliable thin film transistor can be manufactured. Obtainable. Further, as the first gate insulating layer 107, it is possible to reduce the hydrogen content of the first first gate insulating layer by forming a silicon oxide layer by a CVD method using an organosilane gas. Variation in threshold voltage of the thin film transistor can be reduced. Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), and octamethylcyclotetrasiloxane. It is possible to use a silicon-containing compound such as (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ). it can.

The first microcrystalline semiconductor layer 109 is formed using microcrystalline silicon, microcrystalline silicon germanium, microcrystalline germanium, or the like. The first microcrystalline semiconductor layer 109 is formed with a thickness greater than or equal to 1 nm and less than or equal to 20 nm, preferably greater than or equal to 3 nm and less than or equal to 10 nm.

The first microcrystalline semiconductor layer 109 is formed by glow discharge plasma by mixing a deposition gas containing silicon or germanium with hydrogen in a reaction chamber of a plasma CVD apparatus. Alternatively, a deposition gas containing silicon or germanium, hydrogen, and a rare gas such as helium, neon, or krypton are mixed and formed by glow discharge plasma. The flow rate of hydrogen is diluted 10 to 2000 times, preferably 10 to 200 times the flow rate of the deposition gas containing silicon or germanium to form microcrystalline silicon, microcrystalline silicon germanium, microcrystalline germanium, or the like. .

Typical examples of the deposition gas containing silicon or germanium include SiH ₄ , Si ₂ H ₆ , GeH ₄ , and Ge ₂ H ₆ .

Note that before the first microcrystalline semiconductor layer 109 is formed, a deposition gas containing silicon or germanium is introduced while evacuating the treatment chamber of the CVD apparatus to remove impurity elements in the treatment chamber, An impurity element at an interface between the first gate insulating layer 107 and the first microcrystalline semiconductor layer 109 of the thin film transistor to be formed later can be reduced, so that electric characteristics of the thin film transistor can be improved.

Next, as illustrated in FIG. 5B, the second microcrystalline semiconductor layer 111 and the buffer layer 113 are formed over the first microcrystalline semiconductor layer 109. Next, a semiconductor layer to which an impurity imparting one conductivity type is added (hereinafter referred to as an impurity semiconductor layer 115) is formed over the buffer layer 113.

Here, the second microcrystalline semiconductor layer 111 and the buffer layer 113 are formed under a condition that the crystal growth is partially suppressed while the crystal is partially grown from the first microcrystalline semiconductor layer 109. Note that a deposition gas containing silicon or germanium and hydrogen are mixed in a reaction chamber of the plasma CVD apparatus, and the second microcrystalline semiconductor layer 111 and the buffer layer 113 are formed by glow discharge plasma. At this time, deposition is performed under a condition in which the flow rate of hydrogen with respect to the deposition gas containing silicon or germanium is reduced, that is, the crystal growth is reduced as compared with the deposition condition of the first microcrystalline semiconductor layer 109. Then, the crystal grows as a whole, but in the middle of the deposition, the crystal growth is gradually suppressed, and a plurality of conical projections (convex portions) are formed. The layer having a plurality of conical protrusions (convex portions) serves as the second microcrystalline semiconductor layer 111. Further, in the late stage of deposition, a buffer layer 113 that does not include a microcrystalline semiconductor region is formed. Here, a layer deposited at a later stage of deposition is referred to as a buffer layer 113. That is, the late deposition period is a period during which the buffer layer 113 is formed.

In addition, in the reaction chamber of the plasma CVD apparatus, a deposition gas containing silicon or germanium, hydrogen, and a gas containing nitrogen are mixed, and the second microcrystalline semiconductor layer 111 and the buffer layer 113 are formed by glow discharge plasma. To do. At this time, the flow rate of hydrogen with respect to the deposition gas containing silicon or germanium is reduced more than the film formation conditions of the first microcrystalline semiconductor layer 109, and the second microcrystalline semiconductor is mixed with a gas containing nitrogen. Crystal growth in the layer 111 is suppressed, and overall crystal growth occurs in the initial stage of deposition. However, in the middle stage of deposition, the crystal growth is gradually suppressed, and the second microcrystal having a plurality of conical protrusions (convex parts). A semiconductor layer 111 is formed. Further, in the late deposition stage, an amorphous semiconductor layer is formed without including a microcrystalline semiconductor region. Here, a layer deposited at a later stage of deposition is referred to as a buffer layer 113. In other words, the latter period of deposition of the second microcrystalline semiconductor layer 111 is a period for forming the buffer layer 113.

Note that the film formation conditions may be changed during film formation. For example, when the second microcrystalline semiconductor layer 111 is formed, the flow rate of hydrogen with respect to the deposition gas containing silicon or germanium is reduced (the first flow rate is lower than the deposition condition of the first microcrystalline semiconductor layer 109. Condition), a second microcrystalline semiconductor layer 111 having a plurality of conical protrusions (convex portions) is formed. Next, by reducing the flow rate of hydrogen with respect to the deposition gas containing silicon or germanium as compared with the first condition, the crystal growth is suppressed, and the buffer layer 113 formed of an amorphous semiconductor layer is formed. can do. Alternatively, in addition to the first condition, the flow rate of hydrogen with respect to the deposition gas containing silicon or germanium is reduced, and the gas containing nitrogen is mixed to suppress crystal growth, so that the amorphous semiconductor layer The buffer layer 113 to be formed can be formed.

Further, in the initial stage of deposition, the first microcrystalline semiconductor layer 109 is used as a seed crystal to deposit a film as a whole. Thereafter, the crystal growth is partially suppressed, and a microcrystalline semiconductor region having a plurality of cone-shaped protrusions (convex portions) grows (mid-deposition stage). Further, the crystal growth of the conical microcrystalline semiconductor region is suppressed, and the buffer layer 113 (late deposition) not including the microcrystalline semiconductor region is formed. Note that the first microcrystalline semiconductor layers 117 a and 153 a described in Embodiments 1 to 3 correspond to the first microcrystalline semiconductor layer 109. In addition, the second microcrystalline semiconductor layers 117b and 153b described in Embodiments 1 to 3 each have a plurality of conical shapes formed in a middle stage of deposition of a film formed in the initial stage of deposition and the second microcrystalline semiconductor layer 111. This corresponds to a microcrystalline semiconductor region having a protrusion (convex portion). In addition, the pair of buffer layers 135 and 171 described in Embodiments 1 to 3 are amorphous semiconductor layers formed in a later stage of deposition, that is, correspond to the buffer layer 113.

In this manner, after the first microcrystalline semiconductor layer 109 is formed, the second microcrystalline semiconductor layer 111 having a plurality of cone-shaped protrusions (convex portions) is controlled by controlling the deposition conditions, and the first The buffer layer 113 can be formed using an amorphous semiconductor layer on the surface of the second microcrystalline semiconductor layer.

The impurity semiconductor layer 115 is formed by glow discharge plasma by mixing a deposition gas containing silicon or germanium, hydrogen, and phosphine (hydrogen dilution or silane dilution) in a reaction chamber of a plasma CVD apparatus. A deposition gas containing silicon or germanium is diluted with hydrogen, and amorphous silicon to which phosphorus is added, microcrystalline silicon to which phosphorus is added, amorphous silicon germanium to which phosphorus is added, and microcrystalline silicon germanium to which phosphorus is added Amorphous germanium to which phosphorus is added is formed as microcrystalline germanium to which phosphorus is added.

Next, a resist is applied over the impurity semiconductor layer 115, exposed using a second photomask, and then developed to form a resist mask.

Next, the first microcrystalline semiconductor layer 109, the second microcrystalline semiconductor layer 111, the buffer layer 113, and the impurity semiconductor layer 115 are etched using the resist mask, so that the first microcrystalline semiconductor layer 117a is etched. The second microcrystalline semiconductor layer 117b, the buffer layer 119, and the impurity semiconductor layer 121 are formed. After that, the resist mask is removed (see FIG. 5C).

Next, a conductive layer 123 is formed to cover the first microcrystalline semiconductor layer 117a, the second microcrystalline semiconductor layer 117b, the buffer layer 119, and the impurity semiconductor layer 121 (see FIG. 5D).

For the conductive layer 123, the material and stacked structure of the conductive layer 123 described in Embodiment 1 can be used as appropriate. The conductive layer 123 is formed by a CVD method, a sputtering method, or a vacuum evaporation method. Alternatively, the conductive layer 123 may be formed by discharging and baking a conductive nanopaste of silver, gold, copper, or the like using a screen printing method, an inkjet method, or the like. Thereafter, a resist mask is formed over the conductive layer 123.

Next, the conductive layer 123 is etched using a resist mask to form wirings 125 and 127 and a capacitor electrode 129 (see FIG. 6A).

The wirings 125 and 127 function as a source electrode and a drain electrode. Etching of the conductive layer 123 is preferably performed by wet etching. The conductive layer is isotropically etched by wet etching. The wirings 125 and 127 function as signal lines as well as source and drain electrodes. However, the present invention is not limited to this, and the signal line and the wirings 125 and 127 may be provided separately.

Next, part of the impurity semiconductor layer 121 is etched using a resist mask. Here, dry etching is used. Up to this step, the impurity semiconductor layer 131 that functions as a source region and a drain region is formed. Note that part of the buffer layer 119 is also etched in this step. The partially etched buffer layer 119 is referred to as a buffer layer 133 (see FIG. 6B). Here, when the conductive layer 123 is wet-etched, the conductive layer recedes inward from the resist mask, and wirings 125 and 127 are formed. Accordingly, the side surfaces of the wirings 125 and 127 do not coincide with the side surfaces of the etched impurity semiconductor layer 131, and the side surfaces of the source region and the drain region are formed outside the side surfaces of the wirings 125 and 127.

Next, the buffer layer 133 is etched to expose the second microcrystalline semiconductor layer 117b and to form a pair of buffer layers 135 (see FIG. 6C). Here, conditions in which the amorphous semiconductor layer which is the buffer layer 133 is selectively etched by wet etching or dry etching to expose the second microcrystalline semiconductor layer 117b are used as appropriate. Typically, etchants for wet etching include hydrazine, dilute hydrofluoric acid (DHF), and the like. As the dry etching, the amorphous semiconductor layer can be selectively etched using hydrogen.

After that, the resist mask is removed, and plasma treatment 140 for oxidizing or nitriding the surface of the second microcrystalline semiconductor layer 117b is performed, so that the insulating layers 136a, 136c, and 136e illustrated in FIG. 1 are formed. Note that the cross-sectional view illustrated in FIG. 6C corresponds to a cross-sectional view along AB in the plan view of the pixel portion illustrated in FIG.

Note that here, after the wirings 125 and 127 are formed, the buffer layer 133 is etched to expose the second microcrystalline semiconductor layer 117b. However, after the wirings 125 and 127 are formed, the resist mask is removed to remove impurities. A plasma treatment 140 may be performed in which part of the semiconductor layer 121 and the buffer layer 119 are dry-etched and the surface of the second microcrystalline semiconductor layer 117b is oxidized or nitrided. In this case, since the impurity semiconductor layer 121 and the buffer layer 119 are etched using the wirings 125 and 127 as a mask, the side surfaces of the wirings 125 and 127 coincide with the side surfaces of the impurity semiconductor layer 131 functioning as a source region and a drain region. It becomes the shape to do.

As described above, after the second microcrystalline semiconductor layer 117b having conical unevenness is exposed, an insulating layer is formed on the surface of the second microcrystalline semiconductor layer 117b by plasma treatment, whereby the source region and the drain are formed. The distance of the leak path between the regions can be increased, and an insulating layer with high insulating properties is formed. Therefore, off current of the thin film transistor can be reduced.

Next, a second gate insulating layer 137 is formed (see FIG. 7A). The second gate insulating layer 137 can be formed in a manner similar to that of the first gate insulating layer 107. Further, the second gate insulating layer 137 is preferably provided using dense silicon nitride so that an impurity element which can be a source of contamination such as an organic substance, metal, or water vapor floating in the air can be prevented.

Next, openings 139 and 141 are formed in the second gate insulating layer 137 so as to reach the wiring 127 and the capacitor electrode 129. The openings 139 and 141 can be formed by etching part of the second gate insulating layer 137 using a resist mask formed by a photolithography method. After that, the pixel electrode 143 is provided over the second gate insulating layer 137 so that the wiring 127 and the capacitor electrode 129 are connected to each other through the openings 139 and 141. In addition, a back gate electrode 145 is formed. In this manner, a switching transistor in the pixel of the display device illustrated in FIG. 7B can be manufactured. A plan view of FIG. 7B at this time is shown in FIG. Note that in this embodiment, the back gate electrode 145 has a shape parallel to the gate electrode 103 and a shape to which a potential different from that of the gate electrode 103 can be applied.

The pixel electrode 143 and the back gate electrode 145 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium It can be formed using zinc oxide, indium tin oxide to which silicon oxide is added, or the like.

The pixel electrode 143 and the back gate electrode 145 may be patterned by etching using a resist mask formed by photolithography as in the case of the wirings 125 and 127 and the like.

The pixel electrode 143 and the back gate electrode 145 can be formed using a conductive composition including a light-transmitting conductive high molecule (also referred to as a conductive polymer). The pixel electrode 143 preferably has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. Examples thereof include polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more of these.

In this embodiment mode, since the back gate electrode 145 can be formed at the same time as the pixel electrode 143, a thin film transistor having a back gate electrode can be manufactured without increasing the number of photomasks.

Although not illustrated, a back gate electrode 145 is formed over the second gate insulating layer 137, and a spin coating method is performed between the second gate insulating layer 137 and the back gate electrode 145 and the pixel electrode 143. You may have the insulating layer which consists of organic resin formed by etc.

Thereafter, in a VA (Vertical Alignment) type liquid crystal display device, in order to expand the viewing angle, a pixel is divided into a plurality of parts, and the orientation of the liquid crystal of each part of the divided pixels is different (so-called so-called). In the case of the MVA method), it is preferable to form a protrusion having a predetermined shape on the pixel electrode 143. The protrusion is formed of an insulating layer.

When protrusions are formed on the pixel electrode, when the pixel electrode voltage is off, the liquid crystal is aligned perpendicular to the alignment film surface, but the liquid crystal near the protrusion is slightly tilted with respect to the substrate surface. Orientation. When the voltage of the pixel electrode is turned on, the liquid crystal in the inclined alignment portion is first inclined. In addition, liquid crystals other than the vicinity of the protrusions are also affected by these liquid crystals and are sequentially arranged in the same direction. As a result, stable orientation can be obtained for the entire pixel. That is, the orientation of the entire display unit is controlled starting from the protrusion.

Further, instead of providing the protrusion on the pixel electrode, a slit may be provided in the pixel electrode. In this case, when a voltage is applied to the pixel electrode, an electric field distortion occurs in the vicinity of the slit, and the electric field distribution and liquid crystal alignment can be controlled in the same manner as when a protrusion is provided on the pixel electrode.

Through the above steps, the threshold voltage can be controlled, and the on-state current is higher than that of a thin film transistor including an amorphous semiconductor in a channel formation region, and the thin film transistor including a microcrystalline semiconductor in a channel formation region In comparison, an element substrate that has a thin film transistor with low off-state current and can be used for a display device can be manufactured.

(Embodiment 5)
In this embodiment, a method for manufacturing the thin film transistor described in Embodiment 2 will be described. In this embodiment mode, a method for manufacturing an n-type thin film transistor will be described.

A gate electrode 103 and a capacitor wiring 105 are formed over the substrate 101.

Next, a first gate insulating layer 107, a first microcrystalline semiconductor layer 109, a second microcrystalline semiconductor layer 111, a buffer layer 113, an impurity semiconductor layer 115, and a conductive layer 123 which cover the gate electrode 103 are formed. . After that, a resist mask 151 is formed over the conductive layer 123 (see FIG. 9A).

The resist mask 151 includes two regions having different thicknesses, and can be formed using a multi-tone mask. It is preferable to use a multi-tone mask because the number of photomasks to be used is reduced and the number of manufacturing steps is reduced. In this embodiment, a step of forming a pattern of the first microcrystalline semiconductor layer 109, the second microcrystalline semiconductor layer 111, the buffer layer 113, and the impurity semiconductor layer 115, and a step of forming a source region and a drain region A multi-tone mask can be used.

A multi-tone mask is a mask that can be exposed with multiple levels of light, and typically, exposure is performed with three levels of light: an exposed area, a half-exposed area, and an unexposed area. By using a multi-tone mask, a resist mask having a plurality of thicknesses (typically two types) can be formed by one exposure and development process. Therefore, the number of photomasks can be reduced by using a multi-tone mask.

13A-1 and 13B-1 are cross-sectional views of typical multi-tone masks. 13A-1 shows a gray tone mask 180, and FIG. 13B-1 shows a halftone mask 185. FIG.

A gray-tone mask 180 illustrated in FIG. 13A-1 includes a light-shielding portion 182 formed using a light-shielding film over a light-transmitting substrate 181 and a diffraction grating portion 183 provided using a pattern of the light-shielding film. ing.

The diffraction grating unit 183 controls the light transmittance by having slits, dots, meshes, or the like provided at intervals equal to or less than the resolution limit of light used for exposure. Note that the slits, dots, or mesh provided in the diffraction grating portion 183 may be periodic or non-periodic.

As the substrate 181 having a light-transmitting property, quartz or the like can be used. The light-shielding film constituting the light-shielding part 182 and the diffraction grating part 183 may be formed using metal, and is preferably provided with chromium, chromium oxide, or the like.

When the graytone mask 180 is irradiated with light for exposure, as shown in FIG. 13A-2, the light transmittance in the region overlapping the light shielding portion 182 becomes 0%, and the light shielding portion 182 or the diffraction grating portion. The transmissivity in the region where 183 is not provided is 100%. Further, the light transmittance in the diffraction grating portion 183 is generally in the range of 10 to 70%, and can be adjusted by the interval of slits, dots or meshes of the diffraction grating.

A halftone mask 185 illustrated in FIG. 13B-1 includes a semi-transparent portion 187 formed of a semi-transparent film over a light-transmitting substrate 186 and a light-shielding portion 188 formed of a light-shielding film. Has been.

The semi-translucent portion 187 can be formed using a film of MoSiN, MoSi, MoSiO, MoSiON, CrSi or the like. The light shielding portion 188 may be formed using the same metal as the light shielding film of the gray tone mask, and is preferably provided with chromium, chromium oxide, or the like.

When light for exposure is applied to the halftone mask 185, the light transmittance in the region overlapping the light shielding portion 188 is 0% as shown in FIG. The light transmittance in the region where the portion 187 is not provided is 100%. The translucency in the semi-translucent portion 187 is approximately in the range of 10 to 70%, and can be adjusted by the type of material to be formed, the film thickness to be formed, or the like.

By performing exposure and development using a multi-tone mask, a resist mask having regions with different thicknesses can be formed.

Next, using the resist mask 151, the first microcrystalline semiconductor layer 109, the second microcrystalline semiconductor layer 111, the buffer layer 113, the impurity semiconductor layer 115, and the conductive layer 123 are etched. Through this step, the first microcrystalline semiconductor layer 109, the second microcrystalline semiconductor layer 111, the buffer layer 113, the impurity semiconductor layer 115, and the conductive layer 123 are separated for each element, and the first microcrystalline semiconductor layer 153a is separated. A second microcrystalline semiconductor layer 153b, a buffer layer 155, an impurity semiconductor layer 157, and a conductive layer 159 are formed (see FIG. 9B).

Next, the resist mask 151 is moved backward to form a resist mask 163. For the receding of the resist mask, ashing using oxygen plasma may be used. Here, the resist mask 151 is ashed so as to be separated on the gate electrode. As a result, the resist mask 163 is separated (see FIG. 10A).

Next, the conductive layer 159 is etched using the resist mask 163 to form wirings 165 and 167 (see FIG. 10B). The wirings 165 and 167 function as a source electrode and a drain electrode. The conductive layer 159 is preferably etched in the same manner as the etching of the conductive layer 123 described in Embodiment 4.

Next, with the second resist mask 163 formed, the impurity semiconductor layer 157 is etched to form an impurity semiconductor layer 168. Note that part of the buffer layer 155 is also etched in this step. The partially etched buffer layer 155 is referred to as a buffer layer 169 (see FIG. 10C).

Next, the buffer layer 169 is etched to expose the second microcrystalline semiconductor layer 153b and to form a pair of buffer layers 171 (see FIG. 11A). Here, conditions in which the amorphous semiconductor layer which is the buffer layer 169 is selectively etched by wet etching or dry etching to expose the second microcrystalline semiconductor layer 153b are used as appropriate. After that, the resist mask is removed, and plasma treatment for oxidizing or nitriding the surface of the second microcrystalline semiconductor layer 153b is performed, so that the insulating layers 154a, 154c, and 154e illustrated in FIG. 3 are formed. Note that the cross-sectional view illustrated in FIG. 11A corresponds to a cross-sectional view taken along a line AB in the plan view of the pixel portion illustrated in FIG.

Note that here, after the wirings 165 and 167 are formed, the buffer layer 169 is etched to expose the second microcrystalline semiconductor layer 153b. However, after the wirings 165 and 167 are formed, the resist mask is removed, and impurities Plasma treatment may be performed in which part of the semiconductor layer 157 and the buffer layer 155 are dry-etched and the surface of the second microcrystalline semiconductor layer 153b is oxidized or nitrided. In this case, since the impurity semiconductor layer 157 and the buffer layer 155 are etched using the wirings 165 and 167 as a mask, the side surfaces of the wirings 165 and 167 coincide with the side surfaces of the impurity semiconductor layer 168 functioning as a source region and a drain region. It becomes a shape.

As described above, after the second microcrystalline semiconductor layer 153b having conical unevenness is exposed, an insulating layer is formed on the surface of the second microcrystalline semiconductor layer 153b by plasma treatment, whereby the source region and the drain are formed. The distance of the leak path between the regions can be increased, and an insulating layer with high insulating properties is formed. Therefore, off current of the thin film transistor can be reduced.

Through the above process, the thin film transistor according to this embodiment can be manufactured. The thin film transistor according to this embodiment can be applied to a switching transistor in a pixel of a display device, similarly to the thin film transistor described in Embodiment 4. Therefore, a second gate insulating layer 137 is formed so as to cover the thin film transistor (see FIG. 11B).

Next, openings 139 and 173 are formed in the second gate insulating layer 137 so as to reach the wiring 167. The openings 139 and 173 can be formed in the same manner as the openings 139 and 141. After that, the pixel electrode 143 is provided over the second gate insulating layer 137 so as to be connected through the openings 139 and 173. In addition, a back gate electrode 145 is formed. In this manner, a switching transistor in the pixel of the display device illustrated in FIG. 11C can be manufactured. A plan view of FIG. 11C at this time is shown in FIG. Note that in this embodiment, the back gate electrode 145 has a shape parallel to the gate electrode 103 and a shape to which a potential different from that of the gate electrode 103 can be applied.

Although not illustrated, a back gate electrode 145 is formed over the second gate insulating layer 137, and a spin coating method is performed between the second gate insulating layer 137 and the back gate electrode 145 and the pixel electrode 143. You may have the insulating layer which consists of organic resin formed by etc.

Thereafter, as in the fifth embodiment, in a VA (Vertical Alignment) liquid crystal display device, a pixel is divided into a plurality of parts in order to increase the viewing angle, and the orientation of the liquid crystal in each part of the divided pixels is changed. In the case of a different multi-domain method (so-called MVA method), it is preferable to form a protrusion on the pixel electrode 143.

Through the above process, the threshold voltage can be controlled with a small number of masks, and the on-state current is higher than that of a thin film transistor including an amorphous semiconductor in a channel formation region. As compared with the thin film transistor included in the above, an element substrate which can finance a thin film transistor having a low off-state current and can be used for a liquid crystal display device can be manufactured.

(Embodiment 6)
In this embodiment, a method for manufacturing a back gate electrode that can be used instead of the back gate electrode of the thin film transistor described in any of Embodiments 4 and 5 is described with reference to FIGS. Note that although this embodiment mode is described using Embodiment Mode 4, Embodiment Mode 5 can be applied as appropriate.

Through the steps similar to those in Embodiment Mode 4 through the steps from FIG. 5 to FIG. 7A, the gate electrode 103 to the second gate insulating layer 137 are formed.

Next, an opening 147 is formed in a region where the gate electrode 103, the first gate insulating layer 107, and the second gate insulating layer 137 are stacked.

Next, as in Embodiment Mode 4, the pixel electrode 143 and the back gate electrode 145 are formed. Here, the back gate electrode 145 is formed so as to be connected to the gate electrode 103 in the opening 147 formed in the first gate insulating layer 107 and the second gate insulating layer 137 (see FIG. 14). Note that a cross-sectional view taken along a line CD in FIG. 14A corresponds to FIG.

Here, since the back gate electrode 145 can be formed at the same time as the pixel electrode, a thin film transistor having a back gate electrode can be manufactured without increasing the number of photomasks compared to a conventional thin film transistor.

In addition, according to this embodiment, a thin film transistor capable of forming a channel on the first gate electrode 103 side and the second back gate electrode 145 side in the microcrystalline semiconductor layer 153 can be manufactured. . That is, a thin film transistor with high on-state current can be manufactured.

(Embodiment 7)
In this embodiment, applicable modes of top shapes of wirings functioning as a source electrode and a drain electrode of the thin film transistor described in any of Embodiments 1 to 6 will be described with reference to FIGS.

The top surface shape of the wirings functioning as the source electrode and the drain electrode of the thin film transistor illustrated in FIG. 8A is a portion facing the impurity semiconductor layer 131, that is, the wiring 125 functioning as one of the source electrode or the drain electrode and the source electrode or the drain. A region where the wiring 127 functioning as the other electrode is opposed is linear.

In addition, the top shape of the thin film transistor illustrated in FIG. 12A is a portion where the impurity semiconductor layer 168 is opposed, that is, a wiring 165 functioning as one of a source electrode or a drain electrode and a wiring 167 functioning as the other of a source electrode or a drain electrode. A region where and are opposed to each other is linear.

As shown in FIG. 15, a first microcrystalline semiconductor layer 117b and a second microcrystalline semiconductor layer 117b are formed over the gate electrode 103 with a first gate insulating layer interposed therebetween. A source region and a drain region are formed over the layer 117b with a pair of buffer layers interposed therebetween. A wiring 195 serving as one of the source electrode and the drain electrode and the other of the source electrode and the drain electrode are formed over the source region and the drain region. A wiring 197 functioning as is formed. In addition, a second gate insulating layer is formed over the second microcrystalline semiconductor layer 117 b and the wirings 195 and 197. In addition, the pixel electrode 199 is connected to the wiring 197 functioning as the other of the source electrode and the drain electrode in the opening of the second gate insulating layer. In addition, a back gate electrode 145 is formed between the wiring 195 that functions as one of the source electrode and the drain electrode and the wiring 197 that functions as the other of the source electrode and the drain electrode over the second gate insulating layer. Is done. In addition, a region where a facing portion of the source region and the drain region, that is, a wiring 195 functioning as one of the source electrode or the drain electrode and a wiring 197 functioning as the other of the source electrode or the drain electrode are opposed to each other, C-shaped. The back gate electrode 145 is U-shaped or C-shaped. In this embodiment mode, the back gate electrode 145 can be formed at the same time as the pixel electrode 199; therefore, the number of photomasks is the same as that of a conventional thin film transistor, and the thin film transistor having the back gate electrode without increasing the number of photomasks. Can be produced.

16A and 16B, the first microcrystalline semiconductor layer 117a and the second microcrystalline semiconductor layer 117b are formed over the gate electrode 103 with the first gate insulating layer 107 interposed therebetween. An impurity semiconductor layer 131 that functions as a source region and a drain region is formed over the second microcrystalline semiconductor layer 117b through a pair of buffer layers 135, and the impurity semiconductor layer 131 that functions as a source region and a drain region is formed. A wiring 175 that functions as one of the source electrode and the drain electrode and a wiring 177 that functions as the other of the source electrode and the drain electrode are formed thereover. In addition, a second gate insulating layer 137 is formed over the wirings 175 and 177, and a back gate electrode 176 is formed over the second gate insulating layer 137. In addition, an insulating layer 178 is formed over the second gate insulating layer 137 and the back gate electrode 176. In addition, the pixel electrode 179 is connected to the wiring 177 functioning as the other of the source electrode and the drain electrode in the openings of the second gate insulating layer 137 and the insulating layer 178. Here, a region where the wiring 175 that functions as one of the source electrode and the drain electrode and the wiring 177 that functions as the other of the source electrode and the drain electrode are opposed to each other.

As shown in FIGS. 15 and 16, the region where the wiring functioning as one of the source electrode or the drain electrode and the wiring functioning as the other of the source electrode or the drain electrode are in an annular shape, a U shape, or a C shape. 8A and 12A, the channel width can be increased as compared with the thin film transistor having the shape illustrated in FIGS. 8A and 12A, so that the area occupied by the thin film transistor can be reduced and the thin film transistor can be turned on. It is possible to increase the current. In addition, when the thin film transistor having the shape is used as a switching element of a display element, the aperture ratio in the pixel can be increased.

Claims (8)

A gate electrode;
A first gate insulating layer in contact with the gate electrode;
A microcrystalline semiconductor layer in contact with the first gate insulating layer;
A pair of buffer layers in contact with the microcrystalline semiconductor layer; a pair of impurity semiconductor layers formed over the pair of buffer layers;
A wiring formed over the pair of impurity semiconductor layers; a second gate insulating layer formed over the microcrystalline semiconductor layer and the wiring;
A thin film transistor including a back gate electrode formed over the second gate insulating layer, wherein a surface of the microcrystalline semiconductor layer in contact with the pair of buffer layers is uneven.   2. The thin film transistor according to claim 1, wherein the gate electrode, the first gate insulating layer, the microcrystalline semiconductor layer, the second gate electrode, and the back gate electrode overlap with each other.   3. The thin film transistor according to claim 1, wherein the microcrystalline semiconductor layer is in contact with the insulating layer in a region which is in contact with the pair of buffer layers and is not in contact with the pair of buffer layers. A gate electrode;
A first gate insulating layer formed on the gate electrode;
A first microcrystalline semiconductor layer formed over the first gate insulating layer;
A second microcrystalline semiconductor layer having a plurality of cone-shaped protrusions formed on the first microcrystalline semiconductor layer;
A pair of buffer layers formed over the second microcrystalline semiconductor layer; a pair of impurity semiconductor layers formed over the pair of buffer layers;
Wiring formed on the pair of impurity semiconductor layers;
A second gate insulating layer formed over the second microcrystalline semiconductor layer and the wiring;
A thin film transistor comprising a back gate electrode formed on the second gate insulating layer.   5. The gate electrode, the first gate insulating layer, the first microcrystalline semiconductor layer, the second microcrystalline semiconductor layer, the second gate electrode, and the back gate electrode overlap with each other. A thin film transistor.   6. The second microcrystalline semiconductor layer according to claim 4, wherein one surface of the second microcrystalline semiconductor layer is in contact with the first microcrystalline semiconductor layer and the other surface is an insulating layer in a region not in contact with the pair of buffer layers. A thin film transistor which is in contact with each other.   7. The thin film transistor according to claim 1, further comprising a microcrystalline semiconductor layer between the pair of buffer layers and the pair of impurity semiconductor layers.   8. The thin film transistor according to claim 1, wherein the buffer layer is formed using an amorphous semiconductor layer. 9.

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