JP2010123830A5 - - Google Patents

Claims (10)

A core substrate comprising an insulating layer having a plurality of first vias formed of a conductive paste filled in via holes, and a wiring pattern formed on the insulating layer;
A build-up layer formed on the surface layer of the core substrate;
A wiring pattern formed on the surface layer of the build-up layer;
A second via formed in the build-up layer,
The conductive paste is composed of conductive particles having different particle size ranges and a binder mainly composed of a thermosetting resin,
At least one of the plurality of first vias is formed with the second via immediately above,
The printed wiring board, wherein a contact interface between the first via and the second via is connected without a binder in the conductive paste. The printed wiring according to claim 1, wherein the contact interface between the first via and the second via is in contact with the second via and conductive particles in the conductive paste. Board. The contact interface between the first via and the second via has irregularities, and the irregular surface has an interface shape formed due to the shape of the conductive particles of the conductive paste. The printed wiring board according to claim 2. The conductive particles having different particle size ranges are composed of conductive particles having a particle size range of at least 0.2 to 10 μm and conductive particles having a particle size range of 0.6 to 20 μm. The printed wiring board according to 1. The printed wiring board according to claim 1, wherein a wiring pattern formed on the insulating layer of the core substrate is formed on the insulating layer except for a region on the first via. The printed wiring board according to claim 5, wherein the region on the first via is a region including a center of the via and not less than ½ of the diameter of the first via. Forming a via hole in the insulating layer;
Forming a first via filled with a conductive paste in the via hole;
Preparing a core substrate having a first via with a surface exposed by forming a wiring pattern in the insulating layer except for a region on the first via;
Laminating a build-up layer on the core substrate including the wiring pattern;
Forming a via hole in the build-up layer including immediately above the first via;
Forming a second via in the via hole of the build-up layer;
And a step of forming a wiring pattern on the surface layer of the build-up layer,
The conductive paste is composed of conductive particles having different particle size ranges and a binder mainly composed of a thermosetting resin,
The printed wiring board manufacturing method, wherein the binder in the conductive paste is removed from the surface of the first via in the step of preparing the core substrate or the step of forming a via hole in the build-up layer. . The conductive particles having different particle size ranges are composed of conductive particles having a particle size range of at least 0.2 to 10 μm and conductive particles having a particle size range of 0.6 to 20 μm. A method for producing a printed wiring board according to claim 7. A part of the conductive particles is removed at the same time as the binder in the conductive paste is removed, and the conductive particles in the particle size range of 0.2 to 10 μm have a particle size of 0.6 to 20 μm. The method for producing a printed wiring board according to claim 7, wherein more conductive particles in a range are removed. 8. The step of forming a via hole including directly above the first via of the buildup layer includes a step of treating the inside of the via hole and the surface of the first via with an oxidizing agent. Manufacturing method of printed wiring board.