JP2010123730A - Semiconductor device and evaluation method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To acquire with precision trimming information required for fine adjusting a circuit characteristics of a semiconductor device, and to prevent measurement time from prolonged. <P>SOLUTION: The semiconductor device includes a plurality of evaluated elements (TEG) 2, a monitoring element 4 for monitoring a current value or voltage value applied to the plurality of evaluated elements 2 respectively, a plurality of first electrode pads 1 connected to respective one ends of the plurality of evaluated elements 2, and a second electrode pad 3 connected to one end of the monitoring element 4. The respective other ends of the plurality of evaluated elements 2 are connected to the other end of the monitoring element 4 in common. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and an evaluation method thereof, and more particularly to a trimming method of a semiconductor device, a semiconductor device therefor, and an evaluation method thereof.

  In recent years, in an analog circuit or the like, it has become necessary to accurately control an input voltage value or an input current value in order to achieve high accuracy of an output current value. For example, even if an external input can be input with high accuracy, if the resistance value of a semiconductor element, such as a resistor, that constitutes an analog circuit that transmits to an analog element deviates from a reference value, A value deviated from the value is input, and as a result, a value deviated from the expected value is output as the output value.

  In order to solve these problems, trimming technology is introduced in analog circuits and the like. Trimming is a method of adjusting the electrical characteristics of a circuit after forming a semiconductor element in order to input a desired voltage value or a desired current value to an analog circuit.

As the trimming technique, there are the following two techniques.
1) In the zener zap trimming method, two types of zener diodes are formed, and ON (with breakdown current) / OFF (without breakdown current) is controlled by flowing a current of a predetermined current or more. This is a technique for finely adjusting the electrical characteristics of the circuit by controlling these to change the combined resistance.
2) The laser trimming method is a technique for finely adjusting the electrical characteristics of a circuit by processing the shape of the resistor with laser light and changing the resistance value.

  By the way, information necessary for trimming when finely adjusting the electrical characteristics of the circuit is collected by actually inspecting an analog circuit using a tester before trimming. Subsequently, trimming is performed based on the previously obtained inspection result, and further, an inspection similar to the inspection performed before the trimming is executed by the tester to acquire the electrical characteristics of the circuit (for example, see Patent Document 1). reference.).

  In addition, in order to monitor the formation state (performance) of the diffusion process as an electrical characteristic, an assembly of single elements (TEG: Test Element Group) such as a transistor, a capacitor element, or a resistor is formed on the wafer in advance. Yes.

  Therefore, as shown in FIG. 6, after completion of the wafer, these TEGs are measured to confirm the quality of the process. Subsequently, as described above, for each wafer that has been determined to be acceptable due to the quality of the process, an inspection using a tester is performed on each chip in order to obtain trimming information for fine adjustment of the trimming circuit. . Subsequently, the trimming circuit formed in each chip is finely adjusted with the value calculated based on the test result by the tester as trimming information. Thereafter, the same test as before trimming is performed again by the tester to determine whether or not the analog circuit performs a desired function, that is, whether or not the chip including the analog characteristics is acceptable.

However, in the above procedure, inspection by two testers is required, and the cost in the inspection process increases. Therefore, as shown in FIG. 7, a procedure for applying the result obtained from the measurement result for monitoring the quality of the diffusion process and the measurement result of the PCM (process control module) / TEG to the trimming information is also employed. By this method, a deviation from a desired electrical characteristic is obtained from the measurement result of PCM / TEG, and laser processing is performed on a trimming circuit arranged in advance in order to correct this deviation.
Japanese Unexamined Patent Publication No. Sho 61-272916

  However, the above prior art applies the measurement result by the tester or the measurement result of the TEG to the trimming information, and when the TEG measurement result is reflected in the trimming, the plurality of transistors are arrayed and the transistor characteristics are averaged The converted result is applied to the trimming information. For this reason, if there is a singular point among a plurality of transistor characteristics, the trimming information deviates from the true value due to the influence of this singular point, and fine adjustment of the analog circuit, which is the original purpose of trimming technology, is performed Therefore, there is a problem that it is impossible to obtain desired characteristics.

  Also, in order to avoid averaging the transistor characteristics, it is possible to measure with the number of measurement transistors, although it is possible to achieve high accuracy by measuring with multiple transistors mounted on them and using them as trimming information. There is a problem that the measurement time is increased and the inspection cost is increased.

  Further, in today's large-diameter wafers, it is necessary to further increase the number of trimming measurement points, and in order to obtain highly accurate trimming information even in large-diameter wafers, the time required for measurement is greatly reduced. It becomes a problem.

  In view of the above-described conventional problems, an object of the present invention is to obtain trimming information necessary for fine adjustment of circuit characteristics of a semiconductor device with high accuracy and to prevent an increase in measurement time.

  In order to achieve the above object, the present invention provides a semiconductor device comprising: a plurality of elements to be evaluated; and a monitoring element that monitors a current value or a voltage value applied to each of the plurality of elements to be evaluated. A plurality of first electrode pads connected to one end of each of the plurality of elements to be evaluated; and a second electrode pad connected to one end of the monitoring element, and the other end of each of the plurality of elements to be evaluated. Is commonly connected to the other end of the monitoring element.

  According to the semiconductor device of the present invention, the other end of each of the plurality of elements to be evaluated is connected in common with the other end of the monitoring element. Therefore, even if the number of elements to be evaluated is increased, the measurement time is increased. Can be suppressed.

  The semiconductor device according to the present invention includes a third electrode pad commonly connected to the other end of each of the plurality of elements to be evaluated, between the other end of each of the plurality of elements to be evaluated and the other end of the monitoring element. Is preferably further provided.

  In this case, the Kelvin measurement method can be performed by using the first electrode pad, the second electrode pad, the third electrode pad, and the terminal for applying current or voltage, so that the measurement accuracy is improved.

  In the semiconductor device of the present invention, the monitoring element is preferably a resistor.

  In the semiconductor device of the present invention, the plurality of elements to be evaluated are preferably resistors, transistors, or capacitors.

  A first semiconductor device evaluation method using a semiconductor device according to the present invention selects one of a plurality of first electrode pads, and selects between the selected electrode pad and the second electrode pad. A step (a) of applying a current or voltage, a step (b) of measuring a current value flowing through the monitoring element or a voltage value applied to the monitoring element when the current or voltage is applied, and a step (a) And the step (b) are sequentially performed on the plurality of first electrode pads to obtain measurement data for each of the plurality of elements to be evaluated, and the plurality of steps acquired in the step (c). By comparing the measurement data with each other and calculating the maximum value and the minimum value of the plurality of measurement data, the step (d) and the step (d) of removing the maximum value and the minimum value from the measurement data are repeated. Calculate the average value of the multiple measurement data obtained in (c) Characterized in that it comprises a step (e).

  According to the first semiconductor device evaluation method, after calculating the maximum value and the minimum value of a plurality of measurement data, the maximum value and the minimum value are removed from the measurement data, and this is repeated for all the measurement data. An average value of a plurality of measurement data is calculated. In this way, by eliminating the data with unique characteristics and averaging only the data with highly uniform characteristics as trimming information, the influence of singular points can be eliminated, so the trimming information can be increased. It can be obtained with accuracy.

The semiconductor device according to the present invention, the second semiconductor device evaluation method further comprising a third electrode pad connected in common with the other ends of the plurality of elements to be evaluated includes the plurality of first elements. Selecting one of the electrode pads, applying a current or voltage between the selected electrode pad and the second electrode pad (a), and applying the current or voltage to A step (b) of measuring a flowing current value or a voltage value applied to the monitoring element between the second electrode pad and the third electrode pad, a plurality of steps (a) and (b) The first electrode pad is sequentially performed, and the step (c) of acquiring measurement data for each of the plurality of elements to be evaluated is compared with the plurality of measurement data acquired in the step (c). After calculating the maximum and minimum values of multiple measurement data, A step (d) for removing the minimum value from the measurement data, and a step (e) for calculating an average value of the plurality of measurement data obtained in the step (c) by repeating the step (d). According to the second method for evaluating a semiconductor device, after calculating the maximum value and the minimum value of a plurality of measurement data, the maximum value and the minimum value are excluded from the measurement data, By repeating, the average value of a plurality of measurement data is calculated. In this way, by eliminating the data with unique characteristics and averaging only the data with highly uniform characteristics as trimming information, the influence of singular points can be eliminated, so the trimming information can be increased. It can be obtained with accuracy.

  In the first or second semiconductor device evaluation method, the monitoring element is preferably a resistor.

  In the first or second semiconductor device evaluation method, the plurality of elements to be evaluated are preferably resistors, transistors, or capacitors.

  According to the semiconductor device and the evaluation method thereof of the present invention, it is possible to realize high precision trimming information necessary for fine adjustment of circuit characteristics of the semiconductor device, and increase the number of elements to be measured to obtain trimming information. Even so, it is possible to suppress the increase in the measurement time and the inspection cost.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows an equivalent circuit of a semiconductor device according to the first embodiment of the present invention.

  As shown in FIG. 1, the semiconductor device according to the first embodiment includes a plurality of first electrode pads 1, a plurality of TEGs 2 each connected to each first electrode pad 1, and one end The monitoring element 4 is connected to the other end of each TEG 2, and the second electrode pad 3 is connected to the other end of the monitoring element 4. The acquisition target of the trimming parameter information is TEG2.

  The trimming parameter information acquisition method in the first embodiment will be described below.

  First, in order to obtain variation information of the TEG 2, a predetermined potential, 20 mV in this case, is applied to the first electrode pad 1 and the second electrode pad 3 in order from the leftmost TEG 2 in FIG. And a measured value monitored between the second electrode pad 3 and the second electrode pad 3. Each measurement value obtained here is a variation occurring in a plurality of TEGs 2.

  As an example, TEG2 that requires trimming information is assumed to be a resistor, and monitoring element 4 is also assumed to be a resistor. One end of a resistor that is a TEG 2 is connected to the first electrode pad 1. By applying a current of 10 mA to the desired first electrode pad 1, one resistor of the plurality of TEGs 2 is selected, and by applying 0 V to the second electrode pad 3, the desired first electrode pad 1 is selected. A voltage when the resistor of the TEG 2 and the resistor of the monitoring element are connected in series is detected between the first electrode pad 1 and the second electrode pad 3.

  Here, a method of detecting a current between the first electrode pad 1 and the second electrode pad 3 by applying a voltage instead of a current to the first electrode pad 1 is also possible. It is possible to detect a difference in resistance value of each TEG2.

  However, there is a great difference between the two measurement methods in terms of measurement time and thus inspection costs. Specifically, the measurement time can be shortened by applying a current to the first electrode pad 1 and detecting the voltage between the first electrode pad 1 and the second electrode pad 3. When detecting the current by comparing the time required to stabilize the measurement result with the required waiting time as a parameter when detecting the current by applying a voltage and when detecting the voltage by applying the current Is stable at 0.05 seconds, and when voltage is detected, the result is substantially stabilized at 0 seconds. This difference does not become a large difference when the number of measurement points is small, but the measurement time difference of approximately 0.05 seconds is accumulated in the measurement with the circuit for the purpose of obtaining variation information, so that the inspection cost is reduced. Then, it is preferable to detect the voltage by applying a current.

  Further, assuming that the resistance value R of the TEG 2 fluctuates by 0.1Ω, the variation sensitivity is as follows.

  For example, assuming that the resistance value R of the TEG 2 is 1Ω, assuming that the resistance value R of the TEG 2 fluctuates by 0.1Ω to become 1.1Ω, it is detected by setting the resistance value of the monitoring element 4. The fact that the fluctuation rates are different will be described below.

  First, when the resistance of the monitoring element 4 is 1Ω, the voltage drop when a current of 10 mA is applied between the TEG 2 and the monitoring element 4 is 22 mV, and the fluctuation is compared with the voltage drop of 20 mV when there is no fluctuation. The rate is 10%.

  On the other hand, when the resistance of the monitoring element 4 is 0.1Ω, the voltage drop when a current of 10 mA is applied between the TEG 2 and the monitoring element 4 is 12 mV, compared with the voltage drop of 11 mV when there is no fluctuation. The rate of change is 9%.

  Therefore, it is desirable that the resistance value of the monitoring element 4 is set, that is, optimized so that the resistance variation sensitivity of the TEG 2 is maximized.

(Semiconductor device evaluation method)
Hereinafter, an evaluation method using the semiconductor device according to the first embodiment will be described with reference to the drawings.

  FIG. 2 schematically shows a TEG selected by the semiconductor device evaluation method according to the first embodiment. This evaluation method is a method for efficiently obtaining a median value of element characteristic distributions that are true values by eliminating singular points that are out of the average of element characteristic distributions among trimming parameter information acquired from a plurality of TEGs 2. .

  Here, as an example, a method for obtaining the median resistance value of the eight resistors shown in the first embodiment will be described.

  First, as shown in FIG. 2, a group of eight resistors R1 to R8 is divided into two groups of four. In each divided group, one resistor is selected as described above, and the voltage between the first electrode pad 1 of the selected resistor and the second electrode pad 3 which is a common terminal is selected. The detection is repeated four times at a time, and the detected voltage values of the four resistors are compared with each other, and two resistors, ie, the resistor showing the maximum value and the resistor showing the minimum value are excluded.

  For example, in FIG. 2, the resistor R3 indicating the maximum value and the resistor R2 indicating the minimum value are excluded from the group of resistors R1 to R4. Further, in the group of resistors R5 to R8, the resistor R5 indicating the maximum value and the resistor R8 indicating the minimum value are excluded. As a result, four resistors R1, R4, R6, and R7 are excluded from the exclusion targets. For these four resistors, the same measurement is performed again, the measured values are compared, and the resistor R7 having the maximum detected voltage and the resistor R1 having the minimum detected voltage are excluded. To do. The arithmetic mean of the remaining resistors R4 and R6 finally becomes the median value of these eight resistors R1 to R8.

  Thus, when the eight resistors are grouped and compared as described above and the median is obtained by repeating the selection, the comparison is completed in 18 comparison steps. However, in the method of obtaining the median value by comparing the eight resistors without grouping them, the required comparison process is 28 times. Therefore, according to this embodiment, the number of measurements, in other words, the measurement time is shortened.

  As described above, by using the semiconductor device evaluation method according to the first embodiment, the number of comparisons in the comparison process can be reduced as compared with the case of using the conventional semiconductor device evaluation method. You can save time.

  Further, by repeatedly excluding the resistors having the maximum and minimum electrical characteristics in the TEG 2 to be measured, that is, the peculiar characteristics, the trimming information averaged only by the resistors having the high uniformity characteristics is obtained. obtain. This can solve the problem that the trimming information cannot be obtained due to the fact that the trimming information deviates from the true value due to the influence of the singular point when fine-tuning the analog circuit. Can be acquired.

  In actual measurement, the number of elements to be compared is increased from several levels in the chip to a predetermined area in the wafer or the entire wafer level, and further to a level over a plurality of wafers. Therefore, as the number of elements to be compared increases, the difference in the number of comparison steps between the semiconductor device evaluation method according to the present embodiment and the conventional semiconductor device evaluation method increases, and thus the semiconductor device according to the present embodiment. The effect of shortening the measurement time by this evaluation method is also increased accordingly.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 3 shows an equivalent circuit of a semiconductor device according to the second embodiment of the present invention.

  As shown in FIG. 3, the semiconductor device according to the second embodiment includes a plurality of TEGs 2 and monitoring elements 4 as in the first embodiment.

  The difference from the first embodiment is that a third electrode pad 5 common to the plurality of TEGs 2 is connected between the plurality of TEGs 2 connected in parallel and one monitoring element 4. is there. Here, the third electrode pad 5 is provided at one end of the monitoring element 4, the second electrode pad 3 is connected to the other end of the monitoring element 4, and the second electrode pad 3 and the monitoring element 4 are connected to each other. Wiring so that the resistance between them is as close to 0Ω as possible. In addition, although not shown in the drawing, one second electrode pad 3 may be added to obtain two.

  The trimming parameter information acquisition method in the second embodiment will be described below.

  First, in order to obtain variation information of the TEG 2, a predetermined potential is applied to the first electrode pad 1 and the second electrode pad 3 in order from the leftmost TEG 2 in FIG. The measured value monitored with the electrode pad 5 is acquired. Each value obtained here is a variation occurring in a plurality of TEGs 2.

  As an example, TEG2 that requires trimming information is a transistor (field effect transistor), and monitor element 4 is a resistor. A gate terminal of a transistor is connected to the first electrode pad 1, and a source terminal, a substrate terminal, and a drain terminal are connected to each transistor as a common pad. As another connection mode, the drain terminal of the transistor may be connected to the first electrode pad 1, and the source terminal, the substrate terminal, and the gate terminal may be connected to each transistor as a common pad.

  One desired transistor of the plurality of TEGs 2 is selected, a gate voltage Vg = 1.2V at which the transistor is turned on is applied to the first electrode pad 1, and a drain voltage Vd = 1.2V is applied to the drain terminal. In addition, 0 V is applied to the second electrode pad 3. Thereby, the on-resistance of the transistor and the resistance of the monitoring element 4 are connected in series between the second electrode pad 3 and the third electrode pad 5. Therefore, the current variation flowing through the transistor TEG2 can be monitored as the voltage variation between the second electrode pad 3 and the third electrode pad 5. Here, Kelvin measurement (four-terminal measurement) can be performed by setting the resistance value between the second electrode pad 3 and the monitoring element 4 to be as close as possible to 0Ω. In this way, the voltage applied to both ends of the monitoring element 4 without being affected by the wiring resistance between the first electrode pad 1 and the TEG 2 and the wiring resistance between the TEG 2 and the monitoring element 4. Since the difference can be measured, the measurement accuracy is further improved.

  When two second electrode pads 3 are provided, the measurement accuracy can be improved even if Kelvin measurement for monitoring the voltage is performed with one of the second electrode pads and the third electrode pad 5. It becomes possible.

  Here, the advantage of monitoring the voltage is the same as the reason described in the first embodiment.

  Similarly to the description in the first embodiment, the variation in the current flowing through the transistor TEG2 is a change in resistance in the monitoring element 4, that is, the potential difference between the second electrode pad 3 and the third electrode pad 5. Therefore, it is necessary to optimize the resistance value of the monitoring element 4 so that it can be detected with high sensitivity.

  Furthermore, in the second embodiment, there is a point to be noted in the arrangement of a plurality of TEGs 2. FIG. 4 shows a planar configuration of the semiconductor device according to the second embodiment. FIG. 4 is a circuit for detecting characteristic variations of the eight TEGs 2, and the specific circuit configuration is as described in FIG.

  Here, the voltage variation between the second electrode pad 3 and the third electrode pad 5 is monitored. Therefore, it is necessary to make the resistance values of the lead wirings 6A to 6H between the TEGs 2 and the third electrode pads 5 equal to each other, which cause variations in resistance values. This is because if the resistance values of the routing wirings 6A to 6H are different, they are detected as variations in TEG2.

  The TEG2 has been described as a resistor in the first embodiment and a transistor in the second embodiment. However, the TEG2 may be a capacitive element. In this case, it is possible to detect variations in the TEG 2 as the capacitive element by monitoring the potential difference caused by the current flowing through the monitoring element 4 when the accumulated current is discharged.

  In either case, in order to improve the detection sensitivity of the TEG 2, the resistance value of the monitoring element 4 is detected so that the potential difference between the second electrode pad 3 and the third electrode pad 5 can be detected with high sensitivity. In addition, it is necessary to equalize the resistance values of the routing wirings 6A to 6H between the TEGs 2 and the third electrode pads 5.

(Semiconductor device evaluation method)
Hereinafter, an evaluation method using the semiconductor device according to the second embodiment will be described with reference to the drawings.

  FIG. 5 schematically shows a TEG selected by the semiconductor device evaluation method according to the second embodiment. This evaluation method is a method for efficiently obtaining a median value of element characteristic distributions that are true values by eliminating singular points that are out of the average of element characteristic distributions among trimming parameter information acquired from a plurality of TEGs 2. .

  Here, as an example, a method for obtaining the median value of the transistor characteristics of the eight transistors shown in the second embodiment will be described.

  First, as shown in FIG. 5, a group of eight transistors Tr1 to Tr8 is divided into two groups of four. In each of the divided groups, one transistor is selected as described above, and the detection of the voltage across the monitoring element 4 is repeated four times at a time, and the voltage values of the four transistors detected are determined. In comparison with each other, two transistors, the transistor showing the maximum value and the transistor showing the minimum value, are excluded.

  For example, in FIG. 5, in the group of transistors Tr1 to Tr4, the transistor Tr3 indicating the maximum value and the transistor Tr2 indicating the minimum value are excluded. In the group of transistors Tr5 to Tr8, the transistor Tr5 indicating the maximum value and the transistor Tr8 indicating the minimum value are excluded. As a result, four transistors Tr1, Tr4, Tr6, and Tr7 are excluded from the exclusion targets. For these four transistors, the same measurement is performed again, the measured values are compared, and the transistors Tr7 having the maximum detected voltage and the transistor Tr1 having the minimum detected voltage are excluded. The arithmetic average of the remaining transistors Tr4 and Tr6 is the median value of these eight transistors Tr1 to Tr8.

  Also in the second embodiment, as in the first embodiment, when the median is obtained by grouping and comparing eight transistors as described above and repeating the selection, the comparison is completed in 18 comparison steps. To do. However, in the method of obtaining the median value by comparing each of the eight transistors without grouping them, the required comparison process is 28 times. Therefore, according to this embodiment, the number of measurements, in other words, the measurement time is shortened.

  As described above, by using the semiconductor device evaluation method according to the second embodiment, the number of comparisons in the comparison process can be reduced as compared with the case of using the conventional semiconductor device evaluation method. You can save time.

  Further, trimming information is obtained by averaging only the transistors having high uniformity characteristics by repeatedly excluding the transistors having the maximum and minimum electrical characteristics in the TEG 2 to be measured, that is, the transistors having unique characteristics. This can solve the problem that the trimming information cannot be obtained due to the fact that the trimming information deviates from the true value due to the influence of the singular point when fine-tuning the analog circuit. Can be acquired.

  In actual measurement, the number of elements to be compared is increased from several levels in the chip to a predetermined area in the wafer or the entire wafer level, and further to a level over a plurality of wafers. Therefore, as the number of elements to be compared increases, the difference in the number of comparison steps between the semiconductor device evaluation method according to the present embodiment and the conventional semiconductor device evaluation method increases, and thus the semiconductor device according to the present embodiment. The effect of shortening the measurement time by this evaluation method is also increased accordingly.

  Note that the semiconductor device according to the first and second embodiments may be formed in the scribe region of the wafer, may be formed in the chip formation region of the wafer, and can be applied at any formation position. It is.

  In the first and second embodiments, the analog circuit has been described as a measurement target. However, the present invention is not limited to this, and for example, a redundant circuit can be applied as a measurement target.

  The semiconductor device and the evaluation method thereof according to the present invention can acquire trimming information necessary for fine adjustment of circuit characteristics of the semiconductor device with high accuracy, and can avoid an increase in measurement time leading to an increase in inspection cost. Further, even if the number of measurement points increases, it is possible to avoid an increase in measurement time, which is particularly useful for fine adjustment of circuit characteristics of an analog circuit.

1 is an equivalent circuit showing a semiconductor device according to a first embodiment of the present invention. It is explanatory drawing which shows typically the evaluation method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is an equivalent circuit which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a top view which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. It is explanatory drawing which shows typically the evaluation method of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 5 is a diagram showing a basic flow for obtaining trimming information from a tester inspection, which is a first conventional example. It is a 2nd prior art example, and is the figure which showed the basic flow for acquiring trimming information from PCM / TEG measurement.

Explanation of symbols

1 First electrode pad 2 TEG (resistance, transistor)
3 Second electrode pad 4 Element 5 for monitoring Third electrode pads 6A to 6H

Claims (8)

A plurality of elements to be evaluated;
A monitoring element for monitoring a current value or a voltage value applied to each of the plurality of elements to be evaluated;
A plurality of first electrode pads each connected to one end of each of the plurality of elements to be evaluated;
A second electrode pad connected to one end of the monitoring element;
The other end of each of the plurality of elements to be evaluated is connected in common with the other end of the monitoring element.   A third electrode pad connected in common with the other end of each of the plurality of elements to be evaluated is further provided between the other end of each of the plurality of elements to be evaluated and the other end of the monitoring element. The semiconductor device according to claim 1, wherein:   The semiconductor device according to claim 1, wherein the monitoring element is a resistor.   The semiconductor device according to claim 1, wherein the plurality of elements to be evaluated are resistors, transistors, or capacitors. A method for evaluating a semiconductor device using the semiconductor device according to claim 1,
Selecting one of the plurality of first electrode pads and applying a current or voltage between the selected electrode pad and the second electrode pad (a);
(B) measuring the current value flowing through the monitoring element or the voltage value applied to the monitoring element when the current or voltage is applied;
(C) performing the step (a) and the step (b) sequentially on the plurality of first electrode pads to obtain measurement data for each of the plurality of elements to be evaluated;
A step of comparing the plurality of measurement data acquired in the step (c) with each other and calculating the maximum value and the minimum value of the plurality of measurement data, and then removing the maximum value and the minimum value from the measurement data (d )When,
A step (e) of calculating an average value of a plurality of measurement data obtained in the step (c) by repeating the step (d), and a method for evaluating a semiconductor device. A method for evaluating a semiconductor device using the semiconductor device according to claim 2,
Selecting one of the plurality of first electrode pads and applying a current or voltage between the selected electrode pad and the second electrode pad (a);
A step of measuring a current value flowing through the monitoring element or a voltage value applied to the monitoring element between the second electrode pad and the third electrode pad by applying the current or voltage. (B) and
(C) performing the step (a) and the step (b) sequentially on the plurality of first electrode pads to obtain measurement data for each of the plurality of elements to be evaluated;
A step of comparing the plurality of measurement data acquired in the step (c) with each other and calculating the maximum value and the minimum value of the plurality of measurement data, and then removing the maximum value and the minimum value from the measurement data (d )When,
A step (e) of calculating an average value of a plurality of measurement data obtained in the step (c) by repeating the step (d), and a method for evaluating a semiconductor device.   The semiconductor device evaluation method according to claim 5, wherein the monitoring element is a resistor.   The semiconductor device evaluation method according to claim 5, wherein the plurality of elements to be evaluated are resistors, transistors, or capacitors.

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