JP2010118368A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To change characteristics of a power supply switch, even after manufacture. <P>SOLUTION: A semiconductor integrated circuit 1 has a plurality of power supply switches 5 for switching connection between a plurality of power supply lines 2 and 3. At least any one of the power supply switches 5 has: a transistor 40 connected between the plurality of power supply lines 2, 3; a set value storing section 42 for holding a set value; and a selecting section 41 for selecting a connection control signal for switching the connection state of the transistor 40 based on the set value from among a plurality of control signals. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a power switch that switches connections between a plurality of power lines, and more particularly to a technique for preventing a rush current that occurs when a power switch is turned on.

  In recent years, the miniaturization of semiconductor integrated circuits has progressed, and the influence of leakage current on circuits has become greater than before. Patent Document 1 discloses a configuration aiming to reduce this leakage current. In this configuration, a power switch is provided between the power supply lines arranged in the circuit so that the power supply to the circuit connected to the power supply line can be appropriately cut off. As long as there is an electrical supply to the circuit including the transistor, the leakage current is not completely eliminated. However, the leakage current can be prevented by cutting off the electrical supply to the circuit (transistor) in this way.

However, when the power switch as described above is switched from OFF to ON, a rush current may occur in the circuit. This rush current has various adverse effects such as device damage and contact melting. Patent Document 2 discloses a configuration aimed at preventing such a rush current. This configuration is intended to suppress the rush current by shifting the timing of turning on the power switch installed for each area divided on the board so that the amount of current in the entire circuit increases stepwise. It is.
JP 2008-66740 A US2007 / 0103202A1

  When manufacturing a circuit as disclosed in Patent Document 2, a simulation is performed in advance, and the arrangement and wiring of the power switch are performed based on the result. In other words, on the board, areas that require a large amount of current, areas that require a small amount of current, areas that require constant connection, etc. are predicted in advance, and the power supply is gradually increased from areas with a small amount of current to areas with a large amount of current. Transistor selection, circuit logic configuration, wiring, and the like are performed so that the transistors are turned on. However, an error often occurs between a predicted value by simulation and an actually measured value of a manufactured product. For this reason, it may be necessary to change the printed wiring after manufacturing.

  The present invention for solving the above-described problems is a semiconductor integrated circuit having a plurality of power switches for switching connections between a plurality of power supply lines, and at least one of the power switches is connected between the plurality of power supply lines. A set value holding unit for holding a set value, and a selection unit for selecting a connection control signal for switching the connection state of the transistor from a plurality of control signals based on the set value. is there.

  According to this configuration, the selection control unit determines the connection control signal for switching the connection state of the transistor based on the setting value held by the setting value holding unit. Therefore, the connection control signal can be changed by changing the setting value held in the setting value holding unit. As a result, the characteristics of the power switch can be changed even after the semiconductor integrated circuit is manufactured.

  According to the present invention, the characteristics of the power switch can be changed even after the semiconductor integrated circuit is manufactured. As a result, even when there is an error between the predicted value and the actual measurement value by simulation or the like, the rush current can be surely prevented without replacing the transistor or changing the printed wiring. Further, the setting of the power switch can be changed for each user or for each application of the semiconductor integrated circuit.

Embodiment 1 of the Invention
Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a part of the configuration of the semiconductor integrated circuit 1 according to the present embodiment. The semiconductor integrated circuit 1 includes a first power line 2, a second power line 3, a power switch 5, a signal generator 6, and a memory 7.

  The first power supply line 2 is connected to a predetermined power supply device, and is always in a state of supplying a power supply voltage (VDD) during operation. The second power supply line 3 can be supplied with VDD when the power switch 5 is turned on.

  In FIG. 2, the connection relationship among the first and second power supply lines 2 and 3, the power switch 5, the third power supply line 4, and the functional circuit 8 is schematically shown. The third power supply line 4 is connected to GND or the like. The functional circuit 8 is an arbitrary circuit that provides various functions. The power switch 5 is connected to the first power line 2 and the second power line 3. The functional circuit 8 is connected to the second power supply line 3 and the third power supply line 4. When the power switch 5 is turned on, VDD of the first power supply line 2 is supplied to the functional circuit 8 through the second power supply line 3.

  The power switch 5 (see FIG. 1) includes a field effect transistor (FET) 40, a multiplexer 41, and a flip-flop 42.

  The FET 40 has a source connected to the first power line 2 and a drain connected to the second power line 3. A connection control signal (gate voltage) output from the multiplexer 41 is input to the gate of the FET 40.

  Two connection control signals are input to the multiplexer 41, and one of the two connection control signals is selected and output based on the selection control signal output from the output terminal Q of the flip-flop 42.

  The flip-flop 42 has a data terminal D, a clock terminal C, a reset terminal R, and the output terminal Q. The flip-flop 42 outputs the selection control signal from the output terminal Q based on the relationship between an input signal input to the data terminal D and an internal signal that is input before that.

  The flip-flops 42 are connected in a daisy chain so that an output signal from the output terminal Q is input to the data terminal D of another flip-flop 42. It is configured. That is, each flip-flop 42 according to the present embodiment starts with the flip-flop 42 of the power switch 5-13 at the lower left in the figure, and the power switch 5-23 → 5-33 → 5-12 → 5-22 → 5. The connections are made in the order of −32 → 5-11 → 5-21 → 5-31.

  The signal generator 6 is a circuit that generates various signals for setting the control characteristics of each power switch 5, and includes a reset terminal 51, a first connection control signal output terminal 52, and a second connection control signal output. A terminal 53, a third connection control signal output terminal 54, a set terminal 55, an FF setting multiplexer 56, a mode terminal 57, and a data shift terminal 58;

  The reset terminal 51 outputs a reset signal for resetting an internal signal of the flip-flop 42.

  The first to third connection control signal output terminals 52, 53 and 54 output the connection control signal (gate voltage) for controlling the connection state of the FET 40. These first to third connection control signal output terminals 52, 53, and 54 output different connection control signals, respectively.

  As described above, in the present embodiment, the first to third connection control signal output terminals 52, 53, and 54 generate the three types of connection control signals (CTRL0, CTRL1, and CTRL2). The multiplexer 41 receives two (including the same case) connection control signals selected from these three types, and which connection control signal is input depends on the power switch 5. It depends on. In the present embodiment, a connection control signal CTRL0 and a connection control signal CTRL1 are input to the multiplexer 41 of the power switches 5-11, 5-12, 5-13 in the left column. The multiplexer 41 of the power switch 5-21, 5-22, 5-23 in the center column includes a connection control signal CTRL1 and the multiplexer 41 of the power switch 5-11, 5-12, 5-13 in the left column. The connection control signal (CTRL0 or 1) output from is input. The multiplexer 41 of the power switches 5-31, 5-32, 5-33 in the right column includes a connection control signal CTRL2 and the multiplexer 41 of the power switches 5-21, 5-22, 5-23 in the center column. The connection control signal (CTRL0 or 1) output from is input.

  The set terminal 55 outputs a signal for inputting to the data terminal D of the flip-flop 42.

  The FF setting multiplexer 56 selects and outputs one of the signal output from the set terminal 55 and the signal stored in the memory. This selection is performed based on the mode signal output from the mode terminal 57. The signal output from the FF setting multiplexer 56 is input to the data terminal D of the flip-flop 42 and becomes the internal signal or the input signal.

  With this configuration, by switching the mode signal, whether the value set as the internal signal of the flip-flop 42 is a value read from the memory 7 or a signal newly given from the set terminal 55 Can be selected.

  The data shift terminal 58 outputs a clock signal input to the clock terminal C of the flip-flop 42. This clock signal is used as a synchronization signal for propagating the set value of the flip-flop 42 (internal signal at the time of activation) to the flip-flop 42 connected to the subsequent stage. That is, in synchronization with the pulse edge of the clock signal, a signal is input to the data terminal D of the power switch 5-13, and a signal output from the output terminal Q of the power switch 5-13 is the power switch 5-13. 5-23 is input to the data terminal D. Similarly, signals are propagated in the order of the power switch 5-23 → 5-33 → 5-12 → 5-22 → 5-32 → 5-11 → 5-21 → 5-31. The signal input to the data terminal D of the head power switch 5-13 is either a signal stored in the memory 7 or a signal output from the set terminal 55.

  FIG. 3 shows an example of the setting state of each power switch 5. In this example, the first connection control signal CTRL0 is input to the transistors 40 of the power switches 5-11, 5-12, and 5-13. A second connection control signal CTRL1 is input to the transistors 40 of the power switches 5-21, 5-22, and 5-23. A third connection control signal CTRL2 is input to the transistors 40 of the power switches 5-31, 5-32, and 5-33.

  FIG. 4 shows a timing chart of each power switch 5 according to the example shown in FIG. As shown in this timing chart, when the first connection control signal CTRL0 is output, the power switches 5-11, 5-12, and 5-13 are turned on. Further, when the second connection control signal CTRL1 is output, the power switches 5-21, 5-22, and 5-23 are turned on. Further, when the third connection control signal CTRL2 is output, the power switches 5-31, 5-32, and 5-33 are turned on. In this example, the connection control signals CTRL 0, 1, 2 have rising edges that are faster in time in the order of CTRL 0, CTRL 1, CTRL 2. Therefore, the group of the power switches 5-11, 5-12, 5-13 → the group of the power switches 5-21, 5-22, 5-23 → the power switches 5-31, 5-32, 5-33 The connection is turned ON in the order of the groups.

  Then, the functional circuit 8 (see FIG. 2) having a small amount of necessary current is connected to the group of the power switches 5-11, 5-12, and 5-13 which are turned on at an early timing, and are turned on at a later timing. The functional circuit 8 having a larger required current amount is sequentially connected to the group of the power switches 5-21, 5-22, 5-23 and the group of 5-31, 5-32, 5-33. Accordingly, as shown in FIG. 5, the power switches 5-11, 5-12, 5-13, the power switches 5-21, 5-22, 5-23, and the power switches 5-31, 5-32 , 5-33 are sequentially turned ON, the current amount of the semiconductor integrated circuit 1 as a whole increases stepwise, so that no rush current occurs.

  FIG. 6 shows another example of the setting state of each power switch 5. In this example, the first connection control signal CTRL0 is input to the transistors 40 of the power switches 5-11, 5-12, 5-13, 5-22, 5-23, and 5-33. A second connection control signal CTRL1 is input to the transistors 40 of the power switches 5-21 and 5-31. A third connection control signal CTRL2 is input to the transistor 40 of the power switch 5-32.

  FIG. 7 shows a timing chart of each power switch 5 according to the example shown in FIG. As shown in this timing chart, when the first connection control signal CTRL0 is output, the power switches 5-11, 5-12, 5-13, 5-22, 5-23, and 5-33 are turned on. It becomes. Further, when the second connection control signal CTRL1 is output, the power switches 5-21 and 5-31 are turned on. Further, when the third connection control signal CTRL2 is output, the power switch 5-33 is turned on. Accordingly, the group of the power switches 5-11, 5-12, 5-13, 5-22, 5-23, 5-33 → the group of the power switches 5-21, 5-31 → the power switch 5- In the order of 32, the connection is turned ON.

  Then, the functional circuit 8 having a small required current amount is connected to the group of the power switches 5-11, 5-12, 5-13, 5-22, 5-23, and 5-33 which are turned on at an early timing. The functional circuit 8 having a larger required current amount is sequentially connected to the group of the power switches 5-21 and 5-31 which are turned on at a later timing, and 5-32. Accordingly, as shown in FIG. 8, the power switches 5-11, 5-12, 5-13, 5-22, 5-23, 5-33, the power switches 5-21, 5-31, the power supply As the switch 5-32 is sequentially turned on, the current amount of the semiconductor integrated circuit 1 as a whole increases stepwise, so that no rush current occurs.

  As described above, in the semiconductor integrated circuit 1 according to the present invention, the setting of each power switch 5 can be arbitrarily changed. In the present embodiment, the connection control for switching the output signal of the multiplexer 41, that is, the ON / OFF state of the transistor 40, by changing the selection control signal output from the output terminal Q of the flip-flop 42. The signals CTRL0, 1, 2 can be changed.

  The selection control signal output from the flip-flop 42 is determined by an internal signal of the flip-flop 42 and an input signal. The first internal signal is set by a signal input to the data terminal D of the flip-flop 42 at the time of activation. The signal input to the data terminal D is a signal read from the memory 7 or a signal output from the set terminal 55 as shown in FIG. 1, FIG. 3, or FIG. Selection from these two signals is performed by the FF setting multiplexer 56 based on the mode signal from the mode terminal 57. During normal startup, the signal read from the memory 7 is input to the flip-flop 42. When the setting is changed, an output signal from the set terminal 55 that is output according to the setting result by the user or another control circuit is input to the flip-flop 42.

  FIG. 9 is a diagram schematically showing a signal flow when setting the power switch 5 (the flip-flop 42). In the present embodiment, as described above, the flip-flops 42 of the power switches 5 are connected in a daisy chain, and each flip-flop 42 constitutes a shift register. That is, the power switches 5-13, 5-23, 5-33, 5-32, 5-22, 5-12, 5-11, 5-21 and 5-31 are connected in this order. The head power switch 5-13 (the flip-flop 42) is connected to the FF setting multiplexer 56 that outputs either the signal stored in the memory 7 or the signal output from the set terminal 58. The last power switch 5-31 (of the flip-flop 42) is connected to the memory 7.

  When starting up or changing the setting, as indicated by a solid arrow A in the figure, the signal output from the FF setting multiplexer 56 is synchronized with the clock signal, and the flip-flops of the corresponding power switch 5 respectively. Are sequentially input to the group 42. Further, the internal signal held in the flip-flop 42 of each power switch 5 can be stored in the memory 7 as indicated by the broken arrow B in the figure. That is, the internal signals held in the respective flip-flops 42 are sequentially propagated to the subsequent flip-flops 42 in synchronization with the clock signal, and finally all the internal signals are transferred to the corresponding flip-flops 42 (the above-mentioned flip-flops 42). .. Is stored in the memory 7 as information associated with the power switches 5-13, 5-23,. As a result, the changed setting can be stored in the memory 7, and the changed setting can be automatically applied when it is started next time.

  With the above configuration, it is possible to change the characteristics of each power switch 5 even after the semiconductor integrated circuit 1 is manufactured. Thereby, even if there is an error between the predicted value by simulation or the like and the actual measurement value of the manufactured product, adjustment is performed so that rush current can be prevented without replacing the transistor 40 or changing the printed wiring. be able to. Further, the setting of each power switch 5 can be changed for each user or for each application of the semiconductor integrated circuit 1.

FIG. 1 is a diagram showing a part of the configuration of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a diagram schematically showing a connection state of the power supply line, the power supply switch, and the functional circuit of the semiconductor integrated circuit according to the present embodiment. FIG. 3 is a diagram illustrating an example of a setting state of the power switch of the semiconductor integrated circuit according to the present embodiment. FIG. 4 is a diagram showing a timing chart of each power switch in the example shown in FIG. FIG. 5 is a graph showing the relationship between the passage of time and the amount of current in the semiconductor integrated circuit according to the example shown in FIG. FIG. 6 is a diagram showing another example of the setting state of the power switch of the semiconductor integrated circuit according to the present embodiment. FIG. 7 is a timing chart of each power switch in the example shown in FIG. FIG. 8 is a graph showing the relationship between the passage of time and the amount of current in the semiconductor integrated circuit according to the example shown in FIG. FIG. 9 is a diagram schematically showing a signal flow when setting the power switch (flip-flop) in the present embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 1st power supply line 3 2nd power supply line 4 3rd power supply line 5 Power supply switch 6 Signal generation circuit 7 Memory 40 Transistor (FET)
41 multiplexer 42 flip-flop 51 reset terminal 52 first connection control signal output terminal 53 second connection control signal output terminal 54 third connection control signal output terminal 55 set terminal 56 FF setting multiplexer 57 mode terminal 58 data shift terminal

Claims (5)

A semiconductor integrated circuit having a plurality of power switches for switching connections between a plurality of power lines,
At least one of the power switches is
A plurality of transistors connected between the power lines;
A setting value holding unit for holding setting values;
A semiconductor integrated circuit comprising: a selection unit that selects a connection control signal for switching a connection state of the transistor from a plurality of control signals based on the set value. A plurality of the power switches are provided,
First and second control signals are input to the selection unit of each of the power switches,
2. The semiconductor according to claim 1, wherein each of the power switches uses one of the first and second control signals as a control signal for the transistor based on a set value held by the set value holding unit. Integrated circuit. The set value holding unit includes a flip-flop,
The semiconductor integrated circuit according to claim 2, wherein the selection unit includes a multiplexer. 4. The semiconductor integrated circuit according to claim 3, further comprising setting value storage means for storing the setting value corresponding to each flip-flop. 5. The semiconductor integrated circuit according to claim 3, wherein the flip-flop forms a shift register with a flip-flop included in another power switch.

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