JP2010117283A - Semiconductor integrated circuit device, and test device of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of shortening a test time. <P>SOLUTION: When testing this semiconductor integrated circuit device, following processes are executed, namely: a selection process wherein a multiplexer 19 selects the first observation object signal from observation object signals P1-P4; a clock supply process wherein a clock supply circuit 27 supplies a clock satisfying a setup hold restriction to delay fluctuation of the observation object signal outputted from the multiplexer 19 to a flip-flop 26; a taking process wherein the flip-flop 26 takes the observation object signal outputted from the multiplexer 19, synchronously with a clock outputted from the clock supply circuit 27; and a delay adjustment process wherein a delay adjustment circuit 28 inputs the observation object signal outputted from the flip-flop 26, adjusts delay thereof, and can sample the observation object signals P1-P4 at a common timing at an output end thereof. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device equipped with a test circuit and a test method for the semiconductor integrated circuit device.

  FIG. 6 is a circuit diagram showing a part of an example of a conventional semiconductor integrated circuit device equipped with a test circuit. In FIG. 6, 1 is a semiconductor chip, 2-1, 2-2, 2-m are input pins, 3 is a circuit to be tested, 4-9 is a flip-flop, 10 is a clock tree for transmitting a clock CKt, 11-14 Is a test signal wiring provided for the observation target signals P1 to P4, 15 to 18 are delay elements such as buffers inserted in the signal wirings 11 to 14, and 19 is a selection of the observation target signals P1 to P4. A multiplexer constituting the selection circuit, 20 is an output pin for testing, and 21 is an input pin for a selection control signal for controlling the selection operation of the multiplexer 19.

  In this semiconductor integrated circuit device, a signal circuit 11 to 14, a multiplexer 19, an output pin 20, and an input pin 21 constitute a test circuit, and the observation target signals P 1 to P 4 are connected to the output pin 20 via the multiplexer 19. The observation target signal that is transmitted and output to the output pin 20 by the tester can be sampled.

In this semiconductor integrated circuit device, the delay time from the output terminals of the flip-flops 6 to 9, which are points (hereinafter referred to as probe points) in the semiconductor integrated circuit device where the values of the observation target signals P 1 to P 4 are to be observed, to the multiplexer 19. Different. For this reason, even if the multiplexer 19 is switched at a timing synchronized with the clock, the observation target signal may not be sampled at the original sampling timing. Therefore, when the multiplexer 19 is switched, it is necessary to sample the observation target signal while shifting the sampling timing of the observation target signal to determine the original sampling timing, which increases the test time. It was.
Japanese Patent Laid-Open No. 10-239395 JP 2000-314766 A JP-A-6-148288

  SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a semiconductor integrated circuit device and a method for testing a semiconductor integrated circuit device that can shorten a test time.

  The semiconductor integrated circuit device disclosed herein includes a selection circuit, a flip-flop, a clock supply circuit, and a delay adjustment circuit. The selection circuit selects a first observation target signal from a plurality of observation target signals inside the semiconductor integrated circuit device. The flip-flop captures the first observation target signal output from the selection circuit in synchronization with a clock. The clock supply circuit supplies, to the flip-flop, a clock that satisfies a setup / hold constraint with respect to a delay variation of the first observation target signal output from the selection circuit, as the clock. The delay adjustment circuit is configured to input the first observation target signal output from the flip-flop and perform delay adjustment, and at the output end thereof, the plurality of observation target signals can be sampled at a common timing.

  The test method for a semiconductor integrated circuit device disclosed herein includes a selection step, a clock supply step, a capture step, and a delay adjustment step. The selection step is a step in which the selection circuit selects a first observation target signal from a plurality of observation target signals inside the semiconductor integrated circuit device. The clock supply step is a step in which the clock supply circuit supplies a clock that satisfies a setup / hold constraint with respect to a delay variation of the first observation target signal output from the selection circuit to the flip-flop. The capturing step is a step in which the flip-flop captures the first observation target signal output from the selection circuit in synchronization with the clock. In the delay adjustment step, the delay adjustment circuit inputs the first observation target signal output from the flip-flop to adjust the delay, and at the output end, the plurality of observation target signals can be sampled at a common timing. It is a process.

  The flip-flop captures an observation target signal output from the selection circuit in synchronization with a clock that satisfies a setup / hold constraint with respect to a delay variation of the observation target signal output from the selection circuit. Thereby, the sampling possible range when the observation target signal output from the flip-flop is sampled to observe the value is expanded. In addition, the delay adjustment circuit is provided, the observation target signal output from the flip-flop is input and delay adjustment is performed, and at the output end, the plurality of observation target signals can be sampled at a common timing.

  Therefore, even when the observation target signal selected by the selection circuit is switched, the work of sampling the observation target signal and determining the original sampling timing while shifting the sampling timing of the observation target signal becomes unnecessary, and the test time is reduced. Can be shortened. In particular, according to the disclosed semiconductor integrated circuit device, circuit design can be performed without considering delay adjustment from the probe points of the plurality of observation target signals inside the semiconductor integrated circuit device to the selection circuit. The design process can be shortened.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. The present invention is not limited to one embodiment of the present invention. In FIG. 1, parts corresponding to those shown in FIG.

  FIG. 1 is a circuit diagram showing a part of an embodiment of a semiconductor integrated circuit device of the present invention. In one embodiment of the semiconductor integrated circuit device of the present invention, an output timing adjustment circuit 22 is provided between the multiplexer 19 and the output terminal 20, a selector control circuit 23 and an input pin 24 are provided. 6 is configured in the same manner as the conventional semiconductor integrated circuit device shown in FIG.

  The output timing adjustment circuit 22 expands the sampling possible range of the observation target signal and adjusts the output timing of the observation target signal. The selector control circuit 23 controls the selection operation of the selector in the output timing adjustment circuit 22. The input pin 24 is for inputting information to be set in the table 25 in the selector control circuit 23.

  In one embodiment of the semiconductor integrated circuit device of the present invention, testing is performed with the signal lines 11 to 14, the multiplexer 19, the output timing adjustment circuit 22, the selector control circuit 23, the output pin 20, and the input pins 21 and 24. A circuit is configured.

  The multiplexer 19 receives selection control signals SA1 and SA2 from the input pin 21. The multiplexer 19 selects the observation target signal P1 when SA1 = "0" and SA2 = "0", and selects the observation target signal P2 when SA1 = "0" and SA2 = "1", When SA1 = "1" and SA2 = "0", the observation target signal P3 is selected. When SA1 = "1" and SA2 = "1", the observation target signal P4 is selected.

  FIG. 2 is a circuit diagram showing the configuration of the output timing adjustment circuit 22. The output timing adjustment circuit 22 includes a flip-flop 26, a clock supply circuit 27, a delay adjustment circuit 28, and an output circuit 29.

  The flip-flop 26 takes in the observation target signal output from the multiplexer 19 in synchronization with the clock output from the clock supply circuit 27. The clock supply circuit 27 receives the clock CK1 and supplies the flip-flop 26 with a clock that satisfies the setup / hold constraint against the delay variation of the observation target signal output from the multiplexer 19. The clock CK1 is obtained by delaying the clock CKt through the transmission path.

  The clock supply circuit 27 has a branch circuit 30 and a selector 31. The branch circuit 30 divides the transmission path of the clock CK1 into four and has delay circuits 32 to 34. The delay circuits 32 to 34 delay the clock CK1, the delay circuit 32 outputs the clock CK2, the delay circuit 33 outputs the clock CK3, and the delay circuit 34 outputs the clock CK4. The delay circuits 32 to 34 are initially designed so that the delay time varies within one clock cycle, and adjusted later.

  The selector 31 is controlled by selector control signals SB1 and SB2, and selects one clock from the clocks CK1 to CK4. The selector 31 selects the clock CK1 when SB1 = "0" and SB2 = "0", selects the clock CK2 when SB1 = "0" and SB2 = "1", and SB1 = "1". When SB2 = "0", the clock CK3 is selected, and when SB1 = "1" and SB2 = "1", the clock CK4 is selected.

  The delay adjustment circuit 28 inputs the observation target signal output from the flip-flop 26, adjusts the delay, and enables the observation target signals P1 to P4 to be sampled at the common timing on the clock cycle at the output terminal. is there. The delay adjustment circuit 28 includes a branch circuit 35 and a selector 36. The branch circuit 35 divides the transmission path of the observation target signal output from the flip-flop 26 into four, and includes delay circuits 37 to 39. The delay circuits 37 to 39 delay the observation target signal output from the flip-flop 26, and the delay time of the delay circuit 37 <the delay time of the delay circuit 38 <the delay time of the delay circuit 39. The delay circuits 37 to 39 are initially designed so that the delay time varies, and are adjusted later.

  The selector 36 is controlled by the selector control signals SC1 and SC2, and selects one observation target signal from the observation target signals output from the flip-flop 26 and the observation target signals output from the delay circuits 37 to 39. The selector 36 selects the observation target signal output from the flip-flop 26 when SC1 = "0" and SC2 = "0", and the delay circuit 37 when SC1 = "0" and SC2 = "1". Is selected, and when SC1 = "1" and SC2 = "0", the observation signal output by the delay circuit 38 is selected and SC1 = "1" and SC2 = "1". In this case, the observation target signal output from the delay circuit 39 is selected.

  The output circuit 29 is for outputting the observation target signal output from the delay adjustment circuit 28 to the outside, and includes a flip-flop 40 and an output buffer 41. The flip-flop 40 takes in the observation target signal output from the selector 36 in synchronization with the clock CK5. The clock CK5 is obtained by delaying the clock CKt through the transmission path.

  FIG. 3 is a diagram showing the contents of the table 25. The table 25 has a rewritable memory element, and in this memory element, an observation target signal to be output to the outside (observation target signal to be output by the multiplexer 19), selection control signals SB1 and SB2, and a selection control signal SC1 and SC2 are stored in association with each other. The table 25 may be composed of a ROM (read only memory). In this case, the contents of the table 25 are written in the manufacturing process, and the input pin 24 is not necessary.

  The selector control circuit 23 writes the contents of the table 25 given through the input pin 24 into the table 25, inputs the selection control signals SA1 and SA2, and refers to the table 25 to select the selection control signals SA1 and SA2. Selection control signals SB1, SB2, SC1, and SC2 having values corresponding to the values (observation target signals to be output to the outside) are output.

  In this example, the selector control circuit 23 SB1 = "1", SB2 = "0", SC1 when SA1 = "0" and SA2 = "0" (when the observation target signal P1 is output to the outside). = "0" and SC2 = "1". As a result, the selector 31 selects the clock CK3 output from the delay circuit 33, and the selector 36 selects the observation target signal output from the delay circuit 37.

  Further, the selector control circuit 23, when SA1 = “0” and SA2 = “1” (when the observation target signal P2 is output to the outside), SB1 = “0”, SB2 = “1”, and SC1 = “ 1 ”and SC2 =“ 0 ”. As a result, the selector 31 selects the clock CK2 output from the delay circuit 32, and the selector 36 selects the observation target signal output from the delay circuit 38.

  Further, the selector control circuit 23, when SA1 = "1" and SA2 = "0" (when the observation target signal P3 is output to the outside), SB1 = "1", SB2 = "1", SC1 = " 0 ”and SC2 =“ 0 ”. As a result, the selector 31 selects the clock CK4 output from the delay circuit 34, and the selector 36 selects the observation target signal output from the flip-flop 26.

  Further, the selector control circuit 23, when SA1 = "1" and SA2 = "1" (when the observation target signal P4 is output to the outside), SB1 = "0", SB2 = "0", SC1 = “1” and SC2 = “1”. As a result, the selector 31 selects the clock CK1, and the selector 36 selects the observation target signal output from the delay circuit 39.

  A semiconductor integrated circuit according to an embodiment of the present invention is designed as follows. First, the physical design of the circuit is performed without considering the restrictions of the test circuit (step S1). Next, the delay from the probe points of the observation target signals P1 to P4 (output terminals of the flip-flops 6 to 9) to the multiplexer 19 is estimated by static timing analysis (step S2). Next, the delay of the clocks CK1 to CK4 is inserted or deleted so that the clock output from the clock supply circuit 27 satisfies the setup hold constraint with respect to the delay variation of the observation target signal output from the multiplexer 19. (Step S3). Next, the delay values of the delay circuits 37 to 39 of the delay adjustment circuit 28 are determined from the result of the static timing analysis (step S4).

  FIG. 4 is a timing chart for explaining delay adjustment (step S3) of the clocks CK1 to CK4. In FIG. 4, Pka (where k = 1, 2, 3, 4 and so on), Pkb indicates the observation target signal Pk given to the flip-flop 26. Pka is a case where there is no delay variation due to process variations, drive voltage changes, and chip temperature changes, and the delay value from the probe point of the observation target signal Pk to the multiplexer 19 is the minimum value. Pkb has the maximum delay variation due to process variations, drive voltage changes, and chip temperature changes, and the delay value from the probe point of the observation target signal Pk to the multiplexer 19 is the maximum value. Pk-0 to Pk-3 indicate values of the observation target signal P1.

  In this case, when the observation target signal Pk is captured from the flip-flop 26, the observation target signal Pk is temporally overlapped with the value Pk-1 portion of the observation target signal Pka and the value Pk-1 portion of the observation target signal Pkb. The same data portion of the observation target signal Pka and the observation target signal Pkb, such as a range or a range in which the portion of the value Pk-2 of the observation target signal Pka and the portion of the value Pk-2 of the observation target signal Pkb overlap in time. The overlapping range Wk is a signal in which the value of the observation target signal Pk is certain, and the part other than the range Wk is a signal in which the value of the observation target signal Pk is indefinite. Therefore, the range Wk where the same data portions of the observation target signal Pka and the observation target signal Pkb overlap is the possible range of sampling. Pkc indicates the observation target signal Pk captured from the flip-flop 26 as described above.

  Therefore, in this case, the clock output from the clock supply circuit 27 has a rising edge in the range W1, a rising edge in the range W2, a rising edge in the range W3, and a rising edge in the range W4. It is necessary to adjust the delay of the clocks CK1 to CK4 so that there are four types.

  FIG. 5 is a timing chart for explaining a test operation (one embodiment of the test method of the semiconductor integrated circuit device of the present invention) executed in one embodiment of the semiconductor integrated circuit device of the present invention. (A) is a clock CKt, CK1 to CK4, (B) is an observation target signal P1_19 to P4_19 output from the multiplexer 19, (C) is an observation target signal P1_26 to P4_26 output from the flip-flop 26, and (D) is a delay adjustment. Observation target signals P1_28 to P4_28 (E) output from the circuit 28 indicate a clock CK5 applied to the flip-flop 40.

  The observation target signals P1_19, P1_26, and P1_28 correspond to the observation target signal P1, the observation target signals P2_19, P2_26, and P2_28 correspond to the observation target signal P2, and the observation target signals P3_19, P3_26, and P3_28 correspond to the observation target signal P3. The observation target signals P4_19, P4_26, and P4_28 correspond to the observation target signal P4.

  In this example, the clock CK1 is delay-adjusted with respect to the observation target signal P4_19 output from the multiplexer 19 so as to satisfy the setup / hold constraint. The clock CK2 is delay-adjusted with respect to the observation target signal P2_19 output from the multiplexer 19 so as to satisfy the setup / hold constraint. The clock CK3 is delay-adjusted with respect to the observation target signal P1_19 output from the multiplexer 19 so as to satisfy the setup / hold constraint. The clock CK4 is delay-adjusted with respect to the observation target signal P3_19 output from the multiplexer 19 so as to satisfy the setup / hold constraint.

  Therefore, when the multiplexer 19 outputs the observation target signal P1_19, the selector control signal 23 causes the selector 31 to select the clock CK3. As a result, the observation target signal output from the flip-flop 26 is the observation target signal P1_26.

  When the multiplexer 19 outputs the observation target signal P2_19, the selector control signal 23 causes the selector 31 to select the clock CK2. As a result, the observation target signal output from the flip-flop 26 is the observation target signal P2_26.

  Further, when the multiplexer 19 selects the observation target signal P3_19, the selector control signal 23 causes the selector 31 to select the clock CK4. As a result, the observation target signal output from the flip-flop 26 is the observation target signal P3_26.

  When the multiplexer 19 selects the observation target signal P4_19, the selector control signal 23 causes the selector 31 to select the clock CK1. As a result, the observation target signal output from the flip-flop 26 is the observation target signal P4_26.

  The observation target signals P1_26 to P4_26 output from the flip-flop 26 are delay-adjusted by the delay adjustment circuit 28 in accordance with the contents of the table 25. In this example, the observation target signal P1_28 is obtained by delaying the observation target signal P1_26 by the delay circuit 37. The observation target signal P2_28 is obtained by delaying the observation target signal P_26 by the delay circuit 38. The observation target signal P3_28 does not delay the observation target signal P3_26. The observation target signal P4_28 is obtained by delaying the observation target signal P4_26 by the delay circuit 39.

  That is, at the time of the test, the multiplexer 19 selects one observation target signal from the observation target signals P1 to P4, and the clock supply circuit 27 detects the delay variation of the observation target signal output from the multiplexer 19 to the flip-flop 26. A clock supply process for supplying a clock satisfying the setup / hold constraint, and a capture process for capturing the observation target signal output from the multiplexer 19 in synchronization with the clock output from the clock supply circuit 27 by the flip-flop 19. The delay adjustment circuit 28 receives the observation target signal output from the flip-flop 26 and performs delay adjustment, and at the output end thereof, a delay adjustment step is performed to enable the observation target signals P1 to P4 to be sampled at a common timing. The

  The observation target signal output from the delay adjustment circuit 28 is transmitted to the output pin 20 via the output circuit 29. Therefore, the tester can observe the values of the observation target signals P1 to P4 by sampling the observation target signals P1 to P4 output to the output pin 20 at a common timing on the clock cycle.

  In the embodiment of the semiconductor integrated circuit device of the present invention, the output circuit 29 is provided. However, the observation target signal output from the delay adjustment circuit 28 is directly output without providing the output circuit 29. It may be transmitted to the pin 20. In this case, in the range W0 shown in FIG. 5D, the tester samples the observation target signals P1 to P4 output to the output pin 20 at a common timing on the clock cycle, thereby obtaining the observation target signal. The values of P1 to P4 can be observed. Even in this case, the sampleable range W0 is larger than the sampleable ranges W1 to W4 shown in FIG.

  As described above, the observation target signals P1 to P4 cause delay fluctuations due to process variations, drive voltage changes, chip temperature changes, and the like. Therefore, when the observation target signals P1 to P4 output from the multiplexer 19 are captured by the flip-flop 26, the setup / hold constraint is satisfied even when the delay variation of the observation target signals P1 to P4 output from the multiplexer 19 is maximum. It is necessary to supply a clock to the flip-flop 26. Therefore, in one embodiment of the semiconductor integrated circuit device of the present invention, the clock supply circuit 27 supplies the flip-flop 26 with a clock as a clock for setting up and holding constraints on the delay variation of the observation target signals P1 to P4 output from the multiplexer 19. A clock that satisfies the requirements is supplied.

  As a result, the flip-flop 26 captures the observation target signal output from the multiplexer 19 in synchronization with a clock that satisfies the setup / hold constraint with respect to the delay variation of the observation target signals P1 to P4 output from the multiplexer 19. . Thereby, the sampling possible range W1-W4 in the case of sampling the observation object signal output from the flip-flop 26 in order to observe the value is expanded. In addition, a delay adjustment circuit 28 is provided, and the observation target signals P1 to P4 output from the flip-flop 26 are input to adjust the delay. At the output end, the observation target signals P1 to P4 are set to a common timing on the clock cycle. Sampling is possible.

  Therefore, according to one embodiment of the semiconductor integrated circuit device of the present invention, even when the observation target signal selected by the multiplexer 19 is switched, the observation target signal is sampled while shifting the sampling timing of the observation target signal. This eliminates the need to determine the sampling timing of the test and shortens the test time. In addition, since the circuit design can be performed without considering the delay adjustment from the probe points of the observation target signals P1 to P4 (output terminals of the flip-flops 6 to 9) to the multiplexer 19, the design process can be shortened. .

It is a circuit diagram which shows a part of one Embodiment of the semiconductor integrated circuit device of this invention. It is a circuit diagram which shows the structure of the output timing adjustment circuit which one Embodiment of the semiconductor integrated circuit device of this invention has. It is a figure which shows the content of the table in the selector control circuit which one Embodiment of the semiconductor integrated circuit device of this invention has. 6 is a timing chart for explaining clock delay adjustment executed in an embodiment of the semiconductor integrated circuit of the present invention; 6 is a timing chart for explaining a test operation (one embodiment of a test method of a semiconductor integrated circuit device of the present invention) executed in one embodiment of a semiconductor integrated circuit device of the present invention; It is a circuit diagram which shows a part of example of the conventional semiconductor integrated circuit device carrying a test circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip 2-1, 2-2, 2-m ... Input pin 3 ... Test object circuit 4-9 ... Flip-flop 10 ... Clock tree 11-14 ... Signal wiring for a test 15-18 ... Delay element 19 ... Multiplexer 20 ... Output pin 21 ... Input pin 22 ... Output timing adjustment circuit 23 ... Selector control circuit 24 ... Input pin 25 ... Table 26 ... Flip-flop 27 ... Clock supply circuit 28 ... Delay adjustment circuit 29 ... Output circuit 30 ... Branch circuit 31 ... Selector 32-34 ... Delay circuit 35 ... Branch circuit 36 ... Selector 37-39 ... Delay circuit 40 ... Flip-flop 41 ... Output buffer

Claims (4)

A first selection circuit that selects a first observation target signal from a plurality of observation target signals inside the semiconductor integrated circuit device;
A flip-flop that captures the first observation target signal output from the first selection circuit in synchronization with a clock;
A clock supply circuit that supplies, to the flip-flop, a clock that satisfies a setup / hold constraint with respect to a delay variation of the first observation target signal output from the first selection circuit, as the clock;
A delay adjustment circuit that inputs the first observation target signal output from the flip-flop and performs delay adjustment, and at the output end thereof, the delay adjustment circuit that enables sampling of the plurality of observation target signals at a common timing;
A semiconductor integrated circuit device comprising: The clock supply circuit includes:
A first branch circuit that uses a first clock as a plurality of clocks having different phases through the first plurality of branch transmission lines;
A second selection circuit for selecting a second clock from the plurality of clocks output by the first branch circuit;
Have
The delay adjustment circuit includes:
A second branch circuit that uses the first observation target signal output from the flip-flop as a plurality of delay-containing observation target signals having different phases through a second plurality of branch transmission lines;
A third selection circuit for selecting a first delay-containing observation target signal from the plurality of delay-containing observation target signals output by the second branch circuit;
The semiconductor integrated circuit device according to claim 1, comprising: A selection control circuit for controlling a selection operation of the second selection circuit and the third selection circuit;
The selection control circuit includes:
The value of the first selection control signal given to the first selection circuit, the value of the second selection control signal given to the second selection circuit, and the value of the third selection control signal given to the third selection circuit are related to each other. A memory circuit for storing
3. The method according to claim 2, wherein the first selection control signal is input, and the second selection control signal and the third selection control signal having values corresponding to the value of the first selection control signal are output. Semiconductor integrated circuit device. A selection step in which the selection circuit selects a first observation target signal from a plurality of observation target signals inside the semiconductor integrated circuit device;
A clock supply step in which a clock supply circuit supplies a clock that satisfies a setup / hold constraint with respect to a delay variation of the first observation target signal output from the selection circuit to a flip-flop;
A capturing step in which the flip-flop captures the first observation target signal output from the selection circuit in synchronization with the clock;
A delay adjustment step in which a delay adjustment circuit inputs and delay-adjusts the first observation target signal output from the flip-flop, and allows the plurality of observation target signals to be sampled at a common timing at an output end thereof;
A method for testing a semiconductor integrated circuit device, comprising:

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