JP2010114201A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of keeping insulation excellent between a semiconductor substrate included in the semiconductor device and wiring including a through silicon via (TSV) formed in the semiconductor substrate. <P>SOLUTION: A part of an insulating film formed on an inner wall of the through silicon via except a part corresponding to an opening bottom is coated with etching resist and the insulating film is removed through etching using the etching resist as a mask to expose an electrode pad. Then a conductive layer is formed for wiring. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device having a wiring connected to an electrode through a through hole provided in a semiconductor substrate.

  With recent miniaturization of mobile phone terminals and other various devices, miniaturization of semiconductor devices constituting those devices is desired. As a semiconductor device for realizing miniaturization, a chip size package (CSP) in which the size of the semiconductor device is approximately the same as the size of a semiconductor chip is known. Examples of the chip size package include a semiconductor device incorporating a solid-state image sensor such as an image sensor. Usually, in a chip size package, rewirings connected to electrode pads are formed through through holes (TSV: Through Silicon Via) provided in a semiconductor substrate.

For example, Patent Document 1 discloses a semiconductor device related to a chip size package, in which a wiring connected to an electrode pad through a through hole is formed, and a manufacturing method thereof. According to the manufacturing method, first, an insulating film and an electrode are stacked on the surface of the semiconductor substrate, and a through hole reaching the insulating film is formed by etching the semiconductor substrate. Next, after forming an insulating film so as to cover the insulating film and the inner surface of the through hole, the insulating film on the bottom surface of the through hole is removed by a technique such as directional etching to expose the electrode. Then, a wiring connected to the electrode from the surface of the semiconductor substrate through the through hole is formed.
JP 2005-294320 A

  However, the semiconductor device manufacturing method disclosed in Patent Document 1 is formed on the side surface of the through hole when the insulating film on the bottom surface of the through hole is removed by a directional etching method in order to expose the electrode. There is a problem that even the insulating film is removed by etching. According to the directional etching method, it is not possible to selectively irradiate the etching beam only to the insulating film on the bottom surface of the through-hole, but the etching beam can reach the surrounding insulating film, that is, the side surface of the through-hole and the insulating film on the surface of the semiconductor substrate. It is because it is irradiated. For example, the insulating film on the side surface of the through hole is easily removed when the side surface of the through hole has a so-called tapered shape in which the side surface of the through hole is inclined or the shape of the side surface of the through hole is uneven. . In this case, since the insulating film on the side surface of the through hole is thinned, there is a problem that the insulation between the wiring formed on the side surface of the through hole and the semiconductor substrate is deteriorated and short-circuited.

  In order to prevent the insulating film on the side surface of the through hole from being thinned by etching, for example, even if the insulating film on the side surface of the through hole is formed thick, the insulating film on the surface of the semiconductor substrate is also formed at the same time. When the insulating film on the bottom surface of the through hole is completely removed by the directional etching method to expose the pad, the insulating film on the surface of the semiconductor substrate is also thinned at the same time. As a result, the insulating property on the surface of the semiconductor substrate cannot be maintained. Therefore, this method could not solve the problem.

  The present invention has been made in view of the above problems, and a semiconductor device capable of maintaining good insulation between a semiconductor substrate constituting the semiconductor device and a wiring formed on the semiconductor substrate. It aims at providing the manufacturing method of.

  A method of manufacturing a semiconductor device according to the present invention includes a semiconductor substrate, a through hole provided in the semiconductor substrate, an electrode pad formed at an opening bottom of the through hole, and the electrode pad via the through hole. Wiring for reaching the surface of the semiconductor substrate, and an insulating film forming step of forming an insulating film so as to cover the inner wall of the through hole and the surface of the semiconductor substrate, An etching resist forming step of covering a portion of the insulating film excluding a portion corresponding to the bottom of the opening with an etching resist, and removing the portion of the insulating film by etching using the etching resist as a mask to expose the electrode pad An insulating film removing step, and reaching the exposed portion of the electrode pad from the insulating film on the surface of the semiconductor substrate via the through hole. Characterized in that a conductive layer and a conductive layer formation step of forming, as the wiring.

  According to the semiconductor device manufacturing method of the present invention, it is possible to manufacture a semiconductor device in which the insulation between the semiconductor substrate and the wiring is kept good.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.
<First embodiment>
First, as shown in FIG. 1A, an intermediate product 11 to be subjected to TSV formation processing is prepared. The intermediate product 11 is formed by bonding the semiconductor substrate 1 to the support base 5 with the adhesive 6. As the support base 5, for example, when the semiconductor device 10 is an imaging device, a translucent substrate such as a glass substrate is used. The semiconductor substrate 1 is, for example, a silicon substrate. When the semiconductor device 10 is an imaging device, for example, a solid-state imaging element or the like (not shown) is formed on the surface of the semiconductor substrate 1. The adhesive 6 is, for example, a polyimide adhesive.

  An insulating layer 2 such as a silicon oxide film and a protective film 4 such as a silicon nitride film are stacked in this order on the surface of the semiconductor substrate 1. The protective film 4 is a so-called passivation film for protecting the surface of the semiconductor substrate 1. An electrode pad 3 is formed on the surface of the semiconductor substrate 1 with the insulating layer 2 interposed therebetween. The semiconductor substrate 1 and the electrode pad 3 are insulated by the insulating layer 2. The electrode pad 3 is a metal pad such as aluminum. The protective film 4 on the electrode pad 3 has been removed.

  The lamination of the insulating layer 2 and the protective film 4 to the semiconductor substrate 1, the formation of the electrode pad 3, and the adhesion between the support base 5 and the semiconductor substrate 1 can be realized by a conventionally known normal method. When the support substrate 5 and the semiconductor substrate 1 are bonded, the adhesive 6 is removed from the portion corresponding to the semiconductor element such as a solid-state imaging element formed on the surface of the semiconductor substrate 1 to form a so-called air gap. It may be formed. After bonding the support base 5 and the semiconductor substrate 1, the back surface of the semiconductor substrate 1 may be polished by a normal back grinding method to adjust its thickness. In this case, the thickness of the semiconductor substrate 1 is, for example, about 100 μm.

  Next, as shown in FIG. 1B, a resist is applied to the back surface of the semiconductor substrate 1, and the resist on the electrode pad 3 is removed by an ordinary exposure and development method to provide an opening OP.

  Next, as shown in FIG. 1C, the semiconductor substrate 1 and the insulating layer 2 corresponding to the opening OP are etched by normal dry etching, and the through hole 8 reaching the electrode pad 3 from the back surface of the semiconductor substrate 1. Form. Hereinafter, the side where the electrode pad 3 is formed in the opening of the through hole 8 is referred to as an opening bottom 8a, and the opening on the opposite side is referred to as an opening top 8b. The side wall of the through hole 8 is referred to as a through hole side wall portion 8c.

  Next, as shown in FIG. 2A, an insulating film 7 is formed so as to cover the inner wall of the through hole 8 and the back surface of the semiconductor substrate 1. The insulating film 7 is, for example, a silicon oxide film, and is formed by, for example, a plasma CVD (Chemical Vapor Deposition) method. As a source gas for the plasma CVD method, for example, tetraethoxysilane (TEOS) is used.

  Next, as shown in FIG. 2B, a negative photosensitive resist NR is applied on the insulating film 7. The negative photosensitive resist NR is preferably applied by a spray method. For example, when applied by a spin coating method, the resist falls into the through-hole 8 due to centrifugal force and is difficult to be formed on the back surface of the semiconductor substrate 1, whereas when applied by a spray method, the negative photosensitive resist NR. Is applied to the entire inner wall of the through hole 8 and the entire back surface of the semiconductor substrate 1. In addition, there is no restriction | limiting that must be the application by a spray system, and the application by a spin coat system may be sufficient.

  Next, as shown in FIG. 2C, the negative photosensitive resist NR is exposed. At this time, exposure is performed so that only the negative photosensitive resist NR corresponding to the back surface of the semiconductor substrate 1 and the negative photosensitive resist NR corresponding to the side surface from the opening top 8b to the predetermined depth DP are exposed. Specifically, the exposure is performed so that the exposure beam EL is incident obliquely with respect to the depth direction of the through-hole 8 (the direction indicated by the alternate long and short dash line in the drawing). Specifically, the exposure beam EL is irradiated so as to be incident at a predetermined angle θ such as 45 degrees with respect to the depth direction of the through hole 8. In this case, the exposure beam EL does not reach the opening bottom 8a, and only the negative photosensitive resist NR up to a predetermined depth DP indicated by a dotted line in the drawing is exposed.

  The depth DP can be adjusted by changing the angle θ. That is, if the angle θ is increased, the depth DP becomes shallower, and if the angle θ is decreased, the depth DP becomes deeper. The depth DP and the angle θ are not limited, and may be appropriately adjusted according to the depth of the through hole 8, the size of the opening of the through hole 8, the coating thickness of the negative photosensitive resist NR, and the like. The depth DP may reach the opening bottom 8a, and the negative photosensitive resist NR may be exposed except for the portion corresponding to the opening bottom 8a.

  The exposure beam EL is, for example, ultraviolet light. The light source of the exposure beam EL is, for example, a laser. The laser serving as the light source is, for example, an excimer laser such as KrF (wavelength 248 nm), ArF (wavelength 193 nm), or F2 (wavelength 157 nm). The light source and wavelength of the exposure beam EL are not limited, and may be appropriately selected according to the photosensitive characteristics of the negative photosensitive resist NR.

  When performing the exposure, as shown in FIG. 3A, the light source SL is fixed and rotated (rotated) without changing the position of the wafer WF on which the semiconductor substrate 1 is formed, or FIG. As shown in b), the wafer WF is fixed and the light source SL is rotated (revolved) around the wafer WF. When rotating the wafer WF, for example, the wafer WF is fixed to a turntable (not shown) and rotated. In this case, the wafer WF is fixed at the center of the rotation axis. When rotating the light source SL, for example, the light source SL is fixed and rotated on a turntable (not shown). In this case, the light source SL is fixed while being shifted from the center of the rotation axis. The direction of rotation is indicated by an arrow in the figure. By doing in this way, the whole through-hole side wall part 8c to depth DP is exposed. The exposure light from the light source SL may be one that can cover the entire surface of the wafer WF at one time, or one that can irradiate only a part of the wafer WF. In the former case, the entire surface of the wafer WF can be exposed at once. In the latter case, exposure is sequentially performed over the entire surface of the wafer WF by moving a turntable (not shown) on which the wafer WF is mounted or a light source SL.

  2D, only the negative photosensitive resist NR corresponding to the back surface of the semiconductor substrate 1 and the through hole sidewall 8c up to the depth DP is exposed to the developer. Insolubilize. Of the negative photosensitive resist NR, the exposed resist is shown as an etching resist ER in FIG. Here, the etching resist ER refers to a resist used for partial protection (mask) during the etching process, in the same manner as is normally used.

  Next, as shown in FIG. 4A, the non-photosensitive negative photosensitive resist NR below the depth DP in the through hole 8 is removed by development processing. As a result, the insulating film 7 covering the opening bottom 8a is exposed. On the other hand, since the etching resist ER is insoluble in the developer, it remains as it is after development.

  Next, as shown in FIG. 4B, a part of the insulating film 7 covering the bottom 8a of the opening is removed to expose the electrode pad 3. For example, the insulating film 7 is removed by anisotropic dry etching such as reactive ion etching (RIE). In this case, the insulating film 7 is etched by making etching ions EI incident perpendicularly to the opening bottom 8a. When the insulating film 7 is a silicon oxide film, a fluorine-based gas such as carbon tetrafluoride (CF4) is used as an etching gas.

  Since the etching resist ER serves as a mask during anisotropic dry etching, the insulating film 7 covering the through-hole side wall 8c remains without being removed. According to anisotropic dry etching such as RIE, ions for etching enter the through hole 8 perpendicularly, and therefore the insulating film 7 covering the through hole side wall 8c below the depth DP is also removed. It remains as it is. Further, the insulating film 7 formed on the back surface of the semiconductor substrate 1 is not removed but remains as it is protected from the etching ions EI by the etching resist ER.

  Next, as shown in FIG. 4C, the etching resist ER is removed and electrically connected to the exposed portion of the electrode pad 3 through the through hole 8 from the insulating film 7 on the back surface of the semiconductor substrate 1. Thus, a conductive layer is formed as the wiring 9. For example, the etching resist ER is removed by an asher that is a resist stripping (ashing) apparatus. The asher may be of a type in which the gas and the resist are chemically reacted with light such as ultraviolet rays and the resist is peeled off, or may be of a type in which the resist is decomposed and removed in the gas phase by plasma irradiation.

  The wiring 9 is a wiring made of metal such as copper. Since the back surface of the semiconductor substrate 1 and the through hole side wall 8c are covered with the insulating film 7, the wiring 9 and the semiconductor substrate 1 are completely insulated. On the other hand, the wiring 9 is electrically connected to the exposed portion of the electrode pad 3.

  The semiconductor device 10 is manufactured by the above processing. Normally, a plurality of through holes 8 are formed in the semiconductor substrate 1, but FIGS. 1, 2, and 4 are illustrated by paying attention to one of them. The semiconductor device 10 is, for example, a chip size package that incorporates a semiconductor element such as a solid-state imaging element (image sensor or the like).

As described above, according to the semiconductor device manufacturing method of the present embodiment, the wiring 9 that is insulated from the semiconductor substrate 1 and electrically connected to the electrode pad 3 can be formed on the semiconductor substrate 1. Thus, a short circuit between the wiring 9 and the semiconductor substrate 1 can be avoided, and a semiconductor device that operates normally can be manufactured.
<Second embodiment>
FIG. 5 is a cross-sectional view of a semi-finished product in each step of the etching resist forming process according to this embodiment. Hereinafter, the etching resist forming process will be described with reference to FIG. The through hole 8 is formed by the process shown in FIG. 1 as in the first embodiment. The insulating film 7 is formed by the process shown in FIG. 2A as in the first embodiment.

  First, as shown in FIG. 5A, a positive photosensitive resist PR is deposited from the opening bottom 8a to a predetermined height HT (indicated by a dotted line) by, eg, spin coating. The height HT can be adjusted by changing the amount of the positive photosensitive resist PR. That is, if the amount of the positive photosensitive resist PR is increased, the height HT is increased, and if the amount of the positive photosensitive resist PR is decreased, the height HT is decreased. The height HT is not limited, and may be appropriately adjusted according to the depth of the through hole 8, the size of the opening of the through hole 8, the coating thickness of the negative photosensitive resist NR, and the like.

  Next, as shown in FIG. 5B, a negative photosensitive resist NR is applied on the insulating film 7 and the positive photosensitive resist PR. It is desirable to apply the negative photosensitive resist NR by spraying so that the insulating film 7 covering the inner wall of the through hole 8 and the entire back surface of the semiconductor substrate 1 can be applied. At this time, the thickness of the negative photosensitive resist NR applied on the insulating film 7 on the back surface of the semiconductor substrate 1 is equal to the negative photosensitive resist NR applied on the positive photosensitive resist PR in the through hole 8. Apply to be thicker than

  Next, as shown in FIG. 5C, the negative photosensitive resist NR corresponding to the opening bottom 8a, that is, a part of the negative photosensitive resist NR on the positive photosensitive resist PR is removed to remove the positive photosensitive resist NR. The photosensitive resist PR is exposed. For example, the negative photosensitive resist NR is removed by anisotropic etching. In this case, the negative photosensitive resist NR is etched by making the etching ions EI incident perpendicularly to the opening bottom 8a.

  According to anisotropic dry etching such as RIE, the ions for etching enter the through hole 8 perpendicularly, so the negative photosensitive resist NR on the insulating film 7 covering the through hole side wall 8c is removed. Not. That is, the insulating film 7 on the through-hole side wall 8c remains without being removed. Further, since the thickness of the negative photosensitive resist NR on the back surface of the semiconductor substrate 1 is thicker than the thickness of the negative photosensitive resist NR on the positive photosensitive resist PR in the through hole 8, the back surface of the semiconductor substrate 1 is used. The negative photosensitive resist NR remains without being removed by the etching. That is, the insulating film 7 on the back surface of the semiconductor substrate 1 is not removed.

  At this time, if anisotropic etching using oxygen plasma is performed, the ultraviolet light of the plasma is applied to the negative photosensitive resist NR and the positive photosensitive resist PR. As a result, the negative photosensitive resist NR is exposed and insolubilized in the developing solution, and the positive photosensitive resist PR is exposed and solubilized in the developing solution. That is, a part of the negative photosensitive resist NR can be removed by anisotropic etching with oxygen plasma, and the negative photosensitive resist NR and the positive photosensitive resist PR can be exposed.

  When a part of the negative photosensitive resist NR is removed by a method in which the negative photosensitive resist NR and the positive photosensitive resist PR are not exposed, separately, the negative photosensitive resist NR and The positive photosensitive resist PR is exposed. Further, even when a part of the negative photosensitive resist NR is removed by anisotropic etching with oxygen plasma, in order to complete the exposure, the exposure may be separately performed with light such as ultraviolet light. .

  Next, as shown in FIG. 5D, the negative photosensitive resist NR and the positive photosensitive resist PR are developed. At this time, since the negative photosensitive resist NR is insoluble in the developer, it remains as the etching resist ER, and the positive photosensitive resist PR is removed because it is soluble in the developer. As a result, the insulating film covering the opening bottom 8a is exposed. The covering process of the insulating film 7 is completed by the above process.

  The subsequent process of removing the insulating film 7 and the process of forming the wiring 9 are performed in the same manner as in the first embodiment, as shown in FIGS.

  As described above, according to the semiconductor device manufacturing method of the present embodiment, the wiring 9 that is insulated from the semiconductor substrate 1 and electrically connected to the electrode pad 3 can be formed on the semiconductor substrate 1. Thus, a short circuit between the wiring 9 and the semiconductor substrate 1 can be avoided, and a semiconductor device that operates normally can be manufactured. In addition, according to the method for manufacturing a semiconductor device according to the present embodiment, since the light source or the mechanism for rotating the wafer on which the semiconductor substrate 1 is formed as in the first embodiment is not required, the manufacturing apparatus can be downsized. There is also an advantage.

It is sectional drawing of the semi-finished product in each process of the manufacturing method of the semiconductor device by a present Example. It is sectional drawing of the semi-finished product in each process of the manufacturing method of the semiconductor device by a present Example. It is a figure which shows the positional relationship of the semiconductor substrate and light source at the time of resist exposure. It is sectional drawing of the semi-finished product in each process of the manufacturing method of the semiconductor device by a present Example. It is sectional drawing of the semiconductor device in each process of the etching resist formation process by a 2nd Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating layer 3 Electrode pad 4 Protective film 5 Support base 6 Adhesive layer 7 Insulating film 8 Through-hole 9 Wiring 10 Semiconductor device 11 Intermediate product

Claims (10)

A semiconductor substrate; a through hole provided in the semiconductor substrate; an electrode pad formed at an opening bottom of the through hole; and a wiring reaching the surface of the semiconductor substrate from the electrode pad via the through hole A method for manufacturing a semiconductor device including:
An insulating film forming step of forming an insulating film so as to cover the inner wall of the through hole and the surface of the semiconductor substrate;
An etching resist forming step of covering a portion excluding a portion corresponding to the bottom of the opening of the insulating film with an etching resist;
An insulating film removing step for exposing the electrode pad by removing a part of the insulating film by etching using the etching resist as a mask;
A conductive layer forming step of forming a conductive layer as the wiring so as to reach the exposed portion of the electrode pad from the insulating film on the surface of the semiconductor substrate via the through hole. Device manufacturing method. The etching resist forming step includes
A resist coating step of coating a negative photosensitive resist on the insulating film;
An exposure step of exposing a portion excluding a portion corresponding to the bottom of the opening of the negative photosensitive resist;
The semiconductor device according to claim 1, further comprising: a developing step of developing the negative photosensitive resist to obtain the etching resist and exposing a portion of the insulating film covering the bottom of the opening. Manufacturing method.   3. The method of manufacturing a semiconductor device according to claim 2, wherein in the exposure step, an exposure beam is incident obliquely with respect to a depth direction of the through hole. The etching resist forming step includes
A resist deposition step of depositing a positive photosensitive resist on the bottom of the opening;
A resist coating step of coating a negative photosensitive resist on the insulating film and the positive photosensitive resist;
A resist exposure step of exposing the positive photosensitive resist by removing a portion corresponding to the bottom of the opening of the negative photosensitive resist;
An exposure step of exposing the positive photosensitive resist and the negative photosensitive resist;
And developing the positive photosensitive resist and the negative photosensitive resist to obtain the etching resist and exposing a portion of the insulating film covering the bottom of the opening. Item 14. A method for manufacturing a semiconductor device according to Item 1.   5. The method of manufacturing a semiconductor device according to claim 2, wherein, in the resist coating step, the negative photosensitive resist is coated by a spray method.   In the resist coating step, the thickness of the portion of the negative photosensitive resist corresponding to the surface of the semiconductor substrate is applied to be greater than the thickness of the portion of the negative photosensitive resist corresponding to the through hole. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the method is a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the insulating film removing step, at least a part of the insulating film is removed by anisotropic dry etching.   5. The method of manufacturing a semiconductor device according to claim 4, wherein in the resist exposure step, a part of the negative photosensitive resist is removed by anisotropic dry etching.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the anisotropic dry etching is oxygen plasma anisotropic dry etching. Preparing a semiconductor substrate having an electrode pad on the surface;
Forming a through hole that opens the semiconductor substrate from a back surface to expose the electrode pad;
Forming an insulating film so as to cover an inner wall and a bottom surface of the through hole, and a back surface of the semiconductor substrate;
Forming a negative photosensitive resist so as to cover the insulating film;
Removing the insulating film formed on the bottom surface of the through hole by irradiating the resist with exposure light from a tilt angle direction with respect to the depth direction of the through hole and developing;
Forming a conductive layer extending from the insulating film on the back surface of the semiconductor substrate to electrically connect to the electrode pad by extending the inner wall of the through hole;
A method for manufacturing a semiconductor device, comprising:

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