JP2006148003A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Manufacturing method of semiconductor device and semiconductor device Download PDF

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JP2006148003A
JP2006148003A JP2004338909A JP2004338909A JP2006148003A JP 2006148003 A JP2006148003 A JP 2006148003A JP 2004338909 A JP2004338909 A JP 2004338909A JP 2004338909 A JP2004338909 A JP 2004338909A JP 2006148003 A JP2006148003 A JP 2006148003A
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coating film
photosensitive coating
pattern
semiconductor device
photosensitive
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Kenji Kosho
健二 古庄
Moriharu Ishitani
盛治 石谷
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To a method for manufacturing a semiconductor device which can increase processing accuracy when a plurality of step structures are formed in an insulating layer and can reduce the number of processing steps. <P>SOLUTION: The method comprises steps of forming a first photosensitive film 5 coated on a semiconductor substrate; forming a second photosensitive film 6 coated on the first coated film 5 and higher in sensitivity than the first coated film; transferring a first pattern to the first and second coated films 5 and 6 by exposing the structure with light by the use of a first processing mask 7; transferring a second pattern to the second coated film 6 by the use of a second processing mask 8 with such a light exposure quantity as to expose only the second coated film 6 ; and processing the first and second coated films 5 and 6 into different patterns by developing the first and second coated films 5 and 6. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、例えば複数の段差構造を有する半導体装置の製造方法及び半導体装置に関する。   The present invention relates to a method of manufacturing a semiconductor device having a plurality of step structures, for example, and a semiconductor device.

近年、半導体装置の高集積化、高速化に伴い、Ｃｕ多層配線が採用されている。そして、このようなＣｕ多層配線の形成には、一般にデュアルダマシン法が用いられる。すなわち、層間絶縁膜中に予め複数の段差を形成した後、Ｃｕを埋め込み、ＣＭＰ法等により平坦化することにより、配線・コンタクトを同時に形成することができる。   In recent years, Cu multilayer wiring has been adopted as semiconductor devices are highly integrated and speeded up. A dual damascene method is generally used to form such a Cu multilayer wiring. That is, after forming a plurality of steps in the interlayer insulating film in advance, Cu is embedded and planarized by a CMP method or the like, whereby wiring and contacts can be formed simultaneously.

従来このような複数の段差構造は、例えば以下のように形成されている。先ず、図１７に示すように、半導体基板（図示せず）上に形成された層間絶縁膜１０１、コンタクトプラグ１０２、下層配線１０３と、これらの上層に形成された層間絶縁膜１０４上に、感光性塗布膜１０５を塗布、露光してホールパターンを形成し、これをマスクとしてエッチングを行うことにより、下層配線１０３と接続するホールを形成した後、感光性塗布膜１０５を除去する。次いで、図１８に示すように、さらに感光性塗布膜１０６を塗布、露光して配線パターンを形成し、これをマスクとして所定の深さまでエッチングすることにより、配線溝を形成した後、感光性塗布膜１０６を除去して、ホール・配線溝が形成される。   Conventionally, such a plurality of step structures are formed as follows, for example. First, as shown in FIG. 17, a photosensitive film is formed on an interlayer insulating film 101, a contact plug 102, a lower layer wiring 103 formed on a semiconductor substrate (not shown), and an interlayer insulating film 104 formed on the upper layer. The photosensitive coating film 105 is applied and exposed to form a hole pattern, and etching is performed using the hole pattern as a mask to form a hole connected to the lower wiring 103, and then the photosensitive coating film 105 is removed. Next, as shown in FIG. 18, a photosensitive coating film 106 is further applied and exposed to form a wiring pattern, and this is used as a mask to etch to a predetermined depth, thereby forming a wiring groove, and then photosensitive coating. The film 106 is removed to form a hole / wiring groove.

このような従来の方法では、ＰＥＰ（Ｐｈｏｔｏ ｅｔｃｈｉｎｇ ｐｒｏｃｅｓｓ）を複数回繰り返す必要があり、アライメント誤差などにより、加工精度が十分でないという問題があった。そこで、加工精度の向上を図ることが種々検討されている（例えば特許文献１参照）。   In such a conventional method, it is necessary to repeat PEP (Photo etching process) a plurality of times, and there is a problem that processing accuracy is not sufficient due to an alignment error or the like. Therefore, various attempts have been made to improve machining accuracy (see, for example, Patent Document 1).

しかしながら、上述の方法においても、異なるエッチングプロセスを繰り返す等、加工工程が多く、リードタイムの短縮、加工コストの削減が困難であるという問題があった。
特開２０００−１２５３８号公報 However, the above-described method also has a problem that there are many processing steps such as repeating different etching processes, and it is difficult to reduce the lead time and the processing cost.
JP 2000-12538 A

本発明は、絶縁層中に複数の段差を形成する際の加工精度の向上を図るとともに、加工工程数を低減することが可能な半導体装置の製造方法及び半導体装置を提供することを目的とするものである。   It is an object of the present invention to provide a semiconductor device manufacturing method and a semiconductor device capable of improving processing accuracy when forming a plurality of steps in an insulating layer and reducing the number of processing steps. Is.

本発明の一態様によれば、半導体基板上に第１の感光性塗布膜を形成する工程と、前記第１の感光性塗布膜上に、前記第１の感光性塗布膜より感度の高い第２の感光性塗布膜を形成する工程と、第１のマスクを用いて露光を行い、前記第１の感光性塗布膜及び前記第２の感光性塗布膜に前記第１のパターンを転写する工程と、第２のマスクを用いて、前記第２の感光性塗布膜のみ感光する露光量で露光を行い、前記第２の感光性塗布膜に前記第２のパターンを転写する工程と、前記第１の感光性塗布膜及び前記第２の感光性塗布膜を現像し、前記第１の感光性塗布膜と前記第２の感光性塗布膜を異なるパターンに加工する工程を備えることを特徴とする半導体装置の製造方法が提供される。   According to one aspect of the present invention, a step of forming a first photosensitive coating film on a semiconductor substrate, and a first sensitivity higher than that of the first photosensitive coating film on the first photosensitive coating film. A step of forming a second photosensitive coating film, and a step of performing exposure using a first mask to transfer the first pattern to the first photosensitive coating film and the second photosensitive coating film. Using the second mask to perform exposure with an exposure amount that exposes only the second photosensitive coating film, and transferring the second pattern to the second photosensitive coating film; And developing the first photosensitive coating film and the second photosensitive coating film, and processing the first photosensitive coating film and the second photosensitive coating film into different patterns. A method for manufacturing a semiconductor device is provided.

また、本発明の一態様によれば、半導体基板上に第１の感光性塗布膜を形成する工程と、第１のマスクを用いて露光を行い、前記第１の感光性塗布膜及び前記第２の感光性塗布膜に前記第１のパターンを転写、現像し、第１のパターンを形成する工程と、前記第１のパターンの形成された前記第１の感光性塗布膜に、前記第１の感光性塗布膜の感光能力を低下させる表面処理を施す工程と、前記第１の感光性塗布膜上に第２の感光性塗布膜を形成する工程と、第２のマスクを用いて、前記第２の感光性塗布膜のみを露光させ、前記第２の感光性塗布膜に前記第２のパターンを転写する工程と、前記第２の感光性塗布膜を現像し、前記第１のパターンと異なる第２のパターンに加工する工程を備えることを特徴とする半導体装置の製造方法が提供される。   According to another aspect of the present invention, a step of forming a first photosensitive coating film on a semiconductor substrate and exposure using a first mask are performed, and the first photosensitive coating film and the first photosensitive coating film are exposed. Transferring and developing the first pattern to the second photosensitive coating film to form the first pattern; and forming the first pattern on the first photosensitive coating film on which the first pattern is formed. Applying a surface treatment for reducing the photosensitive ability of the photosensitive coating film, forming a second photosensitive coating film on the first photosensitive coating film, and using a second mask, Exposing only the second photosensitive coating film and transferring the second pattern to the second photosensitive coating film; developing the second photosensitive coating film; and There is provided a method of manufacturing a semiconductor device comprising a step of processing into a different second pattern. It is.

また、本発明の一態様によれば、半導体基板上に形成された所定パターンの配線層と、この配線層を下層の所定位置に接続するホールを備え、前記配線層の少なくとも前記ホールの形成された領域の幅方向において、底面がテーパーを有することを特徴とする半導体装置が提供される。   According to another aspect of the present invention, a wiring layer having a predetermined pattern formed on a semiconductor substrate and a hole connecting the wiring layer to a predetermined position on a lower layer are provided, and at least the hole of the wiring layer is formed. There is provided a semiconductor device characterized in that the bottom surface has a taper in the width direction of the region.

本発明の一実施態様によれば、工程数の削減が可能となり、各パターン間における相対的なアライメント精度を向上させることができるとともに、安定した段差を形成することができる。   According to one embodiment of the present invention, the number of steps can be reduced, the relative alignment accuracy between patterns can be improved, and a stable step can be formed.

また、本発明の一実施態様によれば、安定した段差を形成することができるとともに、感光性塗布膜の解像性を向上させることができる。   Moreover, according to one embodiment of the present invention, a stable step can be formed and the resolution of the photosensitive coating film can be improved.

さらに、本発明の一実施態様によれば、コンタクトプラグ／配線底面をテーパー状に加工することができ、その内部に形成されるコンタクトプラグ／配線膜中の欠陥を抑えることが可能となる。   Furthermore, according to one embodiment of the present invention, the contact plug / wiring bottom can be processed into a tapered shape, and defects in the contact plug / wiring film formed therein can be suppressed.

以下本発明の実施形態について、図を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

（実施形態１）
図１乃至図５に本実施形態の半導体装置の製造工程を示す。 (Embodiment 1)
1 to 5 show a manufacturing process of the semiconductor device of this embodiment.

図１に示すように、能動素子領域の形成された半導体基板（図示せず）上に、ＮＳＧ（Ｎｏｎｄｏｐｅｄ ｓｉｌｉｃａｔｅ ｇｌａｓｓ）層１ａ／ＴＥＯＳ層１ｂ／Ｐ−ＳｉＨ４（プラズマシラン（ＳｉＯ２））層１ｃからなる層間絶縁膜１を形成する。次いで、層間絶縁膜１の所定位置に、能動素子、或いは下層配線等の所定領域に到達するＴｉＮ層２ａ／Ｗ層２ｂからなるコンタクトプラグ２と、これと接するＣｕ配線層３を形成する。そして、これらの上層にＳｉＮ層４ａ／ＴＥＯＳ層４ｂからなる層間絶縁膜４を形成する。 As shown in FIG. 1, an NSG (Nondoped Silicate Glass) layer 1a / TEOS layer 1b / P-SiH 4 (plasma silane (SiO 2 )) layer is formed on a semiconductor substrate (not shown) in which an active element region is formed. An interlayer insulating film 1 made of 1c is formed. Next, a contact plug 2 composed of a TiN layer 2a / W layer 2b reaching a predetermined region such as an active element or a lower layer wiring and a Cu wiring layer 3 in contact therewith are formed at a predetermined position of the interlayer insulating film 1 . Then, an interlayer insulating film 4 composed of the SiN layer 4a / TEOS layer 4b is formed on these layers.

次いで、図２に示すように、アクリル系樹脂からなる化学増幅型レジストを塗布し、第1の感光性塗布膜５を形成する。そして、この上層に、より感度の高いフェノール系樹脂からなる化学増幅型レジストを塗布し、第2の感光性塗布膜６を形成する。   Next, as shown in FIG. 2, a chemically amplified resist made of an acrylic resin is applied to form a first photosensitive coating film 5. Then, a chemically amplified resist made of a phenolic resin with higher sensitivity is applied to the upper layer to form a second photosensitive coating film 6.

そして、図３に示すように、加工マスク７を用いて露光し、第１の感光性塗布膜５、第2の感光性塗布膜６第双方に第１のパターンを転写する（感光部５ａ、６ａ）。   Then, as shown in FIG. 3, exposure is performed using a processing mask 7, and the first pattern is transferred to both the first photosensitive coating film 5 and the second photosensitive coating film 6 (photosensitive portion 5a, 6a).

次いで、図４に示すように、加工マスク８を用いて、今度は第2の感光性塗布膜６のみが感光する露光量にて露光し、第2の感光性塗布膜６に第２のパターンを転写する（感光部６ｂ）。   Next, as shown in FIG. 4, using the processing mask 8, this time, the second photosensitive coating film 6 is exposed with an exposure amount that only the second photosensitive coating film 6 is exposed. Is transferred (photosensitive portion 6b).

さらに、これを現像することにより、第１の感光性塗布膜５、第2の感光性塗布膜６を、図５に示すような段差形状とする（第１の感光性塗布膜５’、第２の感光性塗布膜６’）。   Further, by developing this, the first photosensitive coating film 5 and the second photosensitive coating film 6 have a step shape as shown in FIG. 5 (first photosensitive coating film 5 ′, first photosensitive coating film 5 ′, 2 photosensitive coating film 6 ').

このように、１回の現像工程で、複数の段差を有する感光性塗布膜を形成することできるため、工程数の削減が可能となる。また、基板のアライメントが１回で済むため、各パターン間における相対的なアライメント精度を向上させることができる。また、第２のパターンを形成する際、第１の感光性塗布膜５が第２の感光性塗布膜６の露光時に現像されないため、安定した段差を形成することができる。   Thus, since the photosensitive coating film having a plurality of steps can be formed in one development step, the number of steps can be reduced. Further, since alignment of the substrate only needs to be performed once, the relative alignment accuracy between the patterns can be improved. Further, when the second pattern is formed, the first photosensitive coating film 5 is not developed during the exposure of the second photosensitive coating film 6, so that a stable step can be formed.

本実施形態において第１の感光性塗布膜５、第2の感光性塗布膜６に形成された段差を用いて、例えばそのままエッチングを行うことにより、下層のコンタクトプラグ２／Ｃｕ配線３に到達するデュアルダマシン配線を形成することができる。また、第１の感光性塗布膜５、第2の感光性塗布膜６を除去せずそのまま硬化させて、段差形状の層間絶縁膜として用いることも可能である。 In this embodiment, the step formed in the first photosensitive coating film 5 and the second photosensitive coating film 6 is used, for example, to perform etching as it is to reach the lower contact plug 2 / Cu wiring 3. Dual damascene wiring can be formed. Further, the first photosensitive coating film 5 and the second photosensitive coating film 6 can be cured as they are without being removed and used as a step-shaped interlayer insulating film.

尚、本実施形態において、第１の感光性塗布膜５、第２の感光性塗布膜６に、浅い開口部内に深い開口部を形成して段差形状の開口部を形成しているが、各開口部の位置関係は特に限定されるものではなく、図６に示すように、第１の感光性塗布膜１５、第２の感光性塗布膜１６における浅い開口部と深い開口部を、それぞれ異なる場所に形成することも可能である。   In the present embodiment, the first photosensitive coating film 5 and the second photosensitive coating film 6 are formed with stepped openings by forming deep openings in shallow openings. The positional relationship of the openings is not particularly limited. As shown in FIG. 6, the shallow openings and the deep openings in the first photosensitive coating film 15 and the second photosensitive coating film 16 are different from each other. It can also be formed in place.

そして、図７に示すように、このような形状の第１の感光性塗布膜１５、第２の感光性塗布膜１６をマスクとしてイオン注入を行うことにより、半導体基板１７に深さの異なる不純物領域１８ａ、１８ｂを形成することができる。   Then, as shown in FIG. 7, by performing ion implantation using the first photosensitive coating film 15 and the second photosensitive coating film 16 having such shapes as masks, impurities having different depths are formed in the semiconductor substrate 17. Regions 18a and 18b can be formed.

このようにして、半導体基板中に深さの異なる不純物領域形成する際、ＰＥＰ等を繰り返し行う必要がないとともに、アライメント精度／解像性の高いマスクを形成できるため、精度よく不純物領域を形成することが可能となる。また、感光性塗布膜の分子量を上下層で適宜選択することにより、不純物濃度の異なる領域を同様に形成することも可能である。   In this way, when forming impurity regions having different depths in the semiconductor substrate, it is not necessary to repeatedly perform PEP and the like, and a mask with high alignment accuracy / resolution can be formed, so that the impurity regions are formed with high accuracy. It becomes possible. It is also possible to similarly form regions having different impurity concentrations by appropriately selecting the molecular weight of the photosensitive coating film between the upper and lower layers.

尚、本実施形態において、段差を２段としているが、３段以上の多段構造も形成可能である。また、感光性塗布膜は、ネガ型、ポジ型のいずれを用いることも可能である。また、第１の感光性塗布膜５、１５、第2の感光性塗布膜６、１６に化学増幅型レジストを用いているが、これに限定されるものではなく、公知の感光性樹脂を用いることができる。また、加工マスクも特に限定されるものではなく、公知のフォトマスクを用いることができ、位相シフト法によるハーフトーンマスクを用いて露光することにより、第１、第２のパターンを同時に転写することも可能である。   In this embodiment, the step is two steps, but a multi-step structure having three or more steps can also be formed. The photosensitive coating film can be either a negative type or a positive type. Moreover, although the chemically amplified resist is used for the first photosensitive coating films 5 and 15 and the second photosensitive coating films 6 and 16, the invention is not limited to this, and a known photosensitive resin is used. be able to. Further, the processing mask is not particularly limited, and a known photomask can be used, and the first and second patterns can be simultaneously transferred by exposure using a halftone mask by a phase shift method. Is also possible.

（実施形態２）
図８乃至図１２に本実施形態の半導体装置の製造工程を示す。 (Embodiment 2)
8 to 12 show the manufacturing process of the semiconductor device of this embodiment.

図８に示すように、実施形態１と同様に、能動素子領域の形成された半導体基板（図示せず）上に、ＮＳＧ層２１ａ／ＴＥＯＳ層２１ｂ／Ｐ−ＳｉＨ４層２１ｃからなる層間絶縁膜２１、ＴｉＮ層２２ａ／Ｗ層２２ｂからなるコンタクトプラグ２２及びＣｕ配線２３と、これらの上層にＳｉＮ層２４ａ／ＴＥＯＳ層２４ｂからなる層間絶縁膜２４を形成し、これらの上層に、ＰｅｇｍｅａとＰｅｇｍｅの混合溶剤に溶解したノボラック系樹脂を塗布し、第１の感光性塗布膜２５を形成する。 As shown in FIG. 8, as in the first embodiment, an interlayer insulating film composed of an NSG layer 21a / TEOS layer 21b / P-SiH 4 layer 21c on a semiconductor substrate (not shown) on which an active element region is formed. 21 , a contact plug 22 and a Cu wiring 23 made of a TiN layer 22a / W layer 22b, and an interlayer insulating film 24 made of a SiN layer 24a / TEOS layer 24b are formed on these layers, and Pegmea and Pegme are formed on these layers. A novolac resin dissolved in a mixed solvent is applied to form a first photosensitive coating film 25.

次いで、図９に示すように、第１の加工マスクを用いて露光し、感光性塗布膜２５に第１のパターンを転写、現像し、第１の感光性塗布膜２５を第１のパターンに加工する（感光性塗布膜２５’）。   Next, as shown in FIG. 9, exposure is performed using a first processing mask, the first pattern is transferred and developed on the photosensitive coating film 25, and the first photosensitive coating film 25 is converted into the first pattern. Processing (photosensitive coating film 25 ').

そして、図１０に示すように、このパターンの形成された第１の感光性塗布膜２５’表面をＵＶｂａｋｅによりＣｕｒｅ処理する（Ｃｕｒｅ処理された領域２５ａ’）。このＣｕｒｅ処理により第１の感光性塗布膜２５’の感光能力を低下させることができる。尚、第１の感光性塗布膜２５の表面のみのＣｕｒｅ処理であるので、高温・長時間での処理は不要であり、能動素子への影響は抑えられる。そして、図１１に示すように、同じ材料からなる第２の感光性塗布膜２６を形成する。尚、第２の感光性塗布膜２６は、第１の感光性塗布膜２５と異なるものを用いてもよい。   Then, as shown in FIG. 10, the surface of the first photosensitive coating film 25 'on which this pattern has been formed is cured by UV bake (Cure-processed region 25a'). By this cure process, the photosensitive ability of the first photosensitive coating film 25 ′ can be reduced. Since only the surface of the first photosensitive coating film 25 is cure processing, processing at a high temperature and a long time is unnecessary, and the influence on the active element can be suppressed. Then, as shown in FIG. 11, a second photosensitive coating film 26 made of the same material is formed. Note that the second photosensitive coating film 26 may be different from the first photosensitive coating film 25.

次いで、図１２に示すように、第２の加工マスクを用いて、今度は第２の感光性塗布膜２６のみが感光する露光量にて露光し、第２の感光性塗布膜２６に第２のパターンを転写する。そして、これを現像し、第２の感光性塗布膜２６を、第１のパターンと異なる第２のパターンに加工（第２の感光性塗布膜２６’）することにより、第１の感光性塗布膜２５、第２の感光性塗布膜２６に段差を形成する。   Next, as shown in FIG. 12, using the second processing mask, this time, the second photosensitive coating film 26 is exposed to an exposure amount that only the second photosensitive coating film 26 is exposed. The pattern is transferred. Then, this is developed, and the second photosensitive coating film 26 is processed into a second pattern different from the first pattern (second photosensitive coating film 26 ′), whereby the first photosensitive coating film is formed. Steps are formed in the film 25 and the second photosensitive coating film 26.

尚、本実施例においては、第１の感光性塗布膜２５’の表面をＣｕｒｅ処理することにより、第１の感光性塗布膜２５’の感光能力を低下させたが、感光能力を低下させる処理であれば、Ｃｕｒｅ処理に限定されるものではなく、例えば第１の感光性塗布膜２５’の表面に、露光波長の光の透過を抑える薄膜を形成しても良い。   In the present embodiment, the surface of the first photosensitive coating film 25 ′ is cured to reduce the photosensitive ability of the first photosensitive coating film 25 ′. If so, the present invention is not limited to cure processing. For example, a thin film that suppresses transmission of light having an exposure wavelength may be formed on the surface of the first photosensitive coating film 25 ′.

このように、第１の感光性塗布膜２５にパターンを形成した後、その表面をＣｕｒｅすることにより、第２の感光性塗布膜２６露光時の第１の感光性塗布膜２５の感光を抑えることができるので、安定した段差を有する第１の感光性塗布膜２５’、第２の感光性塗布膜２６’を形成することができる。また、第２の感光性塗布膜２６を塗布する際、第１の感光性塗布膜２５’とのインターミキシングを低減することができ、第２の感光性塗布膜２６の解像性を向上させることができる。   As described above, after the pattern is formed on the first photosensitive coating film 25, the surface thereof is cured, thereby suppressing the first photosensitive coating film 25 from being exposed during the exposure of the second photosensitive coating film 26. Therefore, the first photosensitive coating film 25 ′ and the second photosensitive coating film 26 ′ having stable steps can be formed. Further, when the second photosensitive coating film 26 is applied, intermixing with the first photosensitive coating film 25 ′ can be reduced, and the resolution of the second photosensitive coating film 26 is improved. be able to.

本実施形態において第１の感光性塗布膜２５、第２の感光性塗布膜２６に形成された段差を用いて、例えばそのままエッチングを行うことにより、下層のコンタクトプラグ２２／Ｃｕ配線２３に到達するデュアルダマシン配線を形成することができる。また、第１の感光性塗布膜２５’、第2の感光性塗布膜２６’を除去せずそのまま硬化させて、段差形状の層間絶縁膜として用いることも可能である。 In this embodiment, by using the steps formed in the first photosensitive coating film 25 and the second photosensitive coating film 26, for example, etching is performed as it is to reach the lower contact plug 22 / Cu wiring 23. Dual damascene wiring can be formed. Also, the first photosensitive coating film 25 ′ and the second photosensitive coating film 26 ′ can be cured as they are without being removed, and used as a step-shaped interlayer insulating film.

尚、本実施形態において、第１の感光性塗布膜２５、第２の感光性塗布膜２６に、浅い開口部内に深い開口部を形成して段差形状の開口部を形成しているが、各開口部の位置関係は特に限定されるものではなく、実施形態１と同様に、浅い開口部と深い開口部を、それぞれ異なる場所に形成することも可能である。そして、実施形態１と同様に、さらに第１の感光性塗布膜２５’、第２の感光性塗布膜２６’をマスクとしてイオン注入を行うことにより、深さや濃度の異なる不純物領域を形成することができる。   In the present embodiment, the first photosensitive coating film 25 and the second photosensitive coating film 26 are formed with deep openings in shallow openings to form step-shaped openings. The positional relationship of the openings is not particularly limited, and it is possible to form the shallow openings and the deep openings in different places as in the first embodiment. Then, similarly to the first embodiment, ion implantation is further performed using the first photosensitive coating film 25 ′ and the second photosensitive coating film 26 ′ as a mask to form impurity regions having different depths and concentrations. Can do.

また、本実施形態において、段差を２段としているが、３段以上の多段構造も形成可能である。また、感光性塗布膜は、ネガ型、ポジ型のいずれを用いることも可能である。   Moreover, in this embodiment, although the level | step difference is 2 steps | paragraphs, the multistage structure of 3 steps | paragraphs or more can be formed. The photosensitive coating film can be either a negative type or a positive type.

（実施形態３）
本実施形態は、実施形態１の手法により形成された感光性塗布膜の段差を用いて、さらに下層の層間絶縁膜を加工し、デュアルダマシン配線を形成するものである。 (Embodiment 3)
In the present embodiment, the lower interlayer insulating film is processed using the steps of the photosensitive coating film formed by the method of the first embodiment to form dual damascene wiring.

図１３に示すように、実施形態１と同様に、能動素子領域の形成された半導体基板（図示せず）上に、ＮＳＧ層３１ａ／ＴＥＯＳ層３１ｂ／Ｐ−ＳｉＨ４層３１ｃからなる層間絶縁膜３１が形成されており、その所定位置に、能動素子、或いは下層配線等の所定領域に到達するＴｉＮ層３２ａ／Ｗ層３２ｂからなるコンタクトプラグ３２と、これと接するＣｕ配線層３３が形成されている。そして、これらの上層にＳｉＮ層３４ａ／ＴＥＯＳ層３４ｂからなる層間絶縁膜３４が形成されている。そして、実施形態１と同様に、第１の感光性塗布膜３５、第２の感光性塗布膜３６が塗布され、段差を形成される。 As shown in FIG. 13, as in the first embodiment, an interlayer insulating film composed of an NSG layer 31a / TEOS layer 31b / P-SiH 4 layer 31c on a semiconductor substrate (not shown) on which an active element region is formed. 31 is formed, and a contact plug 32 comprising a TiN layer 32a / W layer 32b reaching a predetermined region such as an active element or a lower layer wiring and a Cu wiring layer 33 in contact therewith are formed at a predetermined position. Yes. An interlayer insulating film 34 composed of a SiN layer 34a / TEOS layer 34b is formed on these layers. Then, as in the first embodiment, the first photosensitive coating film 35 and the second photosensitive coating film 36 are applied to form steps.

次いで、ＲＩＥ(Ｒｅａｃｔｉｖｅ ｉｏｎ ｅｔｃｈｉｎｇ)等公知のエッチング方法により、第１の感光性塗布膜３５、第２の感光性塗布膜３６を除去するとともに、第１の感光性塗布膜３５、第２の感光性塗布膜３６をマスクとして層間絶縁膜３４をエッチングする。このとき、第１の感光性塗布膜３５、第２の感光性塗布膜３６及び層間絶縁膜３４のエッチング選択比はほぼ１となるように設定される場合、例えば図１４に示すように、第１の感光性塗布膜３５、第２の感光性塗布膜３６に形成された段差のまま加工され（層間絶縁膜３４’）が、下層のＣｕ配線層３３と接続されるが、夫々のエッチング選択比は適宜設定することが可能である。そして、図１５に示すように、Ｓｅｅｄ−Ｃｕ膜３９ａ、Ｃｕ膜３９ｂを順次形成後、ＣＭＰなどにより平坦化され、層間絶縁膜３４’中形成された段差中にＣｕ等からなるコンタクトプラグ／配線３９が形成される。 Next, the first photosensitive coating film 35 and the second photosensitive coating film 36 are removed and the first photosensitive coating film 35 and the second photosensitive coating film 36 are removed by a known etching method such as RIE (Reactive ion etching). The interlayer insulating film 34 is etched using the conductive coating film 36 as a mask. At this time, when the etching selectivity of the first photosensitive coating film 35, the second photosensitive coating film 36, and the interlayer insulating film 34 is set to be approximately 1, for example, as shown in FIG. Although the steps (interlayer insulating film 34 ') formed in the first photosensitive coating film 35 and the second photosensitive coating film 36 are processed as they are and are connected to the lower Cu wiring layer 33, the respective etching options are selected. The ratio can be set as appropriate. Then, as shown in FIG. 15, a seed-Cu film 39a and a Cu film 39b are sequentially formed, planarized by CMP or the like, and contact plugs / wiring made of Cu or the like in a step formed in the interlayer insulating film 34 ′. 39 is formed.

また、エッジ部のエッチングが進行することにより、図１６に示すように、ビアホールの形成される配線溝底面（破線で囲まれた領域）をテーパー状に加工することができる。このように、少なくとも配線底面の幅方向がテーパー状になるように、層間絶縁膜３４”を加工することにより、この内部に同様にコンタクトプラグ／配線３９’を形成する際のＣｕ等のカバレッジを向上させることができる。 Further, as the etching of the edge portion proceeds, as shown in FIG. 16, the bottom surface of the wiring groove where the via hole is formed (region surrounded by the broken line) can be processed into a taper shape. Thus, by processing the interlayer insulating film 34 ″ so that at least the width direction of the bottom surface of the wiring is tapered, the coverage of Cu or the like when the contact plug / wiring 39 ′ is similarly formed therein is provided. Can be improved.

このようにして、実施形態１の手法により形成された段差形状の第１の感光性塗布膜３５、第２の感光性塗布膜３６の下層の層間絶縁膜３４を、第１の感光性塗布膜３５、第２の感光性塗布膜３６とともにそのままエッチングすることにより段差形状に加工することができる。さらに、配線底面をテーパー状に加工することにより、その内部に形成されるコンタクトプラグ／配線膜中の欠陥を抑えることが可能となる。   In this way, the step-shaped first photosensitive coating film 35 and the interlayer insulating film 34 below the second photosensitive coating film 36 formed by the method of Embodiment 1 are used as the first photosensitive coating film. 35, by etching as it is together with the second photosensitive coating film 36, it can be processed into a stepped shape. Further, by processing the bottom surface of the wiring into a tapered shape, it is possible to suppress defects in the contact plug / wiring film formed inside the wiring.

尚、同様に、実施形態２の手法により形成された段差形状の第１の感光性塗布膜２５’、第2の感光性塗布膜２６’を用いて、下層の層間絶縁膜２４を段差形状に加工することができる。   Similarly, the lower interlayer insulating film 24 is formed into a step shape using the step-shaped first photosensitive coating film 25 ′ and the second photosensitive coating film 26 ′ formed by the method of the second embodiment. Can be processed.

尚、本発明は、上述した実施形態に限定されるものではない。その他要旨を逸脱しない範囲で種々変形して実施することができる。   In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the semiconductor device of one embodiment of this invention. 本発明の一実施態様の半導体装置における配線構造を示す図。The figure which shows the wiring structure in the semiconductor device of one embodiment of this invention. 従来の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the conventional semiconductor device. 従来の半導体装置の製造工程を示す図。The figure which shows the manufacturing process of the conventional semiconductor device.

符号の説明Explanation of symbols

１、４、２４、３４、３４’、３４”、１０４ 層間絶縁膜
２、２２、３２、１０２ コンタクトプラグ
３、２３、３３、１０３ Ｃｕ配線層
５、６、５’、６’、１５、１６、２５、２６、２５’、２６’、３５、３６、１０５、１０６ 感光性塗布膜
７、８ 加工マスク
１７ 半導体基板
１８ 不純物領域
３９、３９’ コンタクトプラグ／配線 1, 4, 24, 34, 34 ', 34 ", 104 Interlayer insulating film 2, 22, 32, 102 Contact plug 3, 23, 33, 103 Cu wiring layers 5, 6, 5', 6 ', 15, 16 25, 26, 25 ′, 26 ′, 35, 36, 105, 106 Photosensitive coating film 7, 8 Processing mask 17 Semiconductor substrate 18 Impurity region 39, 39 ′ Contact plug / wiring

Claims (5)

半導体基板上に第１の感光性塗布膜を形成する工程と、
前記第１の感光性塗布膜上に、前記第１の感光性塗布膜より感度の高い第２の感光性塗布膜を形成する工程と、
第１のマスクを用いて露光を行い、前記第１の感光性塗布膜及び前記第２の感光性塗布膜に前記第１のパターンを転写する工程と、
第２のマスクを用いて、前記第２の感光性塗布膜のみ感光する露光量で露光を行い、前記第２の感光性塗布膜に前記第２のパターンを転写する工程と、
前記第１の感光性塗布膜及び前記第２の感光性塗布膜を現像し、前記第１の感光性塗布膜と前記第２の感光性塗布膜を異なるパターンに加工する工程を備えることを特徴とする半導体装置の製造方法。 Forming a first photosensitive coating film on a semiconductor substrate;
Forming a second photosensitive coating film having higher sensitivity than the first photosensitive coating film on the first photosensitive coating film;
Performing exposure using a first mask and transferring the first pattern to the first photosensitive coating film and the second photosensitive coating film;
Using the second mask to perform exposure with an exposure amount that exposes only the second photosensitive coating film, and transferring the second pattern to the second photosensitive coating film;
And developing the first photosensitive coating film and the second photosensitive coating film, and processing the first photosensitive coating film and the second photosensitive coating film into different patterns. A method for manufacturing a semiconductor device. 半導体基板上に第１の感光性塗布膜を形成する工程と、
第１のマスクを用いて露光を行い、前記第１の感光性塗布膜及び前記第２の感光性塗布膜に前記第１のパターンを転写、現像し、第１のパターンを形成する工程と、
前記第１のパターンの形成された前記第１の感光性塗布膜に、前記第１の感光性塗布膜の感光能力を低下させる表面処理を施す工程と、
前記第１の感光性塗布膜上に第２の感光性塗布膜を形成する工程と、
第２のマスクを用いて、前記第２の感光性塗布膜のみを露光させ、前記第２の感光性塗布膜に前記第２のパターンを転写する工程と、
前記第２の感光性塗布膜を現像し、前記第１のパターンと異なる第２のパターンに加工する工程を備えることを特徴とする半導体装置の製造方法。 Forming a first photosensitive coating film on a semiconductor substrate;
Performing exposure using a first mask, transferring and developing the first pattern to the first photosensitive coating film and the second photosensitive coating film, and forming a first pattern;
Performing a surface treatment on the first photosensitive coating film on which the first pattern is formed to reduce the photosensitive ability of the first photosensitive coating film;
Forming a second photosensitive coating film on the first photosensitive coating film;
Exposing only the second photosensitive coating film using a second mask, and transferring the second pattern to the second photosensitive coating film;
A method of manufacturing a semiconductor device, comprising: developing the second photosensitive coating film and processing the second photosensitive coating film into a second pattern different from the first pattern. パターンの形成された第１、第２の感光性塗布膜をエッチングするとともに、第１、第２の感光性塗布膜をマスクとして前記第１の感光性塗布膜の下層をエッチングし、段差構造を形成する工程を備えることを特徴とする請求項１又は２に記載の半導体装置の製造方法。   The first and second photosensitive coating films on which the pattern is formed are etched, and the lower layer of the first photosensitive coating film is etched using the first and second photosensitive coating films as a mask to form a step structure. The method for manufacturing a semiconductor device according to claim 1, further comprising a forming step. パターンの形成された第１、第２の感光性塗布膜をマスクとしてイオン注入する工程を備えることを特徴とする請求項１又は２に記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of ion implantation using the first and second photosensitive coating films on which the pattern is formed as a mask. 半導体基板上に形成された所定パターンの配線層と、
この配線層を下層の所定位置に接続するホールを備え、
前記配線層の少なくとも前記ホールの形成された領域の幅方向において、底面がテーパーを有することを特徴とする半導体装置。 A wiring layer having a predetermined pattern formed on the semiconductor substrate;
With a hole that connects this wiring layer to a predetermined position in the lower layer,
The semiconductor device according to claim 1, wherein a bottom surface of the wiring layer has a taper in a width direction of at least the region where the hole is formed.
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JP2008153390A (en) * 2006-12-15 2008-07-03 Toyota Motor Corp Method and system for forming impurity implanted region
JP2012208350A (en) * 2011-03-30 2012-10-25 Lapis Semiconductor Co Ltd Method for forming resist pattern, method for manufacturing three-dimensional structure and method for manufacturing semiconductor device
JP2018180416A (en) * 2017-04-19 2018-11-15 キヤノン株式会社 Method for manufacturing semiconductor device and semiconductor device
JP2021005739A (en) * 2014-12-27 2021-01-14 マクセルホールディングス株式会社 Semiconductor device substrate and manufacturing method thereof, and semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008153390A (en) * 2006-12-15 2008-07-03 Toyota Motor Corp Method and system for forming impurity implanted region
JP2012208350A (en) * 2011-03-30 2012-10-25 Lapis Semiconductor Co Ltd Method for forming resist pattern, method for manufacturing three-dimensional structure and method for manufacturing semiconductor device
JP2021005739A (en) * 2014-12-27 2021-01-14 マクセルホールディングス株式会社 Semiconductor device substrate and manufacturing method thereof, and semiconductor device
JP2018180416A (en) * 2017-04-19 2018-11-15 キヤノン株式会社 Method for manufacturing semiconductor device and semiconductor device

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