JP2010109167A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein wiring resistance in a horizontal direction by routing of an electrode becomes nonuniform within a chip and current capacity cannot be increased because a first-layer emitter electrode is disposed at a lower portion of a second-layer base electrode and a first-layer base electrode is disposed at a lower portion of a second-layer emitter electrode, in a discrete-type bipolar transistor having a double-layer electrode structure. <P>SOLUTION: In a semiconductor device, a base region is connected to a first-layer first base electrode 6 via a first contact hole CH1, and the first base electrode is connected to a second-layer second base electrode 16 via a first through-hole CH1 or a second through-hole CH2. An emitter region is connected to a first-layer first emitter electrode via a second contact hole, and the first emitter electrode is connected to a third-layer second emitter electrode via the second opening of the second base electrode and a third through-hole, thus nearly uniformly reducing variations in the wiring resistance of each cell. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of realizing a large current and low saturation voltage of a transistor.

  As a discrete bipolar transistor, there is known a bipolar transistor in which a base electrode and an emitter electrode are arranged in two layers on an operation region composed of a lattice-shaped emitter region and an island-shaped base region (see, for example, Patent Document 1). ).

  A conventional semiconductor device 100 will be described with reference to FIGS. 8 and 9 by taking an npn bipolar transistor as an example.

  FIG. 8 is a plan view of the entire semiconductor device (bipolar transistor) 100, FIG. 8A is a diagram showing the first layer electrode, and FIG. 8B is a diagram showing the second layer electrode. It is. In FIG. 8B, the first layer electrode is indicated by a broken line. 9 is a cross-sectional view, FIG. 9A is a cross-sectional view taken along line cc in FIG. 8B, and FIG. 9B is a cross-sectional view taken along line dd in FIG. 8B. is there.

  Referring to FIG. 8, bipolar transistor 100 includes a first base electrode 56 and a first emitter electrode 57, which are first layer electrodes, on a substrate surface (FIG. 8A), and an insulating film thereon. It has a two-layer electrode structure in which a second base electrode 66 and a second emitter electrode 67 which are second-layer electrodes are provided via (not shown).

  Referring to FIGS. 8 and 9, for example, an n − type semiconductor layer 51 b is stacked on an n + type silicon semiconductor substrate 51 a to provide a collector region. A base region 53 which is a p-type impurity region is provided on the surface of the n− type semiconductor layer 51b, and an emitter region 54 is formed on the surface of the base region 53 by diffusing n + type impurities in a lattice shape. As a result, the base regions 53 are separated into island shapes and are alternately arranged with the emitter regions 54. It is to be noted that the island structure is separated from the surface structure, and the base region 53 formed deeper than the emitter region 54 is one continuous region in a deep region. A transistor formed of the base region 53 divided into islands and the emitter region 54 around the island region is hereinafter referred to as a cell, and a region where a large number of cells are disposed is referred to as an operation region 58.

  The base electrode of the first layer connected to the base region 53 includes an island-shaped first base electrode 56a and a strip-shaped first base electrode 56b, and the base electrode is connected via a contact hole CH1 ′ provided in the first insulating film 61. Contact with region 53. In the first row, the second row, the fifth row, and the sixth row in FIG. 8A, the island-shaped first base electrode 56a and the strip-shaped first base electrode 56b are respectively divided into regions that bisect the operation region 58 at the center. Be placed. Further, a frame-like base electrode 56f is provided on the outer periphery, and a shield metal 59 is provided on the outer side thereof. An annular 55 is provided below the shield metal 59.

  The first emitter electrode 57 is provided in a lattice shape between the first base electrodes 56 a and 56 b and is in contact with the emitter region 54 through a contact hole CH <b> 2 ′ provided in the first insulating film 61.

  A second insulating film 62 is provided on the first base electrodes 56a and 56b and the first emitter electrode 57, and further, a flat plate-like second base electrode 66 and second emitter electrode 67 which are the second layers are provided thereon. It is done. The second base electrode 66 is in contact with the end portions of the island-shaped first base electrode 56a and the strip-shaped first base electrode 56b through the through holes TH1 ′ provided in the second insulating film 62 (FIG. 9 ( A)).

The second emitter electrode 67 is in contact with the first emitter electrode 57 through a through hole TH2 ′ provided in the second insulating film 62 (FIG. 9B). A bonding wire (not shown) such as gold (Au) is connected to the flat second base electrode 66 and the second emitter electrode 67.
JP 2000-40703 A

  In the above bipolar transistor, the base electrode and the emitter electrode each have a two-layer structure, and due to the influence of the wiring resistance of the first layer electrode leading to the second layer electrode, each transistor cell cannot operate uniformly, The capacity is small.

  Specifically, referring to FIG. 9A, a strip-shaped first base electrode 56b of the first layer is disposed below the second emitter electrode 67 of the second layer, and below the second emitter electrode 67. The base region 53 is wired by the first base electrode 56b and connected to the second base electrode 66 to which the bonding wire is fixed. On the other hand, an island-shaped first base electrode 56 a is disposed immediately below the second base electrode 66. That is, the wiring resistance Rb ′ of the base current flowing through the base region 53 wired by the first base electrode 56b has a substrate surface compared to the base current flowing through the base region 53 wired by the island-shaped first base electrode 56a. In contrast, a horizontal wiring resistance R is added, and the base current decreases as the distance from the second base electrode 66 increases.

  Referring to FIG. 9B, a first emitter electrode 57 of the first layer is disposed below the second base electrode 66 of the second layer, and the emitter region 54 below the second base electrode 66 is the first emitter electrode 57. It is wired with one emitter electrode 57 and connected to a second emitter electrode 67 to which a bonding wire is fixed. That is, in this cross section, the wiring resistance R in the horizontal direction with respect to the substrate surface is added to the wiring resistance Re ′ of the emitter current, and the emitter current decreases as the distance from the second emitter electrode 67 increases.

  As described above, the transistor cells in the operation region cannot operate uniformly due to the non-uniform wiring resistance, and the emitter current does not flow easily in the cell in which the on-resistance is increased without much base current flowing, There is a problem that the current capacity per unit area is limited.

  The present invention has been made in view of the above-described various problems, and includes a one-conductivity-type semiconductor substrate serving as a collector region, a plurality of opposite-conductivity-type base regions provided on the substrate and spaced apart from each other, An emitter region of one conductivity type provided around the base region, a first insulating film covering the surface of the substrate, and a first contact hole provided in the first insulating film and exposing the base region and the emitter region, respectively. And a second contact hole, a first base electrode that is in contact with the base region via the first contact hole, and a flat first plate that is in contact with the emitter region via the second contact hole. An emitter electrode; a second insulating film covering the first base electrode and the first emitter electrode; and a second insulating film provided on the second insulating film, A first through hole and a second through hole through which the first electrode is exposed; and the first through hole and the second through hole are provided on the second insulating film so as to cover the first through hole and the first through hole. One flat second base electrode connected to the base electrode, a third insulating film provided on the second base electrode, and a plurality of second electrodes provided on the third insulating film and the second insulating film A plate-like second emitter electrode provided on the third insulating film so as to cover the third through-hole and connected to the first emitter electrode through the third through-hole, It solves by having.

  According to the present invention, the following effects can be obtained.

  Since all the cells in the chip have substantially the same electrode structure, it is possible to prevent the wiring resistance from becoming uneven. Thereby, each cell can be operated uniformly, avoiding thermal runaway due to current concentration and widening the safe operating area (ASO: Area of Safe Operating). That is, since the current capacity per unit area can be increased, for example, when the same chip size is maintained, a large current and a low saturation voltage can be achieved.

  Further, in the case of the same collector current Ic rating, it is possible to reduce the chip size by an increase in current capacity per unit area, thereby realizing cost reduction. Further, the switching speed can be increased by reducing the chip size.

  The embodiment of the present invention will be described in detail with reference to FIGS. In the present embodiment, an npn bipolar transistor having a discrete element will be described as an example of the semiconductor device 10.

  The semiconductor device 10 of this embodiment includes a one-conductivity type semiconductor substrate 1, a base region 3, an emitter region 4, a first insulating film 21, a first contact hole CH 1, a second contact hole CH 2, The base electrode 6, the first emitter electrode 7, the second insulating film 22, the first through hole TH1, the second through hole TH2, the second base electrode 16, the third insulating film 23, and the third through A hole TH3 and a second emitter electrode 17 are provided.

  FIG. 1 is a plan view showing the structure of the semiconductor device 10 of this embodiment. FIG. 1 is a schematic view showing the structure of the electrodes of the semiconductor device 10, and FIG. 1A shows the first-layer electrode structure. FIG. 1B shows the electrode structure of the second layer, and the electrodes of the first layer and the third layer are indicated by broken lines. FIG. 1C shows the electrode structure of the third layer, and the electrodes of the first layer and the second layer are indicated by broken lines. Further, the base region and the emitter region are indicated by alternate long and short dash lines.

  The semiconductor device 10 has a three-layer electrode structure. That is, the first base electrode 6 and the first emitter electrode 7 are disposed in the first layer. The first base electrode 6 includes a plurality of island-shaped base electrodes 6i that are separated from each other and a frame-shaped base electrode 6f that surrounds all of the plurality of island-shaped base electrodes 6i. In addition, although the drawing shows four island-shaped base electrodes 6i for the sake of outline, there are actually more than this. The first emitter electrode 7 is a flat pattern disposed around the island-shaped base region (FIG. 1A). A metal layer (shield metal) 7 ′ in contact with an n-type high concentration impurity region (annular) 4 ′ provided on the substrate surface at the end of the chip is provided in the peripheral portion of the chip surrounding the first base electrode 6. .

  A flat second base electrode 16 is disposed in the second layer (FIG. 1B), and a flat second emitter electrode 17 is disposed in the third layer (outermost surface). The second emitter electrode 17 is smaller than the second base electrode 16, and the lower second base electrode 16 is exposed around the second emitter electrode 17. For example, bonding wires are fixed to the pad portion (emitter pad portion) 17P of the second emitter electrode 17 and the exposed pad portion (base pad portion) 16P of the second base electrode 16 (FIG. 1C).

  Each of the base electrode and the emitter electrode has a two-layer structure. The base electrode is disposed in the first layer and the second layer, and only the base electrode (second base electrode 16) is disposed in the second layer. The emitter electrodes are arranged in the first and third layers, and only the emitter electrode (second emitter electrode 17) is arranged in the third layer.

  FIG. 2 is an enlarged view showing the vicinity of the end of the semiconductor device shown in FIG. The vicinity of the end is the vicinity of the two-dot chain line in FIG. 1C, but the number of first base electrodes shown in FIG. 2 is different from that in FIG. 2A is a plan view, and FIGS. 2B and 2C are cross-sectional views taken along line aa and bb in FIG. 2A, respectively. Note that FIG. 2A shows the patterns of electrodes, insulating films, and operation regions of all layers in an overlapping manner. Moreover, although the two-dot chain line part of FIG. 1 contains the edge part of one side of a chip | tip, the shape of an edge part is the same in the four sides of a chip | tip.

  2A, the base region 3 is connected to the first base electrode 6 through the first contact hole CH1, and the first base electrode 6 is connected to the first through hole TH1 or the second through hole TH1. The second base electrode 16 is connected through the through hole TH2. The emitter region 4 is connected to the first emitter electrode 7 through the second contact hole CH2.

  In the cross section taken along the line bb in FIG. 2A, the first base electrode 6 is connected to the second base electrode 16 through the second through hole TH2. The emitter region 4 is connected to the first emitter electrode 7 through the second contact hole CH2, and the first emitter electrode 7 is connected to the second emitter electrode 17 through the third through hole TH3.

  The second emitter electrode 17 is smaller than the second base electrode 16, and the third insulating film 23 is exposed around the second emitter electrode 17. A fourth through hole TH4 is provided in the third insulating film 23 surrounding the second emitter electrode 17, and the second base electrode 16 is exposed. A part of the exposed second base electrode 16 serves as a base pad portion 16P to which the bonding wire 26 is fixed. Further, a desired region on the surface of the second emitter electrode 17 becomes an emitter pad portion 17P to which the bonding wire 27 is fixed (FIGS. 2B and 1C). A plurality of bonding wires or a bonding wire thicker than the base pad portion 16P is fixed to the emitter pad portion 17P. Alternatively, a plate-like electrode is fixed to the emitter pad portion 17P. A collector electrode 18 is provided on the back surface of the semiconductor substrate 1.

  In FIG. 2B, the bonding wire 26 is shown as a broken line on the second base electrode 16 in order to show the state of bonding wire bonding, but in actuality, as shown in FIG. It is preferable to use the exposed second base electrode 16 as the base pad portion 16P because a large bonding area of the bonding wire can be secured.

  Hereinafter, each layer will be described in detail with reference to the drawings.

  3A and 3B are diagrams showing the operation region 8, in which FIG. 3A is a plan view, and FIGS. 3B and 3C are cross-sectional views taken along lines aa and bb in FIG. It is. In the following drawings, the aa and bb lines all correspond to the same cross section as the cross section of the aa and bb lines in FIG.

  The semiconductor substrate 1 is obtained by providing an n− type semiconductor layer 1b on a high concentration n + type semiconductor substrate 1a by, for example, epitaxial growth or the like, and serves as a collector region of a bipolar transistor.

  Base region 3 is a p-type diffusion region provided on the collector region surface. On the surface of the base region 3, an emitter region 4 is formed by diffusing n + -type impurities into a pattern in which a plurality of base regions 3 are partially exposed. The base region 3 is an island-shaped base region 3i that is exposed at predetermined intervals on the rows and columns along the chip side in an island shape, and a frame-shaped base region that surrounds the plurality of island-shaped base regions 3i and the emitter region 4 Patterned to 3f.

  Although the entire illustration is omitted, the pattern of the island-shaped base region 3i and the frame-shaped base region 3f is the same as the pattern of the island-shaped base electrode 6i and the frame-shaped base electrode 6f of the first layer, respectively. Is the same as the pattern of the first emitter electrode 7 in the first layer (see FIG. 1A).

  The island-shaped base regions 3i have the same shape and area, and in this embodiment, for example, a circular shape is shown, but a polygonal shape may also be used. It is to be noted that the island structure and the frame shape are separated from each other in a superficial structure, and the base region 3 formed deeper than the emitter region 4 is one continuous region in a deep region (FIG. 3 ( B), (C)). A large number of cells formed by the base region 3 and the emitter region 4 are arranged to constitute an operation region 8. That is, in this embodiment, the formation region of the base region 3 is set as the range of the operation region 8.

  An n-type impurity region (annular) 4 ', which is the same as the emitter region, is also provided at the end of the chip. The annular 4 ′ reduces the leakage current by preventing the depletion layer from expanding in the collector region and preventing the n − type semiconductor layer 1 b below the shield metal 7 ′ from being inverted to the p-type.

  4A and 4B are diagrams showing the pattern of the first insulating film and the electrode structure of the first layer. FIG. 4A is a plan view showing the insulating film and contact holes, and FIG. 4B shows the electrode structure. It is a top view. 4C is a cross-sectional view taken along the line aa in FIG. 4B, and FIG. 4D is a cross-sectional view taken along the line bb in FIG. 4B.

  Referring to FIG. 4A, a first insulating film 21 is provided on the surface of operation region 8 (base region 3 and emitter region 4).

  The first insulating film 21 is provided with a first contact hole CH1 and a second contact hole CH2 corresponding to the base region 3 and the emitter region 4, respectively, from which they are exposed. The first contact hole CH1 is provided in a circular shape, for example, and is arranged concentrically with the island-shaped base region 3i (FIG. 2A). Also, a plurality of circular first contact holes CH1 having the same area, for example, are provided on the frame-like base region 3f so as to be separated by a predetermined distance. (FIG. 4 (A)).

  A second contact hole CH 2 is opened above the emitter region 4 on the operation region 8. The second contact hole CH2 is continuously opened around the first contact hole CH1 except for the first insulating film 21 having a desired width concentrically (for example, concentrically). That is, in the operation region 8, the first insulating film 21 is provided in, for example, a ring shape surrounding the island-shaped base electrode 6i, and the space between the adjacent first insulating films 21 becomes the second contact hole CH2. Further, a frame-shaped third contact hole CH3 is provided in the first insulating film 21 at the end of the chip, and the n + -type impurity region 4 'is exposed. The third contact hole CH3 is a scribe line that is diced during assembly.

  A first base electrode 6 and a first emitter electrode 7 are provided on the first insulating film 21. The first base electrode 6 includes two patterns corresponding to the base region 3. That is, island-shaped base electrodes 6i arranged in rows and columns along the chip side at predetermined intervals, and frame-shaped base electrodes surrounding the plurality of island-shaped base electrodes 6i and the first emitter electrodes 7 6f.

  A plurality of island-shaped base electrodes 6i are provided in a pattern overlapping with the island-shaped base region 3i and the first contact hole CH1, and are in contact with the island-shaped base region 3i through the first contact hole CH1. That is, the island-shaped base electrode 6i is, for example, circular, and is provided concentrically with the island-shaped base region 3i and the first contact hole CH1. These are arranged in a matrix on the operation region 8 (FIGS. 1A and 2A).

  The frame-shaped base electrode 6f overlaps the frame-shaped base region 3f. These are in contact through a plurality of first contact holes CH1.

  The first emitter electrode 7 is provided in a single plate shape on the operation region 8 and has first openings OP1 arranged in a matrix. Then, an island-shaped base electrode 6i is disposed in the center of each first opening OP1. The pattern of the first opening OP1 is, for example, a circle. Further, a metal layer (shield metal) 7 ′ in contact with the n-type impurity region 4 ′ at the end of the chip is provided. The metal layer 7 'is patterned into a frame shape surrounding the outer side of the frame-shaped base electrode 6f.

  Referring to FIG. 4C, in the cross section taken along the line aa, the first base electrode 6 is in contact with the base region 3 through the first contact hole CH1, and the first emitter electrode 7 is in the second contact. Contact with the emitter region 4 through the hole CH2. In this cross section, the island-shaped base region 3i, the first contact hole CH1, the island-shaped base electrode 6i (hereinafter collectively referred to as a base group), the emitter region 4, the second contact hole CH2, the first emitter electrode 7 Are alternately arranged. The illustration below the n − type semiconductor layer 1b is omitted.

  Referring to FIG. 4D, in the cross section taken along the line bb, one continuous emitter region 4 is provided over substantially the entire surface of the operation region 8, and one continuous region is provided in the first insulating film 21. The second contact hole CH2 is provided. The second contact hole CH2 is also continuous with the second contact hole CH2 in FIG. Then, the first emitter electrode 7 is in contact with the emitter region 4 through the second contact hole CH2. That is, in this cross section, the island-shaped base region 3i, the first contact hole CH1, and the island-shaped base electrode 6i are not provided. At the end of the chip, the shield metal 7 'and the n-type impurity region 4' are contacted via the third contact hole CH3. The illustration below the n − type semiconductor layer 1b is omitted.

  FIG. 5 is a diagram showing a second-layer insulating film and a second-layer electrode structure, and FIG. 5A is a plan view showing a second-layer insulating film (second insulating film) and through-hole patterns; FIG. 5B is a plan view showing the second-layer electrode.

  5C is a cross-sectional view taken along the line aa in FIG. 5B, and FIG. 5D is a cross-sectional view taken along the line bb in FIG. 5B.

  Referring to FIG. 5A, a second insulating film 22 is provided to cover first base electrode 6 and first emitter electrode 7. The second insulating film 22 is provided with a plurality of first through holes TH1 from which the island-shaped base electrode 6i is exposed and a second through hole TH2 from which the frame-shaped base electrode 6f is exposed.

  The plurality of first through holes TH1 have the same shape (for example, a circle) and the same area, and are arranged concentrically with the base group. The second through hole TH2 overlaps with the frame-shaped base electrode 6f and is formed in a frame shape having a narrower width.

  Referring to FIG. 5B, one flat second base electrode 16 is provided on the second insulating film 22.

  The second base electrode 16 continuously covers the operation region 8 from outside the operation region 8. That is, the first through hole TH1 and the second through hole TH2 are covered with the second base electrode 16. The second base electrode 16 has a plurality of second openings OP2. The second opening OP2 is provided in a matrix between the first through holes TH1. Specifically, the second opening OP2 is provided in a circular shape, for example, and is arranged concentrically with the third through hole TH3 (see FIG. 2A).

  With reference to FIG. 6, the pattern of the third layer insulating film (third insulating film) and the through hole and the structure of the third layer electrode will be described. FIG. 6A is a plan view showing a pattern of the third insulating film and the third through hole, and FIG. 6B is a plan view showing the second emitter electrode 17 which becomes an electrode of the third layer. It is. 6C is a cross-sectional view taken along the line aa in FIG. 6B, and FIG. 6D is a cross-sectional view taken along the line bb in FIG. 6B.

  The third insulating film 23 is provided on the second base electrode 16. A third through hole TH3 is provided in the third insulating film 23 and the second insulating film 22. The third through hole TH3 overlaps with the second opening OP2 below the third through hole TH3. The third through hole TH3 is provided, for example, in a circular shape, and the third through hole TH3 and the second opening OP2 are arranged concentrically (see FIG. 2A).

  The first through holes TH1 are arranged so as to constitute the first matrix corresponding to the island-shaped base electrodes 6i. A plurality of third through holes TH3 are provided for one first emitter electrode 7, and are arranged so as to constitute a second matrix in which the first matrix is shifted by, for example, a half pitch. Accordingly, the third through hole TH3 does not overlap with the first through hole TH1 and the base group.

  The plurality of third through holes TH3 have the same shape as the first through hole TH1 of FIG. 5, but the area is larger than the first through hole TH1.

  The first emitter electrode 7 is exposed from the third through hole TH3 and the second opening OP2.

  The fourth through hole TH4 is provided on the outer periphery including a part of the operation region 8. Further, a fifth through hole TH5 (scribe line) is provided at the end of the chip, and the n-type impurity region 4 'is exposed.

  The second emitter electrode 17 is the second layer as the emitter electrode, but is the third layer electrode as the electrode layer provided on the semiconductor substrate 1. The second emitter electrode 17 is a single plate-like electrode provided on the third insulating film 23 and covering the operating region 8. The area of the second emitter electrode 17 is smaller than the area of the second base electrode 16, and in the plan view, the outer periphery of the second base electrode 16 is exposed around the second emitter electrode 17 through the fourth through hole TH4. Then, a part thereof becomes the base pad portion 16P (see FIG. 1C).

  6B, the third insulating film 23 is disposed below the flat plate-like second emitter electrode 17, and is insulated from the second base electrode 16 provided in the second layer. Yes. On the other hand, in the cross section taken along the line bb in FIG. 6B, the second emitter electrode 17 has a third opening TH3 provided in the third insulating film 23 and a second opening provided in the second base electrode 16. Contact with the first emitter electrode 7 of the first layer through the part OP2.

  Thereby, in the semiconductor device 10, the base region 3 is connected to the first base electrode 6 of the first layer through the first contact hole CH1, and the first base electrode 6 is connected to the first through hole TH1 or the second through hole TH2. And is connected to the second base electrode 16 of the second layer. The emitter region 4 is connected to the first emitter electrode 7 of the first layer through the second contact hole CH2, and the first emitter electrode 7 connects the third through hole TH3 and the second opening OP2 of the second base electrode 16. To the second emitter electrode 17 of the third layer.

  FIGS. 7A and 7B are enlarged views of FIGS. 6C and 6D. FIG. 7A corresponds to FIG. 6C and FIG. 7B corresponds to FIG.

  Referring to FIG. 7A, the second base electrode 16 extends immediately above all the first base electrodes 6 in the operation region 8, and the first base electrode 6 (base region 3) is pulled in the horizontal direction of the substrate. The second base electrode 16 is connected at the shortest distance without being rotated. As a result, the wiring resistance of the base electrodes (first base electrode 6 and second base electrode 16) in the horizontal direction with respect to the substrate surface can be minimized.

  The second emitter electrode 17 extends immediately above all the first emitter electrodes 7 in the operating region 8, and the first emitter electrode 7 (emitter region 3) is not routed in the horizontal direction of the substrate and is the shortest distance away. Two emitter electrodes 17 are connected. Thereby, the wiring resistance of the emitter electrodes (first emitter electrode 7 and second emitter electrode 17) in the horizontal direction with respect to the substrate surface can be minimized.

  The second base electrode 16 is drawn in the horizontal direction with respect to the surface of the substrate on the operation region 8, but is flat and has a large area, and the base current is 1/10 to 1 of the emitter current. / 100 and small. Therefore, since the influence of the wiring resistance is small, there is almost no influence on the uniform operation.

  Therefore, the wiring resistance of the electrodes in the horizontal direction of the substrate can be minimized as the whole transistor. The transistor cells on the operating region 8 have the same electrode structure on the base side and the emitter side. That is, the wiring resistance of the base current and the wiring resistance of the emitter current are almost uniform in all the cells. Therefore, the cells in the chip operate uniformly, avoid the occurrence of thermal runaway due to current concentration, and expand the safe operation area, so that the current capacity per unit area can be increased.

  As a result, as compared with the conventional two-layer electrode structure, if the chip size is the same, a large current and a low saturation voltage can be achieved. Further, in the case of the same collector current Ic rating, the chip size can be reduced by the increase in current capacity per unit area, and the cost can be reduced.

  Also, the switching speed can be improved by reducing the chip size.

  As described above, in the present embodiment, the npn type bipolar transistor has been described as an example. However, even the pnp type bipolar transistor having the conductivity type reversed can be implemented in the same manner and the same effect can be obtained.

It is a top view for demonstrating embodiment of this invention. It is (A) top view, (B) sectional view, and (C) sectional view for explaining an embodiment of the present invention. It is (A) top view, (B) sectional view, and (C) sectional view for explaining an embodiment of the present invention. It is (A) top view, (B) top view, (C) sectional view, (D) sectional view for explaining an embodiment of the present invention. It is (A) top view, (B) top view, (C) sectional view, (D) sectional view for explaining an embodiment of the present invention. It is (A) top view, (B) top view, (C) sectional view, (D) sectional view for explaining an embodiment of the present invention. It is (A) sectional drawing for demonstrating embodiment of this invention, (B) sectional drawing. It is (A) top view and (B) top view for demonstrating a prior art. It is (A) sectional drawing for demonstrating a prior art, (B) sectional drawing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a n + type semiconductor substrate 1b n-type semiconductor layer 3 Base region 3i Island-like base region 3f Frame-like base region 4 Emitter region 6 First base electrode 6i Island-like base electrode 6f Frame-like base electrode 7 First emitter electrode DESCRIPTION OF SYMBOLS 8 Operation area | region 10 Semiconductor element 16 2nd base electrode 16P Base pad part 17 2nd emitter electrode 17P Emitter pad part 21 1st insulating film 22 2nd insulating film 23 3rd insulating film 26, 27 Bonding wire 51a n + type semiconductor substrate 51b n− type semiconductor layer 53 base region 54 emitter region 56 first base electrode 57 first emitter electrode 58 operating region 66 second base electrode 67 second emitter electrode 100 semiconductor element CH1 first contact hole CH2 second contact hole CH3 third Contact hole TH1 first Ruhoru TH2 second through-hole TH3 third through hole TH4 fourth through holes TH5 fifth through hole TH6 sixth through hole

Claims (5)

A one-conductivity type semiconductor substrate to be a collector region;
A plurality of reverse conductivity type base regions provided on the substrate and spaced apart from each other;
An emitter region of one conductivity type provided around the base region;
A first insulating film covering the substrate surface;
A first contact hole and a second contact hole provided in the first insulating film and exposing the base region and the emitter region, respectively;
A first base electrode in contact with the base region through the first contact hole;
One flat first emitter electrode in contact with the emitter region via the second contact hole;
A second insulating film covering the first base electrode and the first emitter electrode;
A first through hole and a second through hole provided in the second insulating film and exposing the first base electrode;
A flat second base electrode that is provided on the second insulating film so as to cover the first through hole and the second through hole, and is connected to the first base electrode through the two through holes;
A third insulating film provided on the second base electrode;
A plurality of third through holes provided in the third insulating film and the second insulating film;
A flat second emitter electrode provided on the third insulating film so as to cover the third through hole and connected to the first emitter electrode through the third through hole;
A semiconductor device comprising: The base region has a plurality of island-shaped base regions and a frame-shaped base region surrounding the plurality of island-shaped base regions,
The first base electrode has a plurality of island-shaped base electrodes and a frame-shaped base electrode surrounding the plurality of island-shaped base electrodes,
The island-shaped base region is connected to the island-shaped base electrode, the frame-shaped base region is connected to the frame-shaped base electrode,
The semiconductor device according to claim 1, wherein the first through hole is provided on the island-shaped base electrode, and the second through hole is provided on the frame-shaped base electrode.   4. A fourth through hole is provided in the third insulating film exposed on an outer periphery of the second emitter electrode, and a part of the second base electrode exposed from the fourth through hole is used as a pad portion. Item 3. The semiconductor device according to Item 2.   4. The method according to claim 1, wherein the first through holes are arranged so as to constitute a first matrix, and the third through holes are arranged so as to constitute a second matrix. A semiconductor device according to claim 1.   The semiconductor device according to claim 1, wherein the second base electrode has an opening, and the opening and the third through hole overlap each other.

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