JP2010109105A - Sample holder and carrying device - Google Patents

Sample holder and carrying device Download PDF

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JP2010109105A
JP2010109105A JP2008279016A JP2008279016A JP2010109105A JP 2010109105 A JP2010109105 A JP 2010109105A JP 2008279016 A JP2008279016 A JP 2008279016A JP 2008279016 A JP2008279016 A JP 2008279016A JP 2010109105 A JP2010109105 A JP 2010109105A
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film
electrode layer
sample holder
amorphous
wafer
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JP5225023B2 (en
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Takeshi Muneishi
猛 宗石
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Kyocera Corp
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<P>PROBLEM TO BE SOLVED: To suppress damage of a target sample to be held and contamination of the target sample, and to stably suck and hold the target sample to be held with relatively large suction force. <P>SOLUTION: The sample holder for sucking and holding a sample by electrostatic force includes: a substrate; and an electrode layer provided on one main surface of the substrate. The surface of the electrode layer is covered with a semi-conductive film with Si as a main constituent. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体ウエハやガラス基板等の試料を保持する試料保持具、および搬送装置に関する。   The present invention relates to a sample holder for holding a sample such as a semiconductor wafer or a glass substrate, and a transfer device.

半導体装置や液晶表示装置等の製造工程では、半導体ウエハやガラス基板等の対象試料を試料保持具によって保持し、エッチング装置や成膜装置内を搬送する必要がある。エッチング装置や成膜装置の真空チャンバ内部等、真空吸着機構が使用できない状態における試料保持には、静電作用を利用して試料を吸着保持する静電チャックが広く用いられている。静電チャックは、吸着方式の違いによって、クーロン力型と、ジョンソン・ラベック力型との、２つの吸着方式に大きく分類される。クーロン力型の静電チャックは、誘電層として絶縁材料を使用し、電極と被処理体との間に誘起された電荷により生じるクーロン力（静電吸着力）を用いて、被処理体を吸着する。一方、ジョンソン・ラベック力型の静電チャックは、誘電層にわずかに導電性を付与し、該誘電層内での電荷移動により生じるジョンソン・ラベック力を用いて、被処理体を吸着する。いずれの吸着方式の静電チャックにおいても、その誘電層には、耐熱性、耐プラズマ性、強度特性等に優れていることから、一般に、セラミックスが用いられており、特に、耐食性に優れたアルミナ系セラミックスが多用されている。   In a manufacturing process of a semiconductor device, a liquid crystal display device, or the like, it is necessary to hold a target sample such as a semiconductor wafer or a glass substrate with a sample holder and transport the sample through an etching device or a film forming device. For holding a sample in a state where a vacuum suction mechanism cannot be used, such as inside a vacuum chamber of an etching apparatus or a film forming apparatus, an electrostatic chuck that holds the sample by suction using electrostatic action is widely used. Electrostatic chucks are broadly classified into two adsorption systems, a Coulomb force type and a Johnson-Labeck force type, depending on the difference in the adsorption system. The Coulomb force type electrostatic chuck uses an insulating material as a dielectric layer, and uses the Coulomb force (electrostatic adsorption force) generated by the charge induced between the electrode and the object to be processed to attract the object to be processed. To do. On the other hand, the Johnson-Labeck force type electrostatic chuck imparts a slight conductivity to the dielectric layer, and adsorbs the object to be processed using the Johnson-Labeck force generated by charge transfer in the dielectric layer. In any of the adsorption type electrostatic chucks, ceramics are generally used for the dielectric layer because of its excellent heat resistance, plasma resistance, strength characteristics, etc., and in particular, alumina with excellent corrosion resistance. Ceramics are often used.

従来のジョンソン・ラベック力を利用する静電チャックは、本来絶縁材料であるＡｌ２Ｏ３に、第２成分として金属酸化物等を添加されることで、導電性が付与されている。これら金属酸化物の添加はＡｌ２Ｏ３材の特徴である高い機械的特性（強度・硬度）、熱伝導性、耐薬品性、耐プラズマ性を低下させる要因となり、また半導体ウエハ等の試料表面の金属汚染の要因の１つともなっていた。例えば、下記非特許文献１には、かかる課題を解決するために、Ａｌ２Ｏ３粒子にＳｉＣ超微粒子を混合させた複合材料を、静電チャックに用いる例が記載されている。また、下記特許文献１には、セラミックス粒子の脱離によるパーティクル発生を抑制するために、セラミックス材に代えて、特定の添加剤を添加したシリカガラス材を用いた静電チャックが提案されている。
“高純度アルミナ-SiC超微粒子複合材料静電チャックの特性”、［online］、［平成２０年１０月２０日検索］、インターネット〈URL：www.socnb.com/report/ptech/1999p79.pdf〉 特開２００８−３５５９０号 The conventional electrostatic chuck using the Johnson-Labeck force is imparted with conductivity by adding a metal oxide or the like as a second component to Al 2 O 3 which is originally an insulating material. The addition of these metal oxides causes the deterioration of the high mechanical properties (strength / hardness), thermal conductivity, chemical resistance, and plasma resistance that are characteristic of Al 2 O 3 materials, and the surface of samples such as semiconductor wafers. It was one of the causes of metal contamination. For example, Non-Patent Document 1 below describes an example in which a composite material in which SiC ultrafine particles are mixed with Al 2 O 3 particles is used for an electrostatic chuck in order to solve such a problem. Patent Document 1 listed below proposes an electrostatic chuck using a silica glass material to which a specific additive is added in place of the ceramic material in order to suppress the generation of particles due to the detachment of the ceramic particles. .
“Characteristics of high-purity alumina-SiC ultrafine particle composite electrostatic chuck”, [online], [October 20, 2008 search], Internet <URL: www.socnb.com/report/ptech/1999p79.pdf> JP 2008-35590 A

非特許文献１に記載の静電チャックでは、ウエハ等の対象試料と接触する静電チャックの表面の硬度が比較的高く、単結晶Ｓｉウエハ等の対象試料表面に、傷等の損傷が比較的生じやすいという問題があった。また、非特許文献１に記載の静電チャックにおいても、例えば単結晶Ｓｉ等のウエハがＡｌ２Ｏ３やＳｉＣによって汚染される可能性があった。同様に、特許文献１記載の静電チャックでは、単結晶Ｓｉ等のウエハが、シリカガラスやその他の不純物によって汚染され易いといった問題があった。本願発明は、かかる課題を解決することを目的になされたものである。 In the electrostatic chuck described in Non-Patent Document 1, the hardness of the surface of the electrostatic chuck that comes into contact with the target sample such as a wafer is relatively high, and the surface of the target sample such as a single crystal Si wafer is relatively damaged. There was a problem that it was likely to occur. Further, even in the electrostatic chuck described in Non-Patent Document 1, there is a possibility that a wafer such as single crystal Si is contaminated by Al 2 O 3 or SiC. Similarly, the electrostatic chuck described in Patent Document 1 has a problem that a wafer made of single crystal Si or the like is easily contaminated by silica glass or other impurities. The present invention has been made for the purpose of solving such problems.

上記課題を解決するために、本発明は、静電気力によって試料を吸着して保持する試料保持具であって、基体と、前記基体の一方主面に設けられた電極層とを有し、前記電極層の表面が半導電性膜によって被覆されていることを特徴とする試料保持具を提供する。また、半導電性を有するとは、表面抵抗が１０５Ω／□以上１０１４Ω／□未満のことをいう。 In order to solve the above-mentioned problem, the present invention is a sample holder for adsorbing and holding a sample by electrostatic force, comprising a base and an electrode layer provided on one main surface of the base, Provided is a sample holder characterized in that the surface of an electrode layer is covered with a semiconductive film. Further, having semiconductivity means that the surface resistance is 10 5 Ω / □ or more and less than 10 14 Ω / □.

なお、前記半導電性膜は、アモルファスＳｉからなることが好ましい。   The semiconductive film is preferably made of amorphous Si.

また、前記半導電性膜の表面抵抗が、１０６〜１０１２（Ω／□）であることが好ましい。この表面抵抗は、ＡＮＳＩ（American National Standards Institute：米国規格協会）／ＥＩＡ５４１に規定されている静電気拡散性の範囲と概ね一致しており、帯電の減衰時間に関して良好な結果をもたらす。表面抵抗値が１０６〜１０１２の半導電性膜の場合には減衰時間が１０秒以下と好ましい結果が得られるのに対して、表面抵抗値が１０１２よりも大きい半導電性膜の場合には１００秒程度かかってしまい好ましくない。なお、帯電の減衰時間は、膜の裏面に電極を形成して、その電極に所定の電圧を印加して、印加終了後の電位が元の電位に戻る時間を計測することにより評価している。 The surface resistance of the semiconductive film is preferably 10 6 to 10 12 (Ω / □). This surface resistance is generally consistent with the static diffusivity range specified in ANSI (American National Standards Institute) / EIA 541 and provides good results with respect to charge decay time. While the surface resistance value in the case of a semi-conductive film of 106 to 1012 is obtained favorable results with decay time 10 seconds or less, when the surface resistance is larger than 10 12 semiconductive film Takes about 100 seconds, which is not preferable. The charge decay time is evaluated by forming an electrode on the back surface of the film, applying a predetermined voltage to the electrode, and measuring the time for the potential to return to the original potential after completion of the application. .

また、前記基体から突出して設けられた支持部を備え、前記支持部の突出端が、前記半導電性膜の表面よりも、前記基体の前記一方主面から突出していることが好ましい。   Further, it is preferable that a support portion provided so as to protrude from the base is provided, and a protruding end of the support portion protrudes from the one main surface of the base rather than the surface of the semiconductive film.

また、前記基体は誘電体からなり、かつ前記支持部は導電性を有し、前記支持部は、前記基体の前記一方主面から他方主面に向けて形成された貫通孔に挿通されて、前記他方主面の側に配された他方電極と電気的に接続していることが好ましい。   Further, the base is made of a dielectric, and the support part has conductivity, and the support part is inserted into a through hole formed from the one main surface to the other main surface of the base, It is preferable to be electrically connected to the other electrode arranged on the other main surface side.

また、前記基体はセラミックスからなることが好ましい。   The substrate is preferably made of ceramics.

また、前記アモルファスＳｉ膜は、ＣＶＤ法によって成膜されていることが好ましい。   The amorphous Si film is preferably formed by a CVD method.

本発明は、また、上述の試料保持具と、前記試料保持具を移動させる移動機構と、を備えて構成された搬送装置を、併せて提供する。   The present invention also provides a transport apparatus that includes the sample holder described above and a moving mechanism that moves the sample holder.

本願発明によれば、保持する対象試料の損傷、および対象試料の汚染を抑制するとともに、保持する対象試料を、比較的大きな吸着力で安定して吸着保持することができる。   According to the present invention, it is possible to suppress damage to the target sample to be held and contamination of the target sample, and to stably hold the target sample to be held with a relatively large suction force.

図１は、本発明の試料保持具の一実施形態である静電チャック１０を用いて構成される、ウエハ吸着機構について説明する図であり、（ａ）は概略上面図、（ｂ）は（ａ）のＸ−Ｘ線断面図である。図１では、静電チャック１０によって、対象試料である単結晶Ｓｉウエハ１１を吸着保持した状態を示している。   1A and 1B are diagrams for explaining a wafer attracting mechanism configured by using an electrostatic chuck 10 which is an embodiment of a sample holder of the present invention. FIG. 1A is a schematic top view, and FIG. It is XX sectional drawing of a). FIG. 1 shows a state in which an electrostatic chuck 10 attracts and holds a single crystal Si wafer 11 as a target sample.

静電チャック１０は、基体１と、基体１の一方主面１ａに設けられた第１電極層４と、第１電極層４の表面を被覆するアモルファスＳｉ膜３と、基体１の他方主面１ｂに設けられた第２電極層５と、基体１の一方主面１ａから突出して設けられた支持部２とを備えている。ウエハ吸着機構は、静電チャック１０と、電圧印加手段２０とを有して構成されている。   The electrostatic chuck 10 includes a base 1, a first electrode layer 4 provided on one main surface 1 a of the base 1, an amorphous Si film 3 covering the surface of the first electrode layer 4, and the other main surface of the base 1. The second electrode layer 5 provided on 1b and the support portion 2 provided so as to protrude from one main surface 1a of the base 1 are provided. The wafer attracting mechanism includes an electrostatic chuck 10 and a voltage applying unit 20.

基体１は誘電部材からなり、本実施形態では、例えばＡｌ２Ｏ３を主成分とするセラミックス焼結体によって構成されている。第１電極層４および第２電極層５は、例えばＴｉやＣｕ等の導電性材料からなり、例えばスパッタリング等の公知の成膜方法によって、基体１の表面に成膜されて形成されている。本実施形態の第１電極層４および第２電極層５は、いずれも、例えば１〜５μｍ程度の厚みとされている。 The base body 1 is made of a dielectric member, and in the present embodiment, is constituted by a ceramic sintered body containing, for example, Al 2 O 3 as a main component. The first electrode layer 4 and the second electrode layer 5 are made of a conductive material such as Ti or Cu, and are formed on the surface of the substrate 1 by a known film formation method such as sputtering. Both the first electrode layer 4 and the second electrode layer 5 of the present embodiment have a thickness of about 1 to 5 μm, for example.

第１電極層４および第２電極層５は、電圧印加手段２０と電気的に接続される電極部４Aおよび５Bを備えている。第１電極層４および第２電極層５は、各電極部がこの電圧印加手段と接続され、第１電極層４および第２電極層５は、それぞれ異なる電位に設定される。電圧印加手段は、直流電圧源など公知の電圧印加手段であればよい。   The first electrode layer 4 and the second electrode layer 5 include electrode portions 4A and 5B that are electrically connected to the voltage applying means 20. Each electrode portion of the first electrode layer 4 and the second electrode layer 5 is connected to this voltage applying means, and the first electrode layer 4 and the second electrode layer 5 are set to different potentials. The voltage applying means may be a known voltage applying means such as a DC voltage source.

第１電極層４は、基体１の一方主面１aの一部、より具体的には、保持対象試料である単結晶Ｓｉウエハ１１に対向する領域に、比較的広い面積で設けられている。基体１には、第１電極層４の周辺に、基体１を一方主面１ａの側から他方主面１ｂの側に貫通する貫通孔１３が設けられている。貫通孔１３には、例えばＴｉやＣｕからなる、導電性を有する支持部材２の一部が挿通されており、支持部材２は、例えば導電性接着剤やロウ付け等によって、基体１に接続固定されている。支持部材２は、基体１の他方主面１ｂの側において、第２電極層５と電気的に接続されており、第２電極層５と同電位にされている。   The first electrode layer 4 is provided in a part of one main surface 1a of the substrate 1, more specifically, in a region facing the single crystal Si wafer 11 that is a sample to be held, with a relatively wide area. The base body 1 is provided with a through hole 13 that penetrates the base body 1 from the one main surface 1 a side to the other main surface 1 b side around the first electrode layer 4. A part of the conductive support member 2 made of, for example, Ti or Cu is inserted into the through hole 13, and the support member 2 is connected and fixed to the base 1 by, for example, a conductive adhesive or brazing. Has been. The support member 2 is electrically connected to the second electrode layer 5 on the side of the other main surface 1 b of the base body 1 and is at the same potential as the second electrode layer 5.

第１電極層４の表面を被覆するアモルファスＳｉ膜３は、例えばＣＶＤ法等の公知の手法を用いて形成されている。アモルファスＳｉ膜３の膜厚や、電気抵抗率および表面抵抗の大きさなどは、例えばＣＶＤ法等の成膜条件を調整することで、比較的高い精度で調整することができる。アモルファスＳｉ膜３は、例えば膜厚が５〜５０μｍとされ、表面抵抗は１０６〜１０１２（Ω／□）と比較的低い値とされている。なお、表面抵抗の大きさは、例えば、ＪＩＳ Ｋ６２７１にて規定される二重リング電極法によって測定すればよい。なお、アモルファスＳｉ膜の表面抵抗の値は、上記範囲に限定されない。このようにアモルファスＳｉ膜３は、半導電性を有し、第１電極層４と同電位とされている。 The amorphous Si film 3 covering the surface of the first electrode layer 4 is formed using a known method such as a CVD method. The thickness of the amorphous Si film 3, the electrical resistivity, the surface resistance, and the like can be adjusted with relatively high accuracy by adjusting film forming conditions such as a CVD method. The amorphous Si film 3 has a film thickness of, for example, 5 to 50 μm and a surface resistance of 10 6 to 10 12 (Ω / □), which is a relatively low value. In addition, what is necessary is just to measure the magnitude | size of surface resistance by the double ring electrode method prescribed | regulated by JISK6271, for example. Note that the value of the surface resistance of the amorphous Si film is not limited to the above range. Thus, the amorphous Si film 3 has semiconductivity and has the same potential as the first electrode layer 4.

本実施形態の静電チャック１０では、アモルファスＳｉ膜３は、第１電極層４のみでなく、基体１の一方主面１ａ全体を被覆している。静電チャック１０では、アモルファスし層３によってＡｌ２Ｏ３等のセラミックス粒子の脱離が抑制されており、パーティクルが比較的発生し難い。 In the electrostatic chuck 10 of this embodiment, the amorphous Si film 3 covers not only the first electrode layer 4 but also the entire one main surface 1a of the substrate 1. In the electrostatic chuck 10, detachment of ceramic particles such as Al 2 O 3 is suppressed by the amorphous layer 3, and particles are hardly generated.

本実施形態の静電チャック１０では、支持部２の突出端２Ａが、アモルファスＳｉ膜３の表面に対し、基体１の一方主面１ａからより離間した位置にある。静電チャック１０では、アモルファスＳｉ膜３の表面と支持部２の突出端２Ａとの、基体の１の一方主面１ａに垂直な方向に沿った離間距離Ｘが、支持部２の突出端２Ａに単結晶Ｓｉウエハ１１を載置した状態で、アモルファスＳｉ膜３の表面と単結晶Ｓｉウエハ１１とが離間するに充分な距離とされている。すなわち、静電チャック１０では、この離間距離Ｘが、基体１の一方主面１ａの側を上向として、支持部２の突出端２Ａに単結晶Ｓｉウエハ１１を載置した場合の、単結晶Ｓｉウエハ１１の自重による撓みの大きさ以下とされている。   In the electrostatic chuck 10 of the present embodiment, the protruding end 2 </ b> A of the support portion 2 is at a position further away from the one main surface 1 a of the substrate 1 with respect to the surface of the amorphous Si film 3. In the electrostatic chuck 10, the separation distance X along the direction perpendicular to the one main surface 1 a of the base 1 between the surface of the amorphous Si film 3 and the protruding end 2 A of the support portion 2 is the protruding end 2 A of the support portion 2. The surface of the amorphous Si film 3 and the single crystal Si wafer 11 are sufficiently separated from each other with the single crystal Si wafer 11 placed thereon. That is, in the electrostatic chuck 10, the separation distance X is a single crystal when the single crystal Si wafer 11 is placed on the protruding end 2 </ b> A of the support portion 2 with the one main surface 1 a side of the substrate 1 facing upward. The magnitude of the deflection of the Si wafer 11 due to its own weight is set to be equal to or less than the magnitude of the deflection.

図２は、静電チャック１０による、単結晶Ｓｉウエハ１１の吸着状態について説明する図である。より具体的には、基体１の一方主面１ａの側を上向として、支持部２の突出端２Ａに単結晶Ｓｉウエハ１１を載置し、第１電極層４の電位Ｖ１、第２電極層５の電位をＶ２（本実施形態ではグランド）に設定した状態を示している。なお、電位Ｖ１と電位Ｖ２との電位差の大きさをＶ（Ｖ１−Ｖ２＝Ｖ）とする。 FIG. 2 is a diagram for explaining a suction state of the single crystal Si wafer 11 by the electrostatic chuck 10. More specifically, the single crystal Si wafer 11 is placed on the protruding end 2A of the support portion 2 with the one main surface 1a side of the base body 1 facing upward, and the potential V 1 of the first electrode layer 4, A state in which the potential of the electrode layer 5 is set to V 2 (ground in the present embodiment) is shown. Note that the magnitude of the potential difference between the potential V 1 and the potential V 2 is V (V 1 −V 2 = V).

第２電極層５は、支持部２と電気的に接続されており、支持部２の電位および突出端２Ａに載置された単結晶Ｓｉウエハ１１の電位もＶ２とされている。また、第１電極層４の表面を被覆する半導電性のアモルファスＳｉ膜３の電位もＶ１とされる。静電チャック１０では、電位Ｖ２とされた単結晶Ｓｉウエハ１１と、電位Ｖ１とされた第１電極層４と、の間でクーロン力（静電吸着力）が発生する。静電チャック１０では、単結晶Ｓｉウエハ１１とアモルファスＳｉ膜３の表面とが離間した状態で、単結晶Ｓｉウエハ１１とアモルファスＳｉ膜３との間（離間距離Ｘ１）に生じたこのクーロン力によって、単結晶Ｓｉウエハ１１を吸着保持する。 The second electrode layer 5, the support portion 2 and are electrically connected, the potential of the support 2 of the potential and placed on the projecting end 2A monocrystalline Si wafer 11 is also set to V 2. The potential of the amorphous Si film 3 semiconductive covering the surface of the first electrode layer 4 are also as V 1. In the electrostatic chuck 10, a single-crystal Si wafer 11, which is a potential V 2, the first electrode layer 4 and the potential V 1, Coulomb force (electrostatic attraction force) is generated between the. In the electrostatic chuck 10, the Coulomb force generated between the single crystal Si wafer 11 and the amorphous Si film 3 (separation distance X1) in a state where the single crystal Si wafer 11 and the surface of the amorphous Si film 3 are separated from each other. The single crystal Si wafer 11 is held by suction.

例えば、シリカガラスなどの絶縁膜で第１電極層４を被覆した場合、絶縁膜の電位は第１電極層４と同電位とはならず、比較的大きく離間した第１電極層４と単結晶Ｓｉウエハ１1との間（図２に示す離間距離Ｘ２に対応）で、電位差Ｖに応じたクーロン力が生じる。一方、本実施形態の静電チャック１０では、第１電極層４を被覆するアモルファスＳｉ膜３が半導電性を有するので、第１電極層４を被覆するアモルファスＳｉ膜３と、保持対象試料である単結晶Ｓｉウエハ１１との間（離間距離Ｘ１）の電位差を、電源装置によって印加される電圧（電位差）の通りとすることができる。すなわち、静電チャック１０では、比較的近接したアモルファスＳｉ膜３と単結晶Ｓｉウエハ１１との間で、電位差Ｖに応じたクーロン力が生じる。このように、静電チャック１０では、第１電極層４を被覆するアモルファスＳｉ膜３と、単結晶Ｓｉウエハ１１との電位差が比較的大きく、保持対象試料である単結晶Ｓｉウエハ１１を、比較的大きな吸着力で、安定して吸着保持することができる。   For example, when the first electrode layer 4 is covered with an insulating film such as silica glass, the potential of the insulating film is not the same as that of the first electrode layer 4, and the first electrode layer 4 and the single crystal that are relatively separated from each other. A Coulomb force corresponding to the potential difference V is generated between the Si wafer 11 1 (corresponding to the separation distance X2 shown in FIG. 2). On the other hand, in the electrostatic chuck 10 of this embodiment, since the amorphous Si film 3 covering the first electrode layer 4 has semiconductivity, the amorphous Si film 3 covering the first electrode layer 4 and the holding target sample are used. The potential difference between the single crystal Si wafer 11 (separation distance X1) can be made the same as the voltage (potential difference) applied by the power supply device. That is, in the electrostatic chuck 10, a Coulomb force corresponding to the potential difference V is generated between the amorphous Si film 3 and the single crystal Si wafer 11 that are relatively close to each other. Thus, in the electrostatic chuck 10, the potential difference between the amorphous Si film 3 covering the first electrode layer 4 and the single crystal Si wafer 11 is relatively large, and the single crystal Si wafer 11 that is a holding target sample is compared. It can be stably adsorbed and held with a large adsorption force.

電圧印加手段での印加電圧を比較的小さく、かつクーロン力を比較的大きくするには、アモルファスＳｉ膜３と単結晶Ｓｉウエハとの離間距離Ｘ１は、比較的小さい方が好ましく、このためには、支持部材２の突出端２ＡとアモルファスＳｉ膜３との離間距離は、比較的小さい方が好ましい。一方、アモルファスＳｉ膜３と、支持部材２の突出端２Ａとの離間距離が小さい場合、保持対象試料である単結晶Ｓｉウエハ１１が想定以上に薄膜化された場合など、単結晶Ｓｉウエハ１１の撓みによって、単結晶Ｓｉウエハ１１とアモルファスＳｉ膜３とが接触する可能性が比較的高くなる。この場合でも、アモルファスＳｉ膜３は、単結晶Ｓｉウエハ１１に比べ硬度が低いため、単結晶Ｓｉウエハ１１表面に傷等の損傷が発生し難い。また、アモルファスＳｉ膜３は、単結晶Ｓｉウエハ１１と同様、Ｓｉで構成されているので、単結晶Ｓｉウエハ１１の汚染（Ｓｉ以外の元素の付着）も、比較的発生し難い。このように、静電チャック１０によれば、保持対象試料である単結晶Ｓｉウエハ１１の損傷および汚染を抑制するとともに、比較的大きな吸着力で、単結晶Ｓｉウエハ１１を安定して吸着保持することができる。   In order to make the voltage applied by the voltage application means relatively small and the Coulomb force relatively large, the distance X1 between the amorphous Si film 3 and the single crystal Si wafer is preferably relatively small. The separation distance between the protruding end 2A of the support member 2 and the amorphous Si film 3 is preferably relatively small. On the other hand, when the separation distance between the amorphous Si film 3 and the projecting end 2A of the support member 2 is small, or when the single crystal Si wafer 11 that is the holding target sample is made thinner than expected, the single crystal Si wafer 11 Due to the bending, the possibility that the single crystal Si wafer 11 and the amorphous Si film 3 are in contact with each other becomes relatively high. Even in this case, since the amorphous Si film 3 has a lower hardness than the single crystal Si wafer 11, damage such as scratches hardly occurs on the surface of the single crystal Si wafer 11. Further, since the amorphous Si film 3 is made of Si like the single crystal Si wafer 11, contamination of the single crystal Si wafer 11 (adhesion of elements other than Si) is relatively unlikely to occur. As described above, according to the electrostatic chuck 10, damage and contamination of the single crystal Si wafer 11, which is a holding target sample, are suppressed, and the single crystal Si wafer 11 is stably held by suction with a relatively large suction force. be able to.

図１に示す静電チャック１０を、例えば公知のハンドリングロボット等の移動機構に設け、例えば半導体製造装置の真空チャンバ内において、保持対象試料である単結晶Ｓｉウエハ１１を搬送させる搬送装置を構成してもよい。静電チャック１０では、クーロン力によって、保持対象試料を比較的高い吸着力で安定して保持することができるので、試料を比較的高速に搬送した場合でも、吸着した試料の位置ずれ等が比較的発生し難い。静電チャック１０を備えて構成された搬送装置では、対象試料を、比較的高速に、かつ高い位置精度で搬送することができる。   The electrostatic chuck 10 shown in FIG. 1 is provided in a moving mechanism such as a known handling robot, for example, and constitutes a transfer device for transferring a single crystal Si wafer 11 as a holding target sample in a vacuum chamber of a semiconductor manufacturing apparatus, for example. May be. Since the electrostatic chuck 10 can stably hold a sample to be held with a relatively high adsorption force by the Coulomb force, even when the sample is transported at a relatively high speed, the positional deviation of the adsorbed sample is compared. Less likely to occur. In the transfer device configured to include the electrostatic chuck 10, the target sample can be transferred at a relatively high speed and with high positional accuracy.

また、アモルファスＳｉ膜３は半導電性を有し、帯電によるパーティクルの付着の程度は比較的小さい。真空中では静電気が比較的発生し易く、例えば、電極表面をシリカガラスなどの絶縁性膜で被覆した場合など、この絶縁性膜が比較的帯電し易い。この場合、真空チャンバ内において、シリカガラスなどの絶縁性膜の表面にパーティクルが付着し易い。静電チャック１０では、電極を被覆するアモルファスＳｉ膜３は半導電性を有し、真空中であっても帯電し難い。静電チャック１０によれば、吸着保持する対象試料へのパーティクルの付着、および、このパーティクルに起因した対象試料表面における傷等の損傷の発生が、比較的少なくされている。   Further, the amorphous Si film 3 has semiconductivity, and the degree of particle adhesion due to charging is relatively small. Static electricity is relatively easily generated in a vacuum. For example, when the electrode surface is covered with an insulating film such as silica glass, the insulating film is relatively easily charged. In this case, particles easily adhere to the surface of an insulating film such as silica glass in the vacuum chamber. In the electrostatic chuck 10, the amorphous Si film 3 covering the electrode has semiconductivity and is difficult to be charged even in a vacuum. According to the electrostatic chuck 10, the adhesion of particles to the target sample to be attracted and held, and the occurrence of damage such as scratches on the surface of the target sample due to the particles are relatively reduced.

上記実施形態では、支持部材２０を備え、保持対象試料である単結晶Ｓｉウエハ１１を、アモルファスＳｉ膜３と離間させた状態で吸着保持する例について説明したが、支持部材２０を必ずしも備えていることに限定されない。すなわち、第１電極層表面を被覆するアモルファスＳｉ膜３に、保持対象試料である単結晶Ｓｉウエハ１１を直接当接させ、単結晶Ｓｉウエハ１１を、ジョンソン・ラベック力によって吸着保持する構成としてもよい。この場合も、保持対象試料と当接する面が、比較的硬度が低いアモルファスＳｉ膜の表面とされているので、例えばセラミックス粒子等によって保持対象試料の表面に傷が発生することがない。また、保持対象試料の表面の、例えば金属酸化物等による汚染が比較的発生し易い。   In the above-described embodiment, the example in which the support member 20 is provided and the single crystal Si wafer 11 that is a sample to be held is sucked and held in a state of being separated from the amorphous Si film 3 has been described, but the support member 20 is not necessarily provided. It is not limited to that. That is, the single crystal Si wafer 11 that is the sample to be held is brought into direct contact with the amorphous Si film 3 that covers the surface of the first electrode layer, and the single crystal Si wafer 11 is adsorbed and held by the Johnson-Labeck force. Good. Also in this case, since the surface in contact with the sample to be held is the surface of the amorphous Si film having a relatively low hardness, the surface of the sample to be held is not damaged by, for example, ceramic particles. Further, the surface of the sample to be held is relatively easily contaminated with, for example, metal oxide.

次に、静電チャック１０の製造方法の一例について説明しておく。   Next, an example of a method for manufacturing the electrostatic chuck 10 will be described.

まず、セラミックスからなる基体１を作製しておく。基体１は、例えば以下のように作製することができる。まず、酸化アルミニウム粉末９６〜９９．９質量％と、酸化珪素、炭酸カルシウム、酸化マグネシウムの各粉末を含む焼結助剤粉末０．１〜４質量％とからなる原料粉末を混合し、ポリエチレングリコールなどの有機結合材をこの原料粉末１００質量部に対して３〜８質量部添加、混合し、水を添加してスラリーとする。このスラリーを噴霧乾燥機により噴霧乾燥し、得られた顆粒をゴム型に充填し、静水圧により加圧して成形体を作製する。得られた成形体を加工して、基体１の形に近い形状に切削し、いわゆるニアネット成形体を作製する。このニアネット成形体を、焼成炉で１５００〜１７００℃で焼成し、焼結体を作製する。焼結体を加工して基体１を作製する。   First, a substrate 1 made of ceramic is prepared. The substrate 1 can be produced as follows, for example. First, raw material powder composed of 96 to 99.9% by mass of aluminum oxide powder and 0.1 to 4% by mass of sintering aid powder containing each powder of silicon oxide, calcium carbonate, and magnesium oxide was mixed, and polyethylene glycol was mixed. 3 to 8 parts by mass of an organic binder such as is added to 100 parts by mass of the raw material powder and mixed, and water is added to form a slurry. This slurry is spray-dried with a spray dryer, and the resulting granule is filled into a rubber mold and pressed with hydrostatic pressure to produce a molded body. The obtained molded body is processed and cut into a shape close to the shape of the substrate 1 to produce a so-called near net molded body. This near-net molded body is fired at 1500 to 1700 ° C. in a firing furnace to produce a sintered body. The sintered body is processed to produce the substrate 1.

次に、例えば公知のスパッタリング法などを用いて、基体１の一方主面１ａおよび他方主面１ｂに、ＴｉやＣｕからなる金属層を成膜する。次いで、公知のフォトリソグラフィー手法およびエッチング手法を用いて、成膜した金属層をパターニングし、基体１の一方主面１ａに第１電極層４を、また、他方主面１ｂに第２電極層５を、それぞれ形成する。   Next, a metal layer made of Ti or Cu is formed on one main surface 1a and the other main surface 1b of the base 1 by using, for example, a known sputtering method. Next, the formed metal layer is patterned using a known photolithography technique and etching technique, and the first electrode layer 4 is formed on one main surface 1a of the substrate 1, and the second electrode layer 5 is formed on the other main surface 1b. Are formed respectively.

次に、公知のＣＶＤ成膜装置を用い、アモルファスＳｉ膜３を成膜する。アモルファスＳｉ膜３は、通常のＣＶＤ法や、ｃａｔ−ＣＶＤ法など、従来公知の成膜方法を用いて成膜すればよい。ＣＶＤ法を用いることで、成膜した膜の電気抵抗率の大きさを、比較的高精度に制御することができる。   Next, an amorphous Si film 3 is formed using a known CVD film forming apparatus. The amorphous Si film 3 may be formed using a conventionally known film forming method such as a normal CVD method or a cat-CVD method. By using the CVD method, the magnitude of the electrical resistivity of the deposited film can be controlled with relatively high accuracy.

ＣＶＤ法による成膜では、例えば成膜用の真空容器に、電極層が形成された基体１を配置し、この真空容器内に、シリコン含有ガス（例えば、ＳｉＨ，Ｓｉ２Ｈ６、Ｓｉ３Ｈ８等）及び、キャリアガスとして、例えば水素や窒素、アルゴン等の不活性ガスを導入し、真空度を例えば１．３〜１３Ｐａに制御する。この状態で、真空容器内のガス導入孔が設けられた導電性の電極板に電力を供給してグロー放電を発生させて、真空容器内に配置した基体１の表面に、アモルファスＳｉ膜２０を成膜する。アモルファスＳｉ膜３の表面抵抗を１０６〜１０１２Ω／□の範囲内に設定するには、水素の量を所定の範囲で管理すればよい。なお、アモルファスＳｉ膜の形成方法は、ＣＶＤ法を用いることに限定されない。 In film formation by the CVD method, for example, the substrate 1 on which an electrode layer is formed is placed in a vacuum vessel for film formation, and a silicon-containing gas (for example, SiH, Si 2 H 6 , Si 3 H) is placed in the vacuum vessel. 8 ) and an inert gas such as hydrogen, nitrogen or argon is introduced as the carrier gas, and the degree of vacuum is controlled to 1.3 to 13 Pa, for example. In this state, power is supplied to the conductive electrode plate provided with the gas introduction hole in the vacuum vessel to generate glow discharge, and the amorphous Si film 20 is formed on the surface of the substrate 1 disposed in the vacuum vessel. Form a film. In order to set the surface resistance of the amorphous Si film 3 within the range of 10 6 to 10 12 Ω / □, the amount of hydrogen may be controlled within a predetermined range. Note that the method of forming the amorphous Si film is not limited to using the CVD method.

最後に、基体１に形成された貫通孔１３に、例えばＴｉやＣｕからなる、導電性を有する支持部材２の一部を挿通し、例えば導電性接着剤やロウ付け等によって、挿通した支持部材２と基体１とを接合固定する。この際、支持部材２は、基体１の他方主面１ｂの側において、第２電極層５と電気的に接続される。   Finally, a part of the conductive support member 2 made of, for example, Ti or Cu is inserted into the through-hole 13 formed in the base 1 and inserted through, for example, a conductive adhesive or brazing. 2 and the substrate 1 are bonded and fixed. At this time, the support member 2 is electrically connected to the second electrode layer 5 on the side of the other main surface 1 b of the base 1.

静電チャック１０は、例えばこのように作製すればよい。   The electrostatic chuck 10 may be manufactured in this way, for example.

以上、本発明の一実施形態について詳細に説明したが、本発明は上記実施形態に限定されるものでなく、本発明の要旨を逸脱しない範囲において、各種の改良および変更を行ってもよいのはもちろんである。   As mentioned above, although one Embodiment of this invention was described in detail, this invention is not limited to the said embodiment, In the range which does not deviate from the summary of this invention, you may perform various improvement and change. Of course.

本発明の試料保持具の一実施形態である静電チャックを用いて構成される、ウエハ吸着機構について説明する図であり、（ａ）は概略上面図、（ｂ）は（ａ）の概略断面図である。It is a figure explaining the wafer adsorption | suction mechanism comprised using the electrostatic chuck which is one Embodiment of the sample holder of this invention, (a) is a schematic top view, (b) is a schematic cross section of (a). FIG. 図１に示す静電チャックによる、単結晶Ｓｉウエハの吸着状態について説明する図である。It is a figure explaining the adsorption | suction state of the single crystal Si wafer by the electrostatic chuck shown in FIG.

符号の説明Explanation of symbols

１ 基体
２ 支持部材
３ アモルファスＳｉ膜
４ 第１電極層
５ 第２電極層
１０ 静電チャック
２０ 電圧印加手段 DESCRIPTION OF SYMBOLS 1 Base body 2 Support member 3 Amorphous Si film 4 1st electrode layer 5 2nd electrode layer 10 Electrostatic chuck 20 Voltage application means

Claims (8)

試料を吸着して保持する試料保持具であって、
基体と、
前記基体の一方主面に設けられた電極層とを有し、
前記電極層の表面が、半導電性膜によって被覆されていることを特徴とする試料保持具。 A sample holder for adsorbing and holding a sample,
A substrate;
An electrode layer provided on one main surface of the substrate,
A sample holder, wherein a surface of the electrode layer is covered with a semiconductive film. 前記半導電性膜は、アモルファスＳｉからなることを特徴とする請求項１記載の試料保持具。   The sample holder according to claim 1, wherein the semiconductive film is made of amorphous Si. 前記半導電性膜の表面抵抗が、１０６〜１０１２（Ω／□）であることを特徴とする請求項１または２に記載の試料保持具。 The sample holder according to claim 1 or 2, wherein the semiconductive film has a surface resistance of 10 6 to 10 12 (Ω / □). 前記基体から突出して設けられた支持部を備え、
前記支持部の突出端が、前記半導電性膜の表面よりも、前記基体の前記一方主面から突出していることを特徴とする請求項１〜３のいずれかに記載の試料保持具。 A support portion provided protruding from the base body,
The sample holder according to any one of claims 1 to 3, wherein a protruding end of the support portion protrudes from the one main surface of the base rather than a surface of the semiconductive film. 前記基体は誘電体からなり、かつ前記支持部は導電性を有し、
前記支持部は、前記基体の前記一方主面から他方主面に向けて形成された貫通孔に挿通されて、前記他方主面の側に配された他方電極と電気的に接続していることを特徴とする請求項１〜４のいずれかに記載の試料保持具。 The base is made of a dielectric, and the support has conductivity.
The support portion is inserted through a through hole formed from the one main surface to the other main surface of the base body and is electrically connected to the other electrode disposed on the other main surface side. The sample holder according to any one of claims 1 to 4. 前記基体はセラミックスからなることを特徴とする請求項１〜５のいずれかに記載の試料保持具。   The sample holder according to claim 1, wherein the substrate is made of ceramics. 前記アモルファスＳｉ膜は、ＣＶＤ法によって成膜されていることを特徴とする請求項１〜６のいずれかに記載の試料保持具。   The sample holder according to claim 1, wherein the amorphous Si film is formed by a CVD method. 請求項１〜７のいずれかに記載の試料保持具と、
前記試料保持具を移動させる移動機構と、を備えて構成された搬送装置。 The sample holder according to any one of claims 1 to 7,
A transfer mechanism configured to move the sample holder.
JP2008279016A 2008-10-30 2008-10-30 Sample holder and transfer device Expired - Fee Related JP5225023B2 (en)

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