JP2010103260A - Method of manufacturing semiconductor device for power control - Google Patents

Method of manufacturing semiconductor device for power control Download PDF

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JP2010103260A
JP2010103260A JP2008272418A JP2008272418A JP2010103260A JP 2010103260 A JP2010103260 A JP 2010103260A JP 2008272418 A JP2008272418 A JP 2008272418A JP 2008272418 A JP2008272418 A JP 2008272418A JP 2010103260 A JP2010103260 A JP 2010103260A
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power control
semiconductor device
type silicon
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layer
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Shingo Sato
慎吾 佐藤
Yasuhisa Omuro
泰久 大室
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Toshiba Corp
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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for power control of which a breakdown voltage is high but an on-resistance is low. <P>SOLUTION: An n-type silicon layer 12 is formed on an n<SP>+</SP>type silicon wafer 11w, and a plurality of trenches 13 are formed in the n-type silicon layer 12. On the inner surface of the trench 13, a non-doped layer 14 containing substantially no impurities is formed. Then a p-type silicon peeler 15 is formed inside the trench 13. After that, an MOS structure is formed at the upper part of the n-type silicon layer 12. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、電力制御用半導体装置の製造方法に関し、特に、スーパージャンクション構造を備えた電力制御用半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a power control semiconductor device, and more particularly to a method for manufacturing a power control semiconductor device having a super junction structure.

高い耐圧と低いオン抵抗とを両立させた電力制御用半導体装置として、ｎ型の半導体層にｐ型の半導体ピラーを埋め込み、ｎ型部分とｐ型部分とを交互に配列させたスーパージャンクション構造（以下、「ＳＪ構造」ともいう）を持つ縦形ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor：金属酸化物半導体電界効果トランジスタ）が知られている。ＳＪ構造においては、ｎ型部分とｐ型部分に含まれる不純物量を相互に等しくすることで、擬似的にノンドープ層を作り出して高耐圧を保持しつつ、不純物濃度が高いｎ型部分を介して電流を流すことにより、低いオン抵抗を実現することができる。   As a power control semiconductor device that achieves both high breakdown voltage and low on-resistance, a super junction structure in which p-type semiconductor pillars are embedded in an n-type semiconductor layer and n-type portions and p-type portions are alternately arranged ( Hereinafter, a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a “SJ structure” is known. In the SJ structure, by making the amounts of impurities contained in the n-type part and the p-type part equal to each other, a pseudo non-doped layer is created and a high breakdown voltage is maintained, and the n-type part has a high impurity concentration. By flowing a current, a low on-resistance can be realized.

このようなＳＪ構造のＭＯＳＦＥＴを形成する方法の１つとして、ｎ＋型の半導体基板上にｎ型の半導体層をエピタキシャル成長法によって成長させ、この半導体層に複数本のトレンチを形成し、トレンチ内にｐ型半導体材料をエピタキシャル成長させてｐ型の半導体ピラーを形成する方法がある（例えば、特許文献１参照。）。 As one of the methods for forming such an SJ-structure MOSFET, an n-type semiconductor layer is grown on an n + -type semiconductor substrate by an epitaxial growth method, and a plurality of trenches are formed in the semiconductor layer. There is a method of forming a p-type semiconductor pillar by epitaxially growing a p-type semiconductor material (see, for example, Patent Document 1).

しかしながら、この方法においては、トレンチ内にｐ型の半導体ピラーを形成した後、ＭＯＳ構造を形成するための熱処理を行ったときに、ｐ型の半導体ピラーに含まれるアクセプタとｎ型の半導体層に含まれるドナーとが相互に拡散してしまい、実効的な不純物濃度が低下してしまうという問題がある。ｐ型の半導体ピラー及びｎ型の半導体層の実効的な不純物濃度が低下することにより、耐圧が低下し、また、ｎ型の半導体層の実効的な不純物濃度が低下することにより、オン抵抗が増大してしまう。そして、この傾向は、半導体装置の微細化に伴い、より顕著になる。   However, in this method, after the p-type semiconductor pillar is formed in the trench and then heat treatment for forming the MOS structure is performed, the acceptor and the n-type semiconductor layer included in the p-type semiconductor pillar are formed. There is a problem that the contained impurity diffuses mutually and the effective impurity concentration decreases. By reducing the effective impurity concentration of the p-type semiconductor pillar and the n-type semiconductor layer, the breakdown voltage is reduced, and by reducing the effective impurity concentration of the n-type semiconductor layer, the on-resistance is reduced. It will increase. This tendency becomes more prominent with the miniaturization of semiconductor devices.

特開２００７−２３５０８０号公報Japanese Patent Laid-Open No. 2007-235080

本発明の目的は、耐圧が高くオン抵抗が低い電力制御用半導体装置の製造方法を提供することである。   An object of the present invention is to provide a method for manufacturing a power control semiconductor device having a high breakdown voltage and a low on-resistance.

本発明の一態様によれば、第１導電型の半導体層に複数本のトレンチを形成する工程と、前記トレンチの側面上に、不純物が実質的に含まれていないノンドープ層を形成する工程と、前記トレンチの内部に第２導電型の半導体ピラーを形成する工程と、を備えたことを特徴とする電力制御用半導体装置の製造方法が提供される。   According to one aspect of the present invention, a step of forming a plurality of trenches in a first conductivity type semiconductor layer, and a step of forming a non-doped layer substantially free of impurities on a side surface of the trench, And a step of forming a second-conductivity-type semiconductor pillar inside the trench. A method for manufacturing a power control semiconductor device is provided.

本発明によれば、耐圧が高くオン抵抗が低い電力制御用半導体装置の製造方法を実現することができる。   According to the present invention, it is possible to realize a method for manufacturing a power control semiconductor device having a high breakdown voltage and a low on-resistance.

以下、本発明の実施形態について図面を参照しながら説明する。
先ず、本発明の第１の実施形態について説明する。
図１（ａ）及び（ｂ）、図２（ａ）及び（ｂ）は、本実施形態に係る電力制御用半導体装置の製造方法を例示する工程断面図である。
本実施形態に係る電力制御用半導体装置は、スーパージャンクション構造（ＳＪ構造）と縦形のＭＯＳＦＥＴが形成された半導体チップであり、例えば、耐圧が６００Ｖの半導体チップである。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention will be described.
FIGS. 1A and 1B and FIGS. 2A and 2B are process cross-sectional views illustrating a method for manufacturing a power control semiconductor device according to this embodiment.
The power control semiconductor device according to the present embodiment is a semiconductor chip in which a super junction structure (SJ structure) and a vertical MOSFET are formed, for example, a semiconductor chip having a withstand voltage of 600V.

先ず、図１（ａ）に示すように、ｎ＋型の単結晶シリコンからなるウェーハ１１ｗを用意する。そして、ウェーハ１１ｗの上面上にｎ型のシリコンをエピタキシャル成長させて、ｎ型シリコン層１２を形成する。ｎ型シリコン層１２にはドナー、例えば、リン（Ｐ）が含有されており、その濃度は例えば１×１０１５〜１×１０１６ｃｍ−３である。 First, as shown in FIG. 1A, a wafer 11w made of n + type single crystal silicon is prepared. Then, n-type silicon is epitaxially grown on the upper surface of the wafer 11w to form the n-type silicon layer 12. The n-type silicon layer 12 contains a donor, for example, phosphorus (P), and the concentration thereof is, for example, 1 × 10 15 to 1 × 10 16 cm −3 .

次に、ｎ型シリコン層１２の上面側からｎ型シリコン層１２の途中まで、ｎ型シリコン層１２の上面に平行な一方向（以下、「ピラー方向」という）に延びるトレンチ１３を複数本形成する。一例では、トレンチ１３の幅は５μｍとし、配列周期は８μｍとし、深さは５０μｍとする。   Next, a plurality of trenches 13 extending in one direction parallel to the upper surface of the n-type silicon layer 12 (hereinafter referred to as “pillar direction”) from the upper surface side of the n-type silicon layer 12 to the middle of the n-type silicon layer 12 are formed. To do. In one example, the width of the trench 13 is 5 μm, the arrangement period is 8 μm, and the depth is 50 μm.

次に、図１（ｂ）に示すように、ｎ型シリコン層１２の上面をシリコン酸化膜（図示せず）により覆った上で、ＣＶＤ（Chemical Vapor Deposition：化学気相成長）を行い、トレンチ１３の内面上に、不純物を添加していないシリコンをエピタキシャル成長させる。このＣＶＤの条件は、例えば、原料をジクロロシラン（ＤＣＳ）とし、温度を１０００℃とする。これにより、トレンチ１３の内面上に、不純物が実質的に含まれていないノンドープ層１４が形成される。一例では、トレンチ１３の側面上におけるノンドープ層１４の膜厚は、０．５μｍとする。   Next, as shown in FIG. 1B, after the upper surface of the n-type silicon layer 12 is covered with a silicon oxide film (not shown), CVD (Chemical Vapor Deposition) is performed to form a trench. Silicon on which no impurities are added is epitaxially grown on the inner surface of 13. The CVD conditions are, for example, that the raw material is dichlorosilane (DCS) and the temperature is 1000 ° C. As a result, a non-doped layer 14 substantially free of impurities is formed on the inner surface of the trench 13. In one example, the film thickness of the non-doped layer 14 on the side surface of the trench 13 is 0.5 μm.

次に、図２（ａ）に示すように、引き続きＣＶＤ法を行い、ドーパントとして例えばＢ２Ｈ６を導入する。これにより、ノンドープ層１４上において、アクセプタとして例えばボロン（Ｂ）が添加されたシリコンがエピタキシャル成長する。この結果、トレンチ１３の内部にｐ型シリコンピラー１５が形成される。その後、ｎ型シリコン層１２の上面をＣＭＰ（Chemical Mechanical Polishing：化学的機械研磨）により平坦化する。 Next, as shown in FIG. 2A, the CVD method is subsequently performed, and for example, B 2 H 6 is introduced as a dopant. Thereby, on the non-doped layer 14, for example, silicon to which boron (B) is added as an acceptor is epitaxially grown. As a result, the p-type silicon pillar 15 is formed inside the trench 13. Thereafter, the upper surface of the n-type silicon layer 12 is planarized by CMP (Chemical Mechanical Polishing).

次に、図２（ｂ）に示すように、通常の方法により、ｐ型シリコンピラー１５の上端部に、ピラー方向に延びるストライプ状のｐ型のベース領域１６を形成する。次に、ベース領域１６の内部に、ピラー方向に延び相互に離隔した２本のｎ＋型のソース領域１７（拡散領域）を形成し、ソース領域１７間の領域に、ピラー方向に延びる１本のｐ＋型のコンタクト領域１８を形成する。そして、ｎ型シリコン層１２上にゲート電極２１及びゲート絶縁膜２２を形成する。例えば、ゲート電極２１はポリシリコンにより形成し、ゲート絶縁膜２２はシリコン酸化物により形成する。これにより、ウェーハ１１ｗの上面にＭＯＳ構造が作製される。このとき、このＭＯＳ構造の作製に伴い、ウェーハ１１ｗ全体が加熱され、各層の不純物が拡散する。この結果、ｎ型シリコン層１２内に含まれるリン（Ｐ）の一部とｐ型シリコンピラー１５内に含まれるボロン（Ｂ）の一部がノンドープ層１４（図２（ａ）参照）内に拡散し、ノンドープ層１４が消失すると共に、ｐｎ接合面が形成される。 Next, as shown in FIG. 2B, a striped p-type base region 16 extending in the pillar direction is formed at the upper end of the p-type silicon pillar 15 by a normal method. Next, two n + -type source regions 17 (diffusion regions) extending in the pillar direction and spaced apart from each other are formed inside the base region 16, and one line extending in the pillar direction is formed between the source regions 17. The p + -type contact region 18 is formed. Then, a gate electrode 21 and a gate insulating film 22 are formed on the n-type silicon layer 12. For example, the gate electrode 21 is formed of polysilicon, and the gate insulating film 22 is formed of silicon oxide. Thereby, a MOS structure is formed on the upper surface of the wafer 11w. At this time, as the MOS structure is manufactured, the entire wafer 11w is heated, and impurities in each layer are diffused. As a result, a part of phosphorus (P) contained in the n-type silicon layer 12 and a part of boron (B) contained in the p-type silicon pillar 15 are in the non-doped layer 14 (see FIG. 2A). As a result of diffusion, the non-doped layer 14 disappears and a pn junction surface is formed.

次に、ｎ型シリコン層１２上に、ゲート電極２１及びゲート絶縁膜２２を覆い、ソース領域１７に接続されるように、ソース電極２３を形成する。一方、ウェーハ１１ｗの下面上には、ウェーハ１１ｗに接続されるようにドレイン電極２４を形成する。ソース電極２３及びドレイン電極２４は例えば金属により形成する。その後、ウェーハ１１ｗをダイシングし、複数のｎ＋型シリコン基板１１に切り分ける。これにより、本実施形態に係る電力制御用半導体装置１が製造される。 Next, the source electrode 23 is formed on the n-type silicon layer 12 so as to cover the gate electrode 21 and the gate insulating film 22 and to be connected to the source region 17. On the other hand, a drain electrode 24 is formed on the lower surface of the wafer 11w so as to be connected to the wafer 11w. The source electrode 23 and the drain electrode 24 are made of metal, for example. Thereafter, the wafer 11 w is diced and cut into a plurality of n + type silicon substrates 11. Thereby, the power control semiconductor device 1 according to the present embodiment is manufactured.

このようにして製造された電力制御用半導体装置１においては、ｎ型シリコン層１２内において、ｐ型シリコンピラー１５と、ｎ型シリコン層１２におけるｐ型シリコンピラー１５間の部分とが交互に配列されて、スーパージャンクション構造（ＳＪ構造）が形成される。   In the power control semiconductor device 1 manufactured as described above, the p-type silicon pillars 15 and the portions between the p-type silicon pillars 15 in the n-type silicon layer 12 are alternately arranged in the n-type silicon layer 12. Thus, a super junction structure (SJ structure) is formed.

次に、本実施形態の作用効果について説明する。
図３は、横軸に位置をとり、縦軸に不純物濃度をとって、本実施形態に係る電力制御用半導体装置内における不純物濃度プロファイルを例示するグラフ図である。
なお、図３の横軸は、ｐ型シリコンピラーの配列方向における位置を表している。また、図３の縦軸は、原点「０」を基準として、上側はアクセプタ（ｐ型不純物）の濃度を表し、下側はドナー（ｎ型不純物）の濃度を表している。後述する図５、図９、図１１についても同様である。更に、図３に示す破線は図２（ａ）に示すＡ−Ａ’線上のアクセプタ濃度及びドナー濃度を表し、一点鎖線は図２（ｂ）に示すＢ−Ｂ’線上のアクセプタ濃度及びドナー濃度を表し、実線は図２（ｂ）に示すＢ−Ｂ’線上の実効的な不純物濃度を表している。 Next, the effect of this embodiment is demonstrated.
FIG. 3 is a graph illustrating an impurity concentration profile in the power control semiconductor device according to the present embodiment, with the position on the horizontal axis and the impurity concentration on the vertical axis.
The horizontal axis in FIG. 3 represents the position in the arrangement direction of the p-type silicon pillars. The vertical axis of FIG. 3 represents the concentration of the acceptor (p-type impurity) on the upper side and the concentration of the donor (n-type impurity) on the lower side with respect to the origin “0”. The same applies to FIGS. 5, 9, and 11 to be described later. Further, the broken line shown in FIG. 3 represents the acceptor concentration and the donor concentration on the AA ′ line shown in FIG. 2A, and the alternate long and short dash line represents the acceptor concentration and the donor concentration on the BB ′ line shown in FIG. The solid line represents the effective impurity concentration on the line BB ′ shown in FIG.

図３に破線で示すように、不純物の拡散前、すなわち、図２（ａ）に示す工程においては、不純物濃度プロファイルは急峻であり、ｐ型シリコンピラー１５に含まれるアクセプタのピークと、ｎ型シリコン層１２に含まれるドナーのピークとは、ノンドープ層１４を挟んで相互に離隔している。   As shown by a broken line in FIG. 3, before impurity diffusion, that is, in the step shown in FIG. 2A, the impurity concentration profile is steep, and the acceptor peak contained in the p-type silicon pillar 15 and the n-type The donor peaks contained in the silicon layer 12 are separated from each other across the non-doped layer 14.

そして、図３に一点鎖線で示すように、ＭＯＳ構造の作製に伴う熱処理により、アクセプタ及びドナーはそれぞれ拡散し、ピークがブロードになる。しかしながら、拡散前におけるアクセプタ及びドナーのピークはノンドープ層１４を挟んで相互に離隔していたため、それぞれがブロードになっても重なり合う領域は少なく、アクセプタの効果とドナーの効果との相殺は少ない。この結果、図３に実線で示すように、実効的なアクセプタ濃度及びドナー濃度を高く維持することができる。   Then, as indicated by the one-dot chain line in FIG. 3, the acceptor and the donor are diffused by the heat treatment accompanying the fabrication of the MOS structure, and the peak becomes broad. However, since the acceptor and donor peaks before diffusion are separated from each other with the non-doped layer 14 interposed therebetween, there are few overlapping regions even when each of them becomes broad, and there is little cancellation between the acceptor effect and the donor effect. As a result, as shown by a solid line in FIG. 3, the effective acceptor concentration and donor concentration can be kept high.

これにより、本実施形態に係る電力制御用半導体装置１においては、ｐ型シリコンピラー１５とｎ型シリコン層１２との間のｐｎ界面の不純物濃度プロファイルを急峻に保つことができるため、耐圧を高く維持することができる。また、ｎ型シリコン層１２における実効的なドナー濃度を高く維持することができるため、オン抵抗を低く保つことができる。更に、アクセプタとドナーの相殺を抑制することができるため、電力制御用半導体装置の微細化が容易になる。   Thereby, in the power control semiconductor device 1 according to the present embodiment, the impurity concentration profile at the pn interface between the p-type silicon pillar 15 and the n-type silicon layer 12 can be kept steep, so that the breakdown voltage is increased. Can be maintained. In addition, since the effective donor concentration in the n-type silicon layer 12 can be kept high, the on-resistance can be kept low. Furthermore, since cancellation of the acceptor and the donor can be suppressed, miniaturization of the power control semiconductor device is facilitated.

次に、本実施形態の比較例について説明する。
図４は、本比較例に係る電力制御用半導体装置の製造方法を例示する工程断面図であり、
図５は、横軸に位置をとり、縦軸に不純物濃度をとって、本比較例に係る電力制御用半導体装置内における不純物濃度プロファイルを例示するグラフ図である。
なお、図５に示す破線は図４に示すＣ−Ｃ’線上のアクセプタ濃度及びドナー濃度を表し、一点鎖線は拡散後のアクセプタ濃度及びドナー濃度をそれぞれ表し、実線は拡散後の実効的な不純物濃度を表している。 Next, a comparative example of this embodiment will be described.
FIG. 4 is a process cross-sectional view illustrating a method for manufacturing a power control semiconductor device according to this comparative example.
FIG. 5 is a graph illustrating the impurity concentration profile in the power control semiconductor device according to this comparative example, with the position on the horizontal axis and the impurity concentration on the vertical axis.
5 represents the acceptor concentration and the donor concentration on the CC ′ line shown in FIG. 4, the alternate long and short dash line represents the acceptor concentration and the donor concentration after diffusion, and the solid line represents an effective impurity after the diffusion. Represents the concentration.

本比較例においては、図１（ａ）に示すように、ウェーハ１１ｗ上に形成されたｎ型シリコン層１２にトレンチ１３を形成した後、図４に示すように、ノンドープ層１４（図１（ｂ）参照）を形成することなく、トレンチ１３の内面上にｐ型のシリコンをエピタキシャル成長させて、トレンチ１３内にｐ型シリコンピラー１５を形成する。以後の製造方法は、前述の第１の実施形態と同様である。   In this comparative example, as shown in FIG. 1A, after forming the trench 13 in the n-type silicon layer 12 formed on the wafer 11w, as shown in FIG. 4, the non-doped layer 14 (FIG. Without forming b), p-type silicon is epitaxially grown on the inner surface of the trench 13 to form the p-type silicon pillar 15 in the trench 13. The subsequent manufacturing method is the same as that in the first embodiment.

図５に破線で示すように、本比較例においても、拡散前の不純物濃度プロファイルは急峻である。但し、ノンドープ層１４（図１（ｂ）参照）が設けられていないため、ｐ型シリコンピラー１５に含まれるアクセプタのピークと、ｎ型シリコン層１２に含まれるドナーのピークとは、相互に接している。   As indicated by a broken line in FIG. 5, the impurity concentration profile before diffusion is steep in this comparative example. However, since the non-doped layer 14 (see FIG. 1B) is not provided, the acceptor peak contained in the p-type silicon pillar 15 and the donor peak contained in the n-type silicon layer 12 are in contact with each other. ing.

そして、図５に一点鎖線で示すように、ＭＯＳ構造の作製に伴う熱処理により、アクセプタ及びドナーはそれぞれ拡散し、ピークがブロードになる。これにより、アクセプタのピークとドナーのピークとが広い領域において重なり合い、アクセプタの効果とドナーの効果とが相殺される。この結果、図５に実線で示すように、ｐ型シリコンピラー１５における実効的なアクセプタ濃度及びｎ型シリコン層１２における実効的なドナー濃度が減少するため、耐圧が低下する。また、ｎ型シリコン層１２における実効的なドナー濃度が減少することにより、オン抵抗が増加する。   Then, as shown by a one-dot chain line in FIG. 5, the acceptor and the donor are diffused by the heat treatment accompanying the fabrication of the MOS structure, and the peak becomes broad. Thereby, the acceptor peak and the donor peak overlap in a wide region, and the effect of the acceptor and the effect of the donor are offset. As a result, as shown by a solid line in FIG. 5, the effective acceptor concentration in the p-type silicon pillar 15 and the effective donor concentration in the n-type silicon layer 12 are reduced, so that the breakdown voltage is lowered. In addition, the on-resistance is increased by reducing the effective donor concentration in the n-type silicon layer 12.

次に、本発明の第２の実施形態について説明する。
図６（ａ）及び（ｂ）、図７（ａ）及び（ｂ）、図８（ａ）及び（ｂ）は、本実施形態に係る電力制御用半導体装置の製造方法を例示する工程断面図である。
本実施形態に係る電力制御用半導体装置も、前述の第１の実施形態と同様に、ＳＪ構造と縦形のＭＯＳＦＥＴが形成された半導体チップである。 Next, a second embodiment of the present invention will be described.
FIGS. 6A and 6B, FIGS. 7A and 7B, and FIGS. 8A and 8B are process cross-sectional views illustrating a method for manufacturing a power control semiconductor device according to this embodiment. It is.
The power control semiconductor device according to the present embodiment is also a semiconductor chip in which an SJ structure and a vertical MOSFET are formed, as in the first embodiment.

先ず、図６（ａ）に示すように、ｎ＋型の単結晶シリコンからなるウェーハ１１ｗの上面上に、ｎ−型のシリコンをエピタキシャル成長させて、ｎ−型シリコン層３２を形成する。ｎ−型シリコン層３２のドナー濃度は、前述の第１の実施形態におけるｎ型シリコン層１２（図１（ａ）参照）のドナー濃度よりも低い。次に、ｎ−型シリコン層３２に、一方向に延びるトレンチ１３を複数本形成する。 First, as shown in FIG. 6A, n − type silicon layer 32 is formed by epitaxially growing n − type silicon on the upper surface of wafer 11w made of n + type single crystal silicon. The donor concentration of the n − -type silicon layer 32 is lower than the donor concentration of the n-type silicon layer 12 (see FIG. 1A) in the first embodiment described above. Next, a plurality of trenches 13 extending in one direction are formed in the n − type silicon layer 32.

次に、図６（ｂ）に示すように、トレンチ１３の側面に対して、ドナー（ｎ型不純物）を注入する。このドナーの注入は、ｎ−型シリコン層３２の上面に垂直な方向に対して、トレンチ１３の配列方向に例えば２．５〜３．５度傾斜した方向から行う。これにより、図７（ａ）に示すように、トレンチ１３の側面にドナーが導入され、ｎ＋型拡散層３３が形成される。 Next, as shown in FIG. 6B, a donor (n-type impurity) is implanted into the side surface of the trench 13. The donor implantation is performed from a direction inclined by, for example, 2.5 to 3.5 degrees with respect to the arrangement direction of the trenches 13 with respect to the direction perpendicular to the upper surface of the n − -type silicon layer 32. As a result, as shown in FIG. 7A, donors are introduced into the side surfaces of the trench 13 to form the n + -type diffusion layer 33.

次に、図７（ｂ）に示すように、ｎ−型シリコン層３２の上面をシリコン酸化膜（図示せず）により覆った上でＣＶＤを行い、トレンチ１３の内面上、すなわち、ｎ＋型拡散層３３上に、不純物を添加していないシリコンをエピタキシャル成長させる。これにより、ｎ＋型拡散層３３を覆うように、不純物が実質的に含まれていないノンドープ層１４が形成される。 Next, as shown in FIG. 7B, the upper surface of the n − -type silicon layer 32 is covered with a silicon oxide film (not shown), and then CVD is performed to form an n + -type on the inner surface of the trench 13. On the diffusion layer 33, silicon not doped with impurities is epitaxially grown. Thereby, the non-doped layer 14 substantially free of impurities is formed so as to cover the n + -type diffusion layer 33.

以後の製造方法は、前述の第１の実施形態と同様である。すなわち、図８（ａ）に示すように、ノンドープ層１４上に、アクセプタとして例えばボロン（Ｂ）が添加されたシリコンがエピタキシャル成長させて、トレンチ１３内にｐ型シリコンピラー１５を埋設する。そして、ＣＭＰを行い、上面を平坦化する。次に、図８（ｂ）に示すように、ベース領域１６、ソース領域１７、コンタクト領域１８、ゲート電極２１、ゲート絶縁膜２２、ソース電極２３及びドレイン電極２４を形成する。これにより、電力用半導体装置２が製造される。本実施形態における上記以外の製造方法は、前述の第１の実施形態と同様である。   The subsequent manufacturing method is the same as that in the first embodiment. That is, as shown in FIG. 8A, silicon doped with, for example, boron (B) as an acceptor is epitaxially grown on the non-doped layer 14 to bury the p-type silicon pillar 15 in the trench 13. Then, CMP is performed to flatten the upper surface. Next, as shown in FIG. 8B, a base region 16, a source region 17, a contact region 18, a gate electrode 21, a gate insulating film 22, a source electrode 23, and a drain electrode 24 are formed. Thereby, the power semiconductor device 2 is manufactured. The manufacturing method other than the above in this embodiment is the same as that in the first embodiment.

次に、本実施形態の作用効果について説明する。
図９は、横軸に位置をとり、縦軸に不純物濃度をとって、本実施形態に係る電力制御用半導体装置内における不純物濃度プロファイルを例示するグラフ図である。
なお、図９に示す破線は図８（ａ）に示すＤ−Ｄ’線上のアクセプタ濃度及びドナー濃度を表し、一点鎖線は図８（ｂ）に示すＥ−Ｅ’線上のアクセプタ濃度及びドナー濃度を表し、実線は図８（ｂ）に示すＥ−Ｅ’線上の実効的な不純物濃度を表している。 Next, the effect of this embodiment is demonstrated.
FIG. 9 is a graph illustrating an impurity concentration profile in the power control semiconductor device according to this embodiment, with the position on the horizontal axis and the impurity concentration on the vertical axis.
9 represents the acceptor concentration and the donor concentration on the DD ′ line shown in FIG. 8A, and the alternate long and short dash line represents the acceptor concentration and the donor concentration on the EE ′ line shown in FIG. 8B. The solid line represents the effective impurity concentration on the line EE ′ shown in FIG.

図９に破線で示すように、不純物の拡散前、すなわち、図８（ａ）に示す工程においては、ｐ型シリコンピラー１５の配列方向に沿った不純物濃度プロファイルにおいて、ｐ型シリコンピラー１５に相当する位置にアクセプタのピークが存在し、ｎ＋型拡散層３３に相当する位置にドナーのピークが存在する。すなわち、１本のアクセプタのピークの両側にドナーのピークがそれぞれ形成される。また、拡散前の不純物濃度プロファイルは全体的に急峻であり、ｐ型シリコンピラー１５に含まれるアクセプタのピークと、ｎ＋型拡散層３３に含まれるドナーのピークとは、ノンドープ層１４を挟んで相互に離隔している。 As shown by a broken line in FIG. 9, before impurity diffusion, that is, in the step shown in FIG. 8A, the impurity concentration profile along the arrangement direction of the p-type silicon pillar 15 corresponds to the p-type silicon pillar 15. The acceptor peak exists at a position corresponding to the n + -type diffusion layer 33, and the donor peak exists at a position corresponding to the n + -type diffusion layer 33. That is, donor peaks are formed on both sides of one acceptor peak. The impurity concentration profile before diffusion is generally steep, and the acceptor peak contained in the p-type silicon pillar 15 and the donor peak contained in the n + -type diffusion layer 33 sandwich the non-doped layer 14. They are separated from each other.

そして、本実施形態においても、前述の第１の実施形態と同様に、拡散前のアクセプタのピークとドナーのピークとが相互に離隔しているため、図９に一点鎖線で示すように、熱処理後においても、ピーク同士の重なり合いが少なく、アクセプタの効果とドナーの効果との相殺が少ない。これにより、図９に実線で示すように、実効的なアクセプタ濃度及びドナー濃度を高く維持することができる。この結果、本実施形態に係る電力制御用半導体装置２においても、耐圧を高く維持することができると共に、オン抵抗を低く保つことができる。   Also in this embodiment, since the acceptor peak and the donor peak before diffusion are separated from each other as in the first embodiment, the heat treatment is performed as shown by the one-dot chain line in FIG. Later, there is little overlap between peaks, and there is little cancellation between the acceptor effect and the donor effect. Thereby, as shown by a solid line in FIG. 9, the effective acceptor concentration and donor concentration can be maintained high. As a result, also in the power control semiconductor device 2 according to the present embodiment, the withstand voltage can be kept high and the on-resistance can be kept low.

また、本実施形態によれば、ｎ＋型拡散層３３を形成することにより、トレンチ１３の側面に沿って電流経路を形成することができる。これにより、電力制御用半導体装置２のオン抵抗を低減することができる。更に、装置２の終端部の耐圧を確保するためには、終端部におけるエピタキシャル層の不純物濃度を低くすることが好ましいが、本実施形態においては、ｎ＋型拡散層３３を形成することにより、その分、ｎ−型シリコン層３２の不純物濃度を低くすることができる。このため、セル部と終端部とでエピタキシャル層を作り分ける必要がなく、製造が容易である。 Further, according to the present embodiment, the current path can be formed along the side surface of the trench 13 by forming the n + -type diffusion layer 33. Thereby, the on-resistance of the power control semiconductor device 2 can be reduced. Furthermore, in order to ensure the breakdown voltage of the terminal portion of the device 2, it is preferable to lower the impurity concentration of the epitaxial layer in the terminal portion, but in this embodiment, by forming the n + -type diffusion layer 33, Accordingly, the impurity concentration of the n − type silicon layer 32 can be lowered. For this reason, it is not necessary to make an epitaxial layer separately for the cell portion and the terminal portion, and the manufacturing is easy.

次に、第２の実施形態の変形例について説明する。
図１０は、本変形例に係る電力制御用半導体装置の製造方法を例示する工程断面図であり、
図１１は、横軸に位置をとり、縦軸に不純物濃度をとって、本変形例に係る電力制御用半導体装置内における不純物濃度プロファイルを例示するグラフ図である。
なお、図１１に示す破線は不純物拡散前のアクセプタ濃度及びドナー濃度を表し、一点鎖線は拡散後のアクセプタ濃度及びドナー濃度を表し、実線は拡散後の実効的な不純物濃度を表している。 Next, a modification of the second embodiment will be described.
FIG. 10 is a process cross-sectional view illustrating a method for manufacturing a power control semiconductor device according to this variation.
FIG. 11 is a graph illustrating an impurity concentration profile in the power control semiconductor device according to this modification, with the position on the horizontal axis and the impurity concentration on the vertical axis.
In addition, the broken line shown in FIG. 11 represents the acceptor density | concentration and donor density | concentration before impurity diffusion, the dashed-dotted line represents the acceptor density | concentration and donor density | concentration after diffusion, and the continuous line represents the effective impurity density | concentration after diffusion.

先ず、図６（ａ）〜図７（ａ）に示す方法により、ウェーハ１１ｗの上面上にｎ−型シリコン層３２を形成し、ｎ−型シリコン層３２にトレンチ１３を複数本形成する。そして、トレンチ１３の側面に対してドナーを注入することにより、トレンチ１３の側面にｎ＋型拡散層３３を形成する。 First, an n − -type silicon layer 32 is formed on the upper surface of the wafer 11 w and a plurality of trenches 13 are formed in the n − -type silicon layer 32 by the method shown in FIGS. 6 (a) to 7 (a). Then, an n + -type diffusion layer 33 is formed on the side surface of the trench 13 by injecting a donor into the side surface of the trench 13.

次に、図１０に示すように、熱処理を行う。これにより、ｎ＋型拡散層３３に含有されていたドナーの一部が、ｎ−型シリコン層３２内に拡散する。以後の製造方法は、図７（ｂ）〜図８（ｂ）に示す方法と同様である。 Next, heat treatment is performed as shown in FIG. Thereby, a part of the donor contained in the n + -type diffusion layer 33 diffuses into the n − -type silicon layer 32. The subsequent manufacturing method is the same as the method shown in FIGS. 7B to 8B.

図１１に示すように、本変形例によれば、トレンチ１３の側面にｎ＋型拡散層３３を形成した後、熱処理を行うことにより、ｎ＋型拡散層３３に含まれていたドナーの一部がｎ−型シリコン層３２内に拡散する。これにより、ドナーのピークがトレンチ１３から離隔する方向に移動する。そして、その後、トレンチ１３内にｐ型シリコンピラー１５を埋設することにより、ドナーのピークとアクセプタのピークとをより一層離隔させることができる。この結果、熱拡散後の実効的な不純物濃度を、より高く維持することができる。本変形例における上記以外の製造方法及び作用効果は、前述の第２の実施形態と同様である。 As shown in FIG. 11, according to this modified example, after forming the n + -type diffusion layer 33 on the side surfaces of the trenches 13, by heat treatment, n + -type diffusion layer of the donor that were included in the 33 one Part diffuses into the n − -type silicon layer 32. As a result, the donor peak moves away from the trench 13. Then, by embedding the p-type silicon pillar 15 in the trench 13, the donor peak and the acceptor peak can be further separated. As a result, the effective impurity concentration after thermal diffusion can be maintained higher. The manufacturing method and operational effects other than those described above in the present modification are the same as those in the second embodiment described above.

以上、実施形態及びその変形例を参照して本発明を説明したが、本発明はこれらの実施形態及びその変形例に限定されるものではない。例えば、前述の各実施形態及びその変形例に対して、当業者が適宜、構成要素の追加、削除若しくは設計変更を行ったもの、又は、工程の追加、省略若しくは条件変更を行ったものも、本発明の要旨を備えている限り、本発明の範囲に含有される。   As mentioned above, although this invention was demonstrated with reference to embodiment and its modification, this invention is not limited to these embodiment and its modification. For example, for each of the above-described embodiments and modifications thereof, a person skilled in the art appropriately added, deleted, or changed a design, or added a process, omitted, or changed a condition. As long as the gist of the present invention is provided, it is included in the scope of the present invention.

例えば、前述の各実施形態及びその変形例においては、第１の導電型をｎ型、第２の導電型をｐ型として説明したが、本発明は第１の導電型をｐ型、第２の導電型をｎ型としても実施可能である。また、ｎ＋型シリコン基板１１とｎ型シリコン層１２との間に、不純物濃度がｎ型シリコン層１２の不純物濃度よりも低いｎ−型バッファ層を設けてもよい。更に、前述の各実施形態及びその変形例においては、プレナー型ＭＯＳゲート構造を持つ半導体チップを例に挙げて説明したが、本発明に係る半導体チップは、トレンチ型ＭＯＳゲート構造（ＵＭＯＳ構造）を用いても実施可能である。更にまた、前述の各実施形態及びその変形例においては、半導体としてシリコン（Ｓｉ）を用いる例を示したが、半導体には例えば、シリコンカーバイト（ＳｉＣ）若しくは窒化ガリウム（ＧａＮ）等の化合物半導体、又は、ダイアモンド等のワイドバンドギャップ半導体を用いることもできる。 For example, in each of the above-described embodiments and modifications thereof, the first conductivity type is described as n-type and the second conductivity type is defined as p-type. However, the present invention describes that the first conductivity type is p-type and second It is also possible to use n type conductivity. Further, an n − -type buffer layer having an impurity concentration lower than that of the n-type silicon layer 12 may be provided between the n + -type silicon substrate 11 and the n-type silicon layer 12. Furthermore, in each of the above-described embodiments and modifications thereof, the semiconductor chip having a planar MOS gate structure has been described as an example. However, the semiconductor chip according to the present invention has a trench MOS gate structure (UMOS structure). It can be implemented even if it is used. Furthermore, in each of the above-described embodiments and modifications thereof, an example in which silicon (Si) is used as a semiconductor has been shown. For example, a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) is used as the semiconductor Alternatively, a wide band gap semiconductor such as diamond can be used.

（ａ）及び（ｂ）は、本発明の第１の実施形態に係る電力制御用半導体装置の製造方法を例示する工程断面図である。(A) And (b) is process sectional drawing which illustrates the manufacturing method of the semiconductor device for electric power control which concerns on the 1st Embodiment of this invention. （ａ）及び（ｂ）は、第１の実施形態に係る電力制御用半導体装置の製造方法を例示する工程断面図である。FIGS. 5A and 5B are process cross-sectional views illustrating the method for manufacturing the power control semiconductor device according to the first embodiment. FIGS. 横軸に位置をとり、縦軸に不純物濃度をとって、第１の実施形態に係る電力制御用半導体装置内における不純物濃度プロファイルを例示するグラフ図である。FIG. 6 is a graph illustrating an impurity concentration profile in the power control semiconductor device according to the first embodiment, with the horizontal axis representing the position and the vertical axis representing the impurity concentration. 第１の実施形態の比較例に係る電力制御用半導体装置の製造方法を例示する工程断面図である。11 is a process cross-sectional view illustrating a method for manufacturing the power control semiconductor device according to the comparative example of the first embodiment; FIG. 横軸に位置をとり、縦軸に不純物濃度をとって、比較例に係る電力制御用半導体装置内における不純物濃度プロファイルを例示するグラフ図である。FIG. 11 is a graph illustrating an impurity concentration profile in a power control semiconductor device according to a comparative example, with the position on the horizontal axis and the impurity concentration on the vertical axis. （ａ）及び（ｂ）は、本発明の第２の実施形態に係る電力制御用半導体装置の製造方法を例示する工程断面図である。(A) And (b) is process sectional drawing which illustrates the manufacturing method of the semiconductor device for electric power control which concerns on the 2nd Embodiment of this invention. （ａ）及び（ｂ）は、第２の実施形態に係る電力制御用半導体装置の製造方法を例示する工程断面図である。(A) And (b) is process sectional drawing which illustrates the manufacturing method of the semiconductor device for electric power control which concerns on 2nd Embodiment. （ａ）及び（ｂ）は、第２の実施形態に係る電力制御用半導体装置の製造方法を例示する工程断面図である。(A) And (b) is process sectional drawing which illustrates the manufacturing method of the semiconductor device for electric power control which concerns on 2nd Embodiment. 横軸に位置をとり、縦軸に不純物濃度をとって、第２の実施形態に係る電力制御用半導体装置内における不純物濃度プロファイルを例示するグラフ図である。FIG. 10 is a graph illustrating an impurity concentration profile in the power control semiconductor device according to the second embodiment, with the position on the horizontal axis and the impurity concentration on the vertical axis. 第２の実施形態の変形例に係る電力制御用半導体装置の製造方法を例示する工程断面図である。FIG. 10 is a process cross-sectional view illustrating a method for manufacturing a power control semiconductor device according to a variation of the second embodiment. 横軸に位置をとり、縦軸に不純物濃度をとって、第２の実施形態の変形例に係る電力制御用半導体装置内における不純物濃度プロファイルを例示するグラフ図である。FIG. 10 is a graph illustrating an impurity concentration profile in a power control semiconductor device according to a modification of the second embodiment, with the horizontal axis representing the position and the vertical axis representing the impurity concentration.

符号の説明Explanation of symbols

１、２ 電力制御用半導体装置、１１ ｎ＋型シリコン基板、１１ｗ ウェーハ、１２ ｎ型シリコン層、１３ トレンチ、１４ ノンドープ層、１５ ｐ型シリコンピラー、１６ ベース領域、１７ ソース領域、１８ コンタクト領域、２１ ゲート電極、２２ ゲート絶縁膜、２３ ソース電極、２４ ドレイン電極、３２ ｎ−型シリコン層、３３ ｎ＋型拡散層 1, 2 power control semiconductor device, 11 n + type silicon substrate, 11w wafer, 12 n type silicon layer, 13 trench, 14 non-doped layer, 15 p type silicon pillar, 16 base region, 17 source region, 18 contact region, 21 gate electrode, 22 gate insulating film, 23 source electrode, 24 drain electrode, 32 n − type silicon layer, 33 n + type diffusion layer

Claims (5)

第１導電型の半導体層に複数本のトレンチを形成する工程と、
前記トレンチの側面上に、不純物が実質的に含まれていないノンドープ層を形成する工程と、
前記トレンチの内部に第２導電型の半導体ピラーを形成する工程と、
を備えたことを特徴とする電力制御用半導体装置の製造方法。 Forming a plurality of trenches in the first conductivity type semiconductor layer;
Forming a non-doped layer substantially free of impurities on the side surface of the trench;
Forming a second conductivity type semiconductor pillar inside the trench;
A method for manufacturing a power control semiconductor device, comprising: 前記ノンドープ層は、不純物を実質的に含まない半導体材料を前記トレンチの側面上にエピタキシャル成長させることにより形成することを特徴とする請求項１記載の電力制御用半導体装置の製造方法。   2. The method of manufacturing a power control semiconductor device according to claim 1, wherein the non-doped layer is formed by epitaxially growing a semiconductor material substantially free of impurities on a side surface of the trench. 前記ノンドープ層を形成する工程の前に、前記トレンチの側面に対して第１導電型不純物を注入する工程をさらに備えたことを特徴とする請求項１または２に記載の電力制御用半導体装置の製造方法。   3. The power control semiconductor device according to claim 1, further comprising a step of injecting a first conductivity type impurity into a side surface of the trench before the step of forming the non-doped layer. Production method. 前記第１導電型不純物を注入する工程と前記ノンドープ層を形成する工程との間に、注入された前記第１導電型不純物を拡散させる工程をさらに備えたことを特徴とする請求項３記載の電力制御用半導体装置の製造方法。   4. The method according to claim 3, further comprising a step of diffusing the implanted first conductivity type impurity between the step of implanting the first conductivity type impurity and the step of forming the non-doped layer. A method of manufacturing a power control semiconductor device. 前記半導体層は第１導電型の半導体基板上に形成されたものであり、
前記半導体ピラーの上端部に第２導電型の拡散領域を形成する工程と、
前記第２導電型の拡散領域の内部に第１導電型の拡散領域を形成する工程と、
前記半導体層上に制御電極を形成する工程と、
前記半導体基板の下面上に前記半導体基板に接続される第１の主電極を形成する工程と、
前記半導体層上に前記第１導電型の拡散領域に接続される第２の主電極を形成する工程と、
をさらに備えたことを特徴とする請求項１〜４のいずれか１つに記載の電力制御用半導体装置の製造方法。 The semiconductor layer is formed on a first conductivity type semiconductor substrate,
Forming a diffusion region of a second conductivity type at the upper end of the semiconductor pillar;
Forming a first conductivity type diffusion region inside the second conductivity type diffusion region;
Forming a control electrode on the semiconductor layer;
Forming a first main electrode connected to the semiconductor substrate on a lower surface of the semiconductor substrate;
Forming a second main electrode connected to the diffusion region of the first conductivity type on the semiconductor layer;
The method for manufacturing a power control semiconductor device according to claim 1, further comprising:
JP2008272418A 2008-10-22 2008-10-22 Method of manufacturing semiconductor device for power control Pending JP2010103260A (en)

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