JP2012195394A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device allowing reduction in a termination region and processes.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: simultaneously forming first trenches in an element region in a first-conductivity-type semiconductor layer and a second trench wider than the first trenches in a termination region in the semiconductor layer; burying a second-conductivity-type semiconductor film in the first trenches and forming the second-conductivity-type semiconductor film on the inner wall of the second trench; and injecting a first-conductivity-type impurity into the second-conductivity-type semiconductor film formed on the inner wall of the second trench and forming, inside the inner wall of the second trench, a first-conductivity-type semiconductor region having a lower first-conductivity-type impurity concentration than the semiconductor layer.

Description

  Embodiments described herein relate generally to a method for manufacturing a semiconductor device.

  The on-resistance of the vertical power device greatly depends on the electric resistance of the drift layer. The impurity concentration that determines the electrical resistance of the drift layer has a limit in terms of securing a required breakdown voltage. That is, there is a trade-off relationship between element breakdown voltage and on-resistance.

  As an example of a vertical power device that solves this problem, a structure in which a drift layer is provided with a p-type pillar and an n-type pillar called a super junction structure is known. The super junction structure has the same charge amount (impurity amount) contained in the p-type pillar and the n-type pillar, thereby creating a pseudo non-doped layer and maintaining a high breakdown voltage while maintaining a relatively high doping type n-type. Low on-resistance can be achieved by flowing the main current through the pillar.

  As one method for forming a super junction structure, there is a method in which a trench is formed in an n-type semiconductor layer and a p-type semiconductor film serving as a p-type pillar is embedded in the trench.

  Further, in the power device, a withstand voltage is also required for the termination region, but on the other hand, reduction is also required for the termination region that does not contribute to the on operation. In order to reduce the termination region, a deep trench termination structure in which a trench is provided in the termination region is known.

  In manufacturing a device having a super junction structure and a deep trench termination structure, separately forming the super junction trench and the termination region trench leads to an increase in the number of processes.

JP 2007-129086 A JP 2009-4547 A

  According to the embodiment, a method of manufacturing a semiconductor device capable of reducing the termination region and reducing the number of processes is provided.

  According to the embodiment, the method of manufacturing a semiconductor device includes a first trench in the element region in the semiconductor layer of the first conductivity type having an element region and a termination region formed outside the element region, and the termination region in the first region. A step of simultaneously forming a second trench having a width wider than that of the first trench. The method for manufacturing a semiconductor device includes a step of burying a second conductivity type semiconductor film in the first trench and forming the second conductivity type semiconductor film on the inner wall of the second trench. . Further, in the method of manufacturing a semiconductor device, a first conductivity type impurity is implanted into the second conductivity type semiconductor film formed on the inner wall of the second trench, and the inner wall of the second trench is formed from the semiconductor layer. Includes a step of forming a first conductivity type semiconductor region having a low first conductivity type impurity concentration.

1 is a schematic diagram of a semiconductor device of an embodiment. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. FIG. 6 is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of the embodiment. The schematic cross section of the semiconductor device of other embodiments. Furthermore, the schematic cross section of the semiconductor device of other embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element in each drawing. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

  In the semiconductor device of the embodiment, for example, silicon is used as a semiconductor material. Alternatively, a semiconductor other than silicon (for example, a compound semiconductor such as SiC or GaN) may be used.

  FIG. 1A is a schematic cross-sectional view of the semiconductor device of the embodiment, and FIG. 1B is a schematic plan view showing a planar layout of main elements in the semiconductor device. FIG. 1A corresponds to the AA cross section in FIG.

  In the semiconductor device of the embodiment, the first main electrode 11 provided on one main surface side in the thickness direction of the semiconductor layer (or substrate) and the second main electrode 21 provided on the other main surface side. Is a vertical device in which a current path is formed in the vertical direction connecting the two.

  The semiconductor device of this embodiment includes an element region 10 and a termination region 30 formed outside the element region 10. As shown in FIG. 1B, the termination region 30 continuously surrounds the element region 10.

On the main surface of the n ^{+ -type} semiconductor layer (or substrate) 12, an n-type pillar 13a and a p-type pillar 14a are provided. The n-type pillars 13 a and the p-type pillars 14 a are periodically arranged alternately adjacent to each other in the lateral direction substantially parallel to the main surface of the n ^{+ -type} semiconductor layer 12 (pn junction), and a so-called super junction structure 20 is formed. It is composed.

  A super junction structure 20 that is a periodic arrangement structure of n-type pillars 13 a and p-type pillars 14 a is formed in the element region 10. The planar pattern of the super junction structure 20 is, for example, a stripe shape. Alternatively, the planar pattern of the super junction structure 20 may be formed in a lattice shape or a staggered shape.

  On the super junction structure 20, a p-type semiconductor layer 14b is provided. The p-type semiconductor layer 14b is in contact with the upper end of each p-type pillar 14a. A second main electrode 21 is provided on the p-type semiconductor layer 14b. The p-type semiconductor layer 14 b is in ohmic contact with the second main electrode 21. Therefore, the p-type pillar 14 a and the p-type semiconductor layer 14 b are electrically connected to the second main electrode 21.

A first main electrode 11 is provided on the back surface of the n ^{+ -type} semiconductor layer 12. The n ^{+ -type} semiconductor layer 12 is in ohmic contact with and electrically connected to the first main electrode 11.

  The p-type pillar 14a is provided in a first trench t1 formed in the element region 10 in the n-type semiconductor layer 13, as will be described later. The termination region 30 in the n-type semiconductor layer 13 is provided with a termination trench t2 as a second trench. That is, the semiconductor device of this embodiment has a termination trench structure.

The width of the termination trench t2 is larger than the width of the first trench t1. An n ^{− type} semiconductor region 15 is provided on the inner wall (side wall and bottom) of the termination trench t2. The n ^{− type} semiconductor region 15 is adjacent to the n type semiconductor layer 13 provided on the n ^{+ type} semiconductor layer 12 in the termination region 30. The side surface and the bottom surface of the n ^{− type} semiconductor region 15 are surrounded by the n type semiconductor layer 13.

n-type impurity concentration of the n-type semiconductor layer 13 and n-type pillar 13a is substantially the same, n ^- n-type impurity concentration of the type semiconductor region 15 is of n-type impurity concentration of the n-type semiconductor layer 13 and n-type pillar 13a Is also low. Further, the n type impurity concentration of the n ^{+ type} semiconductor layer 12 is higher than the n type impurity concentration of the n type semiconductor layer 13 and the n type pillar 13a.

An insulating film 16 is formed inside the n ⁻ -type semiconductor region 15 in the termination trench t2. The insulating film 16 is a silicon oxide film, for example.

  Inside the insulating film 16 in the termination trench t2, for example, non-doped polycrystalline silicon 17 (not intentionally doped with impurities) is buried as a filling material. The polycrystalline silicon 17 is in an electrically floating state.

  An insulating film 18 is provided on the polycrystalline silicon 17, the insulating film 16, and the p-type semiconductor layer 14 b in the termination region 30. The insulating film 18 is a silicon oxide film, for example. On the insulating film 18, an interlayer film 19 made of an insulating material is provided. The interlayer film 18 is, for example, a silicon oxide film.

  An insulating layer 22 made of a resin such as polyimide is provided on the interlayer film 19. The insulating layer 22 covers a part of the second main electrode 21. A connection portion of the second main electrode 21 with the outside is exposed from the insulating layer 22.

The semiconductor device of this embodiment is a vertical diode in which the second main electrode 21 is an anode electrode and the first main electrode 11 is a cathode electrode. That is, at the time of forward bias, a relatively high potential is applied to the second main electrode 21 and a low potential is applied to the first main electrode 11, and the p-type semiconductor layer 14b, the super junction structure 20, and the n-type below the p-type semiconductor layer 14b. A main current flows in the vertical direction between the second main electrode 21 and the first main electrode 11 through the semiconductor layer 13 and the n ^{+ -type} semiconductor layer 12.

  At the time of reverse bias, a relatively low potential is applied to the second main electrode 21 and a high potential is applied to the first main electrode 11. At this time, the depletion layer extends in the lateral direction from the pn junction of the n-type pillar 13a and the p-type pillar 14a in the super junction structure 20 of the element region 10, and high breakdown voltage can be maintained.

Further, the depletion layer extends from the pn junction at the interface between the n-type semiconductor layer 13 and the n ⁻ -type semiconductor region 15 in the termination region 30 and the p-type semiconductor layer 14b. Thereby, a high breakdown voltage can be obtained also in the termination region 30.

In the present embodiment, the n ^{− type} semiconductor region 15 having an n type impurity concentration lower than that of the n type semiconductor layer 13 is provided on the side wall and the bottom of the termination trench t 2 in the termination region 30. For this reason, as shown by a two-dot chain line in FIG. 1A, the depletion layer becomes easier to extend in the depth direction, the electric field at the interface between the n ⁻ -type semiconductor region 15 and the insulating film 16 is relaxed, and more. The breakdown voltage can be improved.

  The end surface 40, which is a cut surface at the time of cutting from the wafer state, is crushed due to the influence at the time of cutting, and the leak current tends to increase. In the present embodiment, a termination trench t2 is formed in the termination region 30, and an insulating film 16 and non-doped polycrystalline silicon 17 are provided therein. With such a termination trench structure, the extension of the depletion layer can be stopped before the depletion layer reaches the fracture portion of the termination surface 40. As a result, current leakage through the crushing portion of the end face 40 can be avoided. Moreover, high reliability is obtained by covering and protecting the inner wall of the termination trench t2 with the insulating film 16.

  As a comparative example, in a structure in which a termination region is formed of a high resistance layer, a termination length of, for example, 200 (μm) is required to prevent the depletion layer from reaching the termination surface. On the other hand, in the termination trench structure as in this embodiment, the termination length is about 80 to 120 (μm), for example. For this reason, size reduction of a device (chip) can be achieved.

  Next, with reference to FIGS. 2A to 3D, a method for manufacturing the semiconductor device of the embodiment will be described. In addition, the cross-sectional part in process drawing respond | corresponds to the AA cross section in FIG.

FIG. 2A shows a state in which the n-type semiconductor layer 13 is epitaxially grown on the main surface of the substrate (n ^{+ -type} semiconductor layer) 12. In FIG. 2B and subsequent cross-sectional views, the substrate (n ^{+ -type} semiconductor layer) 12 is not shown.

  Then, for example, a silicon oxide film or the like is formed on the surface of the n-type semiconductor layer 13, and then selectively etched to form the first opening 31a and the second opening 31b, and the mask 31 is formed. A plurality of first openings 31 a are formed in the element region 10. The second opening 31 b has a larger opening width than the first opening 31 a and is formed in the termination region 30.

  Next, the n-type semiconductor layer 13 is etched using the mask 31 by, for example, RIE (Reactive Ion Etching). Thereby, as shown in FIG. 2B, a first trench t1 and a termination trench t2 which is a second trench are formed simultaneously. The first trench t1 is formed under the first opening 31a. The second trench t2 is formed under the second opening 31b. FIG. 2C corresponds to a top view after the trenches t1 and t2 are formed.

  A plurality of first trenches t1 are formed in the element region 10, for example, in a stripe shape. The termination trench t2 is formed so as to continuously surround the element region 10 as shown in FIG. The width b of the termination trench t2 is larger than the width a of the first trench t1. In the n-type semiconductor layer 13 in the element region 10, a portion adjacent to the first trench t1 becomes an n-type pillar 13a.

  Next, a p-type semiconductor film is formed in the first trench t1 and the termination trench t2 by, for example, an epitaxial growth method. The p-type semiconductor film fills the inside of the first trench t1, and becomes a p-type pillar 14a as shown in FIG. The termination trench t2 is wider than the first trench t1. Therefore, the p-type semiconductor film 14c in the termination trench t2 is formed along the inner wall (side wall and bottom wall) of the termination trench t2, and a cavity remains inside the p-type semiconductor film 14c in the termination trench t2. The p-type pillar 14a and the p-type semiconductor film 14c are formed simultaneously.

  Next, as shown in FIG. 3B, after covering the surface other than the termination trench t2 with a mask 32, the n-type is formed by ion implantation on the p-type semiconductor film 14c formed on the inner wall of the termination trench t2. Impurities (for example, phosphorus) are implanted.

Ion implantation is performed in a direction inclined with respect to the main surface of the substrate (n ^{+ -type} semiconductor layer) 12. As a result, an n-type impurity is implanted into the p-type semiconductor film 14c formed on the sidewall of the termination trench t2. Furthermore, since the termination trench t2 is wide, an n-type impurity is also implanted into the p-type semiconductor film 14c on the bottom surface of the termination trench t2.

After the ion implantation, annealing is performed to diffuse the implanted n-type impurity. As a result, the p-type semiconductor film 14c is inverted to the n-type, and as shown in FIG. 3B, the n ⁻ -type semiconductor region 15 is formed on the inner wall of the termination trench t2. n ^- so that the n-type impurity concentration of the type semiconductor region 15 is lower than the n-type impurity concentration of the n-type semiconductor layer 13, the dose of n-type impurity is set.

Next, as shown in FIG. 3C, the insulating film 16 is formed inside the n ⁻ -type semiconductor region 15 in the termination trench t2. The insulating film 16 is a silicon oxide film formed by, for example, a thermal oxidation method. Since the termination trench t2 is wide, the interior of the termination trench t2 is not filled with the insulating film (oxide film) 16 formed by the thermal oxidation method.

  Next, as shown in FIG. 3D, non-doped polycrystalline silicon 17 is embedded as an embedded material inside the insulating film 16 in the termination trench t2. The cavity remaining in the termination trench t2 is filled with polycrystalline silicon 17. The polycrystalline silicon 17 is excellent in embeddability and can be easily embedded in the termination trench t2 without applying stress or strain to the periphery.

  Next, after removing the polycrystalline silicon 17 remaining on the surface other than the termination trench t2 by, for example, a CMP (Chemical Mechanical Polishing) method, the p shown in FIG. A shaped semiconductor layer 14b is formed. For example, a p-type semiconductor layer 14b is formed by forming a thermal oxide film, ion-implanting p-type impurities (for example, boron) into the surface of the n-type semiconductor layer 13, and then diffusing by annealing.

  Thereafter, an electrode, an insulating film on the termination trench structure, and the like are formed.

  According to this embodiment, when manufacturing a semiconductor device having a super junction structure and a termination trench structure, the first trench t1 in the element region 10 and the termination trench t2 in the termination region 30 are formed simultaneously. For this reason, the number of processes can be reduced as compared with the case where the first trench t1 and the termination trench t2 are formed separately.

Further, after forming the trenches t1 and t2, a p-type semiconductor film is formed in the trenches t1 and t2. The p-type semiconductor film in the trench t1 is left as it is to become the p-type pillar 14a. The p-type semiconductor film 14c formed in the termination trench t2 is inverted to the n-type by implanting an n-type impurity. Further, the film inverted to the n-type becomes an n ⁻ -type semiconductor region 15 having an n-type impurity concentration lower than that of the n-type pillar 13 a and the n-type semiconductor layer 13 in the termination region 30. For this reason, as described above, the depletion layer easily extends in the depth direction in the termination region 30 at the time of reverse bias, and a high breakdown voltage is obtained.

  In the process described above, after the p-type semiconductor layer 14b is formed, the polycrystalline silicon 17 is removed from the termination trench t2, and the insulating film in the termination trench t2 is removed as shown in FIGS. An interlayer film (for example, a silicon oxide film) 19 and an insulating layer (for example, a resin) 22 may be embedded inside the 16 as an embedded material.

  The interlayer film 19 and the insulating layer 22 may be completely embedded in the termination trench t2 as shown in FIG. 4B, or inside the insulating layer 22 as shown in FIG. 4A. It does not matter if a cavity remains.

1A shows a structure in which the bottom of the p-type pillar 14a and the bottom of the termination trench t2 are located in the n-type semiconductor layer 13 and do not reach the n ^{+ -type} semiconductor layer 12. FIG. However, the structure is not limited to this, and the p-type pillar 14a and the termination trench t2 may reach the n ^{+ -type} semiconductor layer 12 as shown in FIG.
4A, 4B, and FIG. 5B described below, even if the p-type pillar 14a and the termination trench t2 reach the n ^{+ -type} semiconductor layer 12. Good.

  Next, FIG. 5B shows a semiconductor device according to another embodiment. A planar MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is formed in the element region 10 of the semiconductor device.

Also in the present embodiment, a super junction structure 20 that is a periodic arrangement structure of n-type pillars 13 a and p-type pillars 14 a is provided on the main surface of the n ^{+ -type} semiconductor layer (or substrate) 12 in the element region 10. It has been.

A p-type base layer 14d is provided on the p-type pillar 14a. On the surface of the p-type base layer 14d, an n ^{+ -type} source region 41 is selectively provided. The source region 41 has an n-type impurity concentration higher than that of the n-type pillar 13a.

  A gate insulating film 42 is provided on a portion from the n-type pillar 13a through the p-type base layer 14d to a part of the source region 41, and a gate electrode 43 is provided thereon.

  A second main electrode 21 is provided on the surface of the source region 41, and the source region 41 is in ohmic contact with and electrically connected to the second main electrode 21. An interlayer insulating film 44 is provided between the gate electrode 43 and the second main electrode 21.

  The structure of the termination region 30 is the same as that of FIG. 1A, FIG. 4A, or FIG.

  In the semiconductor device of the present embodiment, a desired gate potential is applied to the gate electrode 43 while a relatively high potential is applied to the first main electrode 11 and a low potential is applied to the second main electrode 21. Then, an inversion layer (n channel) is formed in the vicinity of the interface with the gate insulating film 42 in the p-type base layer 14d. For example, a positive potential is applied to the gate electrode 43 with respect to the potential of the second main electrode 21 to which a ground potential or a negative potential is applied. A positive potential higher than the gate potential is applied to the first main electrode 11.

As a result, a current flows between the second main electrode 21 and the first main electrode 11 via the source region 41, the n-channel, the n-type pillar 13a, and the n ^{+ -type} semiconductor layer 12 to be turned on.

When the gate is turned off, a depletion layer extends laterally from the pn junction between the n-type pillar 13a and the p-type pillar 14a in the super junction structure 20 in the element region 10, and a high breakdown voltage can be maintained. Further, the depletion layer extends from the pn junction at the interface between the n-type semiconductor layer 13 and the n ⁻ -type semiconductor region 15 in the termination region 30 and the outermost p-type base layer 14 e. Thereby, a high breakdown voltage can be obtained also in the termination region 30. The outermost p-type base layer 14e is formed simultaneously with the p-type base layer 14d.

Also in this embodiment, the n ⁻ -type semiconductor region 15 having an n-type impurity concentration lower than that of the n-type semiconductor layer 13 is provided on the side wall and the bottom of the termination trench t 2 in the termination region 30. For this reason, the depletion layer becomes easier to extend in the depth direction, the electric field at the interface between the n ⁻ -type semiconductor region 15 and the insulating film 16 is relaxed, and the breakdown voltage can be further improved.

  Further, the termination trench structure can stop the extension of the depletion layer before the depletion layer reaches the fracture portion of the termination surface 40. As a result, current leakage through the crushing portion of the end face 40 can be avoided. Moreover, high reliability is obtained by covering and protecting the inner wall of the termination trench t2 with the insulating film 16.

  Also in this embodiment, when manufacturing a semiconductor device having a super junction structure and a termination trench structure, the first trench t1 in the element region 10 and the termination trench t2 in the termination region 30 are formed simultaneously. For this reason, the number of processes can be reduced as compared with the case where the first trench t1 and the termination trench t2 are formed separately.

Further, after forming the trenches t1 and t2, a p-type semiconductor film is formed in the trenches t1 and t2. The p-type semiconductor film in the trench t1 is left as it is to become the p-type pillar 14a. The p-type semiconductor film 14c formed in the termination trench t2 is inverted to the n-type by implanting an n-type impurity. Further, the film inverted to the n-type becomes an n ⁻ -type semiconductor region 15 having an n-type impurity concentration lower than that of the n-type pillar 13 a and the n-type semiconductor layer 13 in the termination region 30. For this reason, the depletion layer easily extends in the depth direction in the termination region 30 when the gate is turned off, and a high breakdown voltage is obtained.

In FIG. 5B, the planar MOSFET is taken as an example, but a trench gate MOSFET or an IGBT (Insulated Gate Bipolar Transistor) may be used. In the case of IGBT, the n ^{+ type} semiconductor layer (drain layer) 12 may be replaced with a p ^{+ type} semiconductor layer (collector layer).

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10 ... device region 11 ... first main electrode, 12 ... ^{n +} -type semiconductor layer, 13 ... n-type semiconductor layer, 13a ... n-type pillar, 14a ... p-type pillar, 15 ... n ^- type semiconductor region, 16 ... Insulating film, 17 ... polycrystalline silicon, 21 ... second main electrode, 30 ... termination region, 40 ... termination surface, t1 ... first trench, t2 ... termination trench

Claims (5)

In the first conductivity type semiconductor layer having an element region and a termination region formed outside the element region, a first trench is formed in the element region, and a second trench having a width wider than that of the first trench in the termination region. Forming simultaneously,
Burying a second conductivity type semiconductor film in the first trench and forming the second conductivity type semiconductor film on an inner wall of the second trench;
A first conductivity type impurity is implanted into the second conductivity type semiconductor film formed on the inner wall of the second trench, and the first conductivity type impurity concentration is lower than the semiconductor layer on the inner wall of the second trench. Forming a first conductivity type semiconductor region;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming an insulating film inside the first conductivity type semiconductor region in the second trench.   3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of forming a filling material inside the insulating film in the second trench.   4. The method of manufacturing a semiconductor device according to claim 3, wherein non-doped silicon is embedded as the embedded material.   4. The method of manufacturing a semiconductor device according to claim 3, wherein an insulator is embedded as the embedded material.

Images