JP2010087483A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with low operating voltage over a wide current density range. <P>SOLUTION: The semiconductor device 10 includes: a first conductivity-type semiconductor substrate 1; a first conductivity-type semiconductor layer 2 that is formed on the semiconductor substrate 1 with a lower doping concentration than that of the semiconductor substrate 1; first second-conductivity-type semiconductor regions 3 that are formed side by side at a predetermined interval on the outer surface of the semiconductor layer 2; a first electrode 5 that is formed on the semiconductor layer 2 and the first semiconductor regions 3 to form a Schottky contact with the semiconductor layer 2 and form an Ohmic-contact with the first semiconductor regions 3; and a second electrode 6 that is formed on the backside of the semiconductor substrate 1, wherein the width Wp (μm) of the first semiconductor region 3 and doping concentration N (cm<SP>-3</SP>) of the semiconductor layer 2 have a relationship of Wp>-72×In(N)+2,685. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a Schottky barrier diode and a pin diode are configured in parallel, and more particularly to a semiconductor device using a wide gap semiconductor element such as silicon carbide (SiC).

  In wide-gap semiconductors such as silicon carbide (SiC) semiconductors, Schottky barrier diodes, pin diodes, or JBS (Junction Barrier Schottky) diodes in which both are arranged in parallel are known (see, for example, Patent Document 1). . For example, Patent Document 1 aims to reduce the reverse leakage current as compared with a Schottky barrier diode, and in the forward characteristics, a configuration for lowering the operating voltage of the element at a relatively low current density in which current flows through the Schottky portion. A JBS diode is disclosed.

Japanese Patent Laid-Open No. 10-321879

  However, in the above-described semiconductor device using a semiconductor element such as a diode, the operating voltage of the element cannot be lowered or a large current cannot be passed through the element in a current density region having a particularly high forward characteristic. was there.

  The above-described problem will be described in detail below. In a general JBS diode, the element region width of the pin diode portion is approximately 4 μm. However, with this element region width, even if a voltage corresponding to the band gap of the semiconductor material is applied to the pin diode portion, the potential of the n-type drift layer does not rise sufficiently, so that the current in the pin diode portion does not rise. . Therefore, as in the case of a low current density even at a high current density, the device operates only by a current flowing through the Schottky barrier diode portion, and the operating voltage of the element in a large current region cannot be lowered. Alternatively, a large current cannot flow through the element.

  Therefore, the present invention has been made to solve such a problem, and an object of the present invention is to obtain a semiconductor device having a small operating voltage in a wide current density range.

The semiconductor device according to the present invention includes a first conductivity type semiconductor substrate, a first conductivity type semiconductor layer formed on the semiconductor substrate at a lower doping concentration than the semiconductor substrate, and a surface layer of the semiconductor layer at a predetermined interval. A first semiconductor region of a second conductivity type juxtaposed and formed on the semiconductor layer and the first semiconductor region, and in contact with the semiconductor layer, ohmic with the first semiconductor region A first electrode in contact with the second electrode formed on the back surface of the semiconductor substrate; a width Wp (μm) of the first semiconductor region; and a doping concentration N (cm ⁻³ ) of the semiconductor layer. ) Have a relationship of Wp> −72 × ln (N) +2585.

A semiconductor device according to the present invention includes a first conductive type semiconductor substrate, a first conductive type semiconductor layer formed on the semiconductor substrate at a lower doping concentration than the semiconductor substrate, and at least a peripheral portion of the semiconductor layer. A first semiconductor region of a second conductivity type formed in a surface layer, and formed on the semiconductor layer and the first semiconductor region; Schottky contact with the semiconductor layer; ohmic contact with the first semiconductor region A termination formed on a surface layer of a peripheral portion of the semiconductor layer as a termination structure in the first semiconductor region, and a second electrode formed on a back surface of the semiconductor substrate. The width Wpt (μm) of the partial semiconductor region and the doping concentration N (cm ⁻³ ) of the semiconductor layer have a relationship of Wpt> −72 × ln (N) +2585.

  According to the semiconductor device of the present invention, the potential of the n-type drift layer is sufficiently increased when a voltage corresponding to the forbidden band width of the semiconductor material is applied by sufficiently increasing the element region width of the pin diode portion. As a result, the current of the pin diode portion rises. Therefore, in the forward characteristics, it is possible to realize a diode configuration mainly composed of a Schottky barrier diode part at a relatively low current density and a current component flowing through a pin diode part at a high current density, and a wide current density range. Thus, a semiconductor device with a lower operating voltage can be realized.

  According to the semiconductor device of the present invention, the potential of the n-type drift layer when a voltage corresponding to the forbidden band width of the semiconductor material is applied by sufficiently widening the element region width of the pin diode portion at the terminal portion. Is sufficiently increased, and the current of the pin diode portion composed of the termination semiconductor region and the n-type drift layer rises. As a result, in the forward characteristics, the diode mainly has a current component that flows through the Schottky barrier diode portion at a relatively low current density and a current component that flows through the pin diode portion formed of the termination semiconductor region at a high current density. A configuration can be realized. Therefore, a semiconductor device with a smaller operating voltage can be realized in a wide current density range. It is also effective for high-speed switching.

It is sectional drawing which shows the structure of the semiconductor device 10 using the silicon carbide semiconductor element in Embodiment 1 of this invention. It is a figure which shows the example of the current-voltage characteristic of the semiconductor device in Embodiment 1 of this invention. It is a figure which shows the change by the voltage application of the band structure of the semiconductor device in Embodiment 1 of this invention. The semiconductor device according to the first embodiment of the present invention calculated the dependence on the element region width Wp (μm) and the drift layer doping concentration N (cm ⁻³ ) when the current rises without bending when a voltage corresponding to the forbidden band width is applied. It is a figure which shows a result. It is sectional drawing which shows the structure of the semiconductor device 20 using the silicon carbide semiconductor element in Embodiment 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device 30 using the silicon carbide semiconductor element in Embodiment 3 of this invention. It is sectional drawing which shows the structure of the semiconductor device 40 using the silicon carbide semiconductor element in Embodiment 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device 41 using the silicon carbide semiconductor element in the modification 1 of Embodiment 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device 42 using the silicon carbide semiconductor element in the modification 2 of Embodiment 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device 43 using the silicon carbide semiconductor element in the modification 3 of Embodiment 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device 50 using the silicon carbide semiconductor element in Embodiment 5 of this invention. It is sectional drawing which shows the structure of the semiconductor device 60 using the silicon carbide semiconductor element in Embodiment 6 of this invention. It is sectional drawing which shows the structure of the semiconductor device 70 using the silicon carbide semiconductor element in Embodiment 7 of this invention. It is sectional drawing which shows the structure of the semiconductor device 71 using the silicon carbide semiconductor element in the modification of Embodiment 7 of this invention.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 10 using a silicon carbide semiconductor element in the first embodiment of the present invention. The semiconductor device 10 includes a low-resistance n-type SiC substrate 1, an n-type SiC drift layer (semiconductor layer) 2 for maintaining a withstand voltage formed on the n-type SiC substrate 1, and an n-type SiC drift layer 2. P-type SiC regions (first semiconductor regions) 3 and 4 juxtaposed at a predetermined interval on the surface layer, and anode electrodes (first electrodes) formed on n-type SiC drift layer 2 and p-type SiC regions 3 and 4 1 electrode) 5 and a cathode electrode (second electrode) 6 formed on the back surface of the n-type SiC substrate 1. The p-type SiC regions 3 and 4 include an internal p-type SiC region 3 and a termination p-type SiC region 4. The n-type SiC substrate 1, the n-type SiC drift layer 2, the p-type SiC regions 3 and 4, the anode electrode 5, and the cathode electrode 6 are JBS diode elements (hereinafter sometimes referred to as “JBS diodes” or “elements”). Constitute.

N-type SiC drift layer 2 is formed on n-type SiC substrate 1 by epitaxial growth at a lower doping concentration than n-type SiC substrate 1. The n-type SiC drift layer 2 has a thickness of about 3 to 150 μm and a doping concentration of about 0.5 to 15 × 10 ¹⁵ / cm ³ .

Internal p-type SiC region 3 (3a, 3b, 3c, 3d...) Is selectively formed in n-type SiC drift layer 2 by an ion implantation process and an activation heat treatment process. The internal p-type SiC region 3 has a film thickness of about 0.5 to 2 μm and a doping concentration of about 1 to 100 × 10 ¹⁷ / cm ³ . Moreover, the termination | terminus part p-type SiC area | region 4 (4a, 4b ...) is formed in the peripheral part of an element as a termination | terminus structure. The internal p-type SiC region 3 is formed inside except for the peripheral portion of the element. The film thickness and doping concentration of the termination p-type SiC region 4 may be the same as or different from those of the internal p-type SiC region 3, and are regions having several concentrations instead of a single concentration. It is good also as a combination.

The anode electrode 5 is in Schottky contact with the n-type SiC drift layer 2 and functions as an ohmic electrode with respect to the internal p-type SiC region 3. In order to function as an ohmic electrode, the contact resistance value may be 10 ⁻³ Ωcm ² or less, and the contact resistance value of the anode electrode 5 with the internal p-type SiC region 3 may be 10 ⁻³ Ωcm ² or less. The increase in the on-voltage due to the influence of the contact portion when current flows through the pin diode portion can be reduced. The contact resistance value of the anode electrode 5 with the internal p-type SiC region 3 is more desirably 10 ⁻⁴ Ωcm ² or less, and if it is 10 ⁻⁴ Ωcm ² or less, an increase in on-voltage due to the influence of the contact portion is almost ignored. it can. Therefore, the anode electrode 5 is not limited to an electrode having a single metal layer structure, and may be made of different materials for the contact portion with the n-type SiC drift layer 2 and the contact portion with the internal p-type SiC region 3. . For termination p-type SiC region 4, anode electrode 5 may be a Schottky contact or an ohmic electrode, and is the same material as the contact portion with n-type SiC drift layer 2 or the contact portion with internal p-type SiC region 3. Or different materials may be used.

  The length 7 where the anode electrode 5 is in contact with the internal p-type SiC region 3 is the pin diode region width Wp, and the length 8 where the anode electrode 5 is in contact with the n-type SiC drift layer 2 (n-type SiC drift layer 2 (Width between two p-type SiC regions 3 facing each other) is defined as a Schottky barrier diode region width Ws. The value of the region width depends on the doping concentration of the n-type SiC drift layer 2, which will be described below.

  FIG. 1 is a cross-sectional view of the semiconductor device 10 and may have a comb-shaped element structure in which one period of the cross-section (corresponding to a region sandwiched between two alternate long and short dash lines) extends in one direction. An element structure in which one period is a polygon may be used. In the cross-sectional view shown in FIG. 1, it seems that a plurality of internal p-type SiC regions 3 and termination p-type SiC regions 4 are provided. When viewed from one side in the thickness direction of the SiC substrate 1, an element structure in which the basic structure is repeated in a comb shape or a polygonal shape is obtained. Therefore, three-dimensionally, at least the terminal p-type SiC region 4 is one, and in many cases, it is also connected to the internal p-type SiC region 3 to form one p-type SiC region.

Next, FIG. 2 shows the device region width (here, the pin diode region width Wp and the Schottky) for the forward current / voltage characteristics when the doping concentration of the n-type SiC drift layer 2 is 2 × 10 ¹⁵ / cm ^3. It is a figure which shows the result of having calculated the change by a device simulation by making the barrier diode area | region width Ws the same. FIG. 2 also shows a case of a pin diode in which the internal p-type SiC region 3 is not selective but formed in the entire element region, and a Schottky barrier diode in which the internal p-type SiC region 3 is not formed at all in the element region. Show.

  As shown in FIG. 2, in the case of a Schottky barrier diode, the current increases almost in proportion to the voltage application. In the case of a pin diode, the current rises when a voltage corresponding to the forbidden bandwidth is applied.

  On the other hand, in the case of a JBS diode, when the element region width Wp is 150 μm, there is no bending (kink) in the current / voltage characteristics, and the current in the pin diode portion rises when a voltage equivalent to the forbidden band width is applied. On the other hand, when the element region width Wp is 100 μm, bending is observed, and when the element region width Wp is 50 μm, the current does not rise unless a voltage larger than the forbidden band width is applied.

  FIG. 3 is a diagram illustrating a change in the band structure of the semiconductor device 10 according to the present embodiment due to voltage application. With reference to FIG. 3, the current / voltage characteristics of the semiconductor device 10 shown in FIG. 2 will be described. In each figure, the left end is the anode electrode 5 side, and the right end is the cathode electrode 6 side. FIG. 3A is a diagram showing a case of a pin diode in which the internal p-type SiC region 3 is not selective but formed in the entire device region. FIG. 3B shows a Schottky barrier diode in which the internal p-type SiC region 3 is not formed at all in the element region. On the other hand, FIGS. 3C and 3D show the case of the JBC diode structure. FIG. 3C shows the case where the element region width Wp is 50 μm, and FIG. It is the figure which showed the case where is 150 micrometers.

  In the case of the single pin diode shown in FIG. 3A and the case of the single Schottky barrier diode shown in FIG. 3B, when the forward voltage indicated by the bold line is applied, the voltage indicated by the thin line is applied. Compared with the case of 0V, the band is lifted, electrons can flow to the left side of the figure, and forward current flows from the anode to the cathode.

  In the case of the JBS structure shown in FIG. 3C, the band is sufficiently lifted when a forward voltage is applied in the Schottky barrier diode part (hereinafter sometimes referred to as “Schottky part”), but the band is sufficiently lifted in the pin diode part. Therefore, it can be seen that the current is mainly Schottky current. On the other hand, in the case of the JBS structure shown in FIG. 3D, the band of the pin diode part is sufficiently lifted when the forward voltage is applied, and the current flows not only in the Schottky part but also in the pin diode part. It can be seen that the current rises compared to FIG.

Thus, in order for the current in the pin diode part to rise without bending (kink) in the current / voltage characteristics, that is, to cause the current in the pin diode part to rise upon application of a voltage equivalent to the forbidden band width, A large element region width Wp is required. FIG. 4 is a diagram illustrating a result of calculating the relationship between the element region width Wp (μm) and the doping concentration N (cm ⁻³ ) of the n-type SiC drift layer 2 from device simulation when the current rises without bending. The straight line in the figure is represented by the following formula (1). That is, by setting the element region width Wp according to the doping concentration of the n-type SiC drift layer 2 so that the region width is larger than the following formula (1), the operating voltage in the high current density region can be lowered. It becomes possible.

Therefore, when the doping concentration of the n-type SiC drift layer 2 is 4 × 10 ¹⁵ / cm ³ , the pin diode portion element region width Wp is 100 μm, 2 × 10 ¹⁵ / cm ³ is 150 μm, and 1 × 10 ¹⁵ / cm ³ is 200 μm. By doing so, it becomes possible to lower the operating voltage in the high current density region, and a larger current can flow.

  The element region width Wp may be a value larger than the value shown in the expression (1). On the other hand, the increase in the element region width Wp is a low voltage region where the current in the Schottky portion is mainly used. However, the differential resistance of the current / voltage characteristic is slightly increased. Therefore, when the operation at a low voltage is emphasized to some extent, it is not a good idea to make the value too large, but it is about 1.5 times the value shown by the equation (1), that is, the range up to the following equation (2). It is preferable to keep it at a minimum.

  As described above, according to the semiconductor device 10 in the present embodiment, the pin diode region width Wp, which is the width of the pin diode portion composed of the n-type SiC drift layer 2 and the selectively provided internal p-type SiC region 3, is obtained. By making it sufficiently large, when a voltage corresponding to the forbidden band width of the semiconductor material is applied, the potential of the n-type SiC drift layer 2 is sufficiently increased, and the current of the pin diode portion is increased. As a result, in the forward characteristics, it is possible to realize a diode configuration in which the Schottky barrier diode part is mainly used at a relatively low current density and the current component flowing through the pin diode part is high at a high current density. In the range, a semiconductor device with a smaller operating voltage can be realized.

  In addition, since the semiconductor device 10 according to the present embodiment enables the operating voltage to be lowered in a wide current density range as described above, it also has an effect of reducing energy consumption.

<Embodiment 2>
FIG. 5 is a cross sectional view showing a configuration of semiconductor device 20 using the silicon carbide semiconductor element in the second embodiment of the present invention. Since the semiconductor device 20 of the present embodiment is similar in configuration to the semiconductor device 10 of the first embodiment, only different parts will be described, and corresponding parts will be denoted by the same reference numerals and common. Description is omitted. The semiconductor device 20 of the present embodiment is different from the semiconductor device 10 of the first embodiment in that the semiconductor device 20 pins the Schottky barrier diode region width Ws where the n-type SiC drift layer 2 is in contact with the anode electrode 5. The configuration is such that the operating voltage at a relatively low current density can be lowered by making it larger than the diode region width Wp. Similarly to the first embodiment, the pin diode region width Wp is set to a region width larger than the expression (1) with respect to the doping concentration of the n-type SiC drift layer 2, thereby lowering the operating voltage at a high current density. It is possible.

  From the above, according to the semiconductor device 20 in the present embodiment, the Schottky barrier diode width Ws is made larger than the pin diode region width Wp, and the Schottky barrier diode is formed by the portion where the internal p-type SiC region 3 is not formed. By increasing the area of the portion, the on-voltage in a low voltage region where the current of the pin diode portion does not rise can be reduced, and a semiconductor device with a smaller operating voltage can be realized in a wide current density range. .

<Embodiment 3>
FIG. 6 is a cross sectional view showing a configuration of semiconductor device 30 using the silicon carbide semiconductor element in the third embodiment of the present invention. Since the semiconductor device 30 of the present embodiment is similar in configuration to the semiconductor device 10 of the first embodiment, only different parts will be described, and corresponding parts will be denoted by the same reference numerals and common. Description is omitted. The semiconductor device 30 of the present embodiment is different from that of the first embodiment in that the semiconductor device 30 has an n-type SiC in a Schottky region that is a region of the n-type SiC drift layer 2 sandwiched between the internal p-type SiC regions 3. By further providing n-type SiC region 9 (9a, 9b, 9c, 9d, 9e,...) Formed at a higher doping concentration than drift layer 2, it is possible to lower the operating voltage at a relatively low current density. This is the point of the configuration. N-type SiC region 9 corresponds to a second semiconductor region.

  Similarly to the first embodiment, the pin diode region width Wp is set to a region width larger than the expression (1) with respect to the doping concentration of the n-type SiC drift layer 2, thereby lowering the operating voltage at a high current density. This is possible and does not depend on the doping concentration of the n-type SiC region 9 sandwiched between the internal p-type SiC regions 3. In this configuration, depending on the doping concentration of the n-type SiC region 9, the operating voltage at a relatively low current density can be lowered even if the Schottky barrier diode region width Ws is smaller than the pin diode region width Wp. The configuration can be as follows.

  As described above, according to the semiconductor device 30 in the present embodiment, by increasing the doping concentration on the surface of the n-type SiC drift layer 2 of the Schottky barrier diode portion constituted by the portion where the internal p-type SiC region 3 is not formed, The on-voltage in a low voltage region where the current of the pin diode portion does not rise can be reduced, and a semiconductor device with a smaller operating voltage can be realized in a wide current density range. Further, since the Schottky barrier diode region width Ws can be set to a value smaller than the pin diode region width Wp, there is an effect of downsizing the semiconductor device.

<Embodiment 4>
FIG. 7 is a cross sectional view showing a configuration of semiconductor device 40 using the silicon carbide semiconductor element in the fourth embodiment of the present invention. Since the semiconductor device 40 of the present embodiment is similar in configuration to the semiconductor device 10 of the first embodiment, only different parts will be described, and the corresponding parts are denoted by the same reference numerals and are common. Description is omitted.

  The semiconductor device 40 according to the present embodiment is different from the semiconductor device 10 according to the first embodiment in that in the semiconductor device 40, all portions of the internal p-type SiC region 3 (3a, 3b, 3e...) The element region width Wp does not satisfy the relationship in which the region width is larger than the value of the expression (1), but only a part satisfies the relationship and the other portions do not satisfy the relationship.

  For example, in the example shown in FIG. 7, only the portions indicated by reference marks 3 a and 3 b in the internal p-type SiC region 3 satisfy the above relationship. Other reference numerals 3e, 3f, 3g, 3h, 3i, 3j, 3k, 3l, 3m, and 3n do not satisfy the above relationship, and are smaller as indicated by Wpn as the element region width. It has an element region width, specifically, a region width equal to or smaller than the value of equation (1). Hereinafter, the internal p-type SiC region 3 that satisfies the above relationship, that is, a portion having a region width larger than the value of the formula (1) is referred to as a “wide internal p-type region”. The portion of the internal p-type SiC region 3 having a region width equal to or less than the value of) is called a “narrow internal p-type region”. In the semiconductor device 40 shown in FIG. 7, the internal p-type SiC region 3 includes two wide internal p-type regions 3a and 3b and ten narrow internal p-type regions 3e to 3n.

  Pin diode region width (hereinafter referred to as “wide pin region width”) Wp of wide internal p-type regions 3a and 3b corresponds to pin diode region width Wp of internal p-type SiC region 3 in the first embodiment described above, and anode The length of the portion where the electrode 5 is in contact with the wide internal p-type regions 3a and 3b is 7. The length 11 of the portion where the anode electrode 5 is in contact with the narrow internal p-type regions 3e to 3n is the pin diode region width of the narrow internal p-type regions 3e to 3n (hereinafter referred to as “narrow pin region width”). Let it be Wpn.

As described above, in the present embodiment, the width of internal p-type SiC region 3 has two or more values. Among them, the width of at least one internal p-type SiC region 3, specifically, the width Wp (μm) of the wide internal p-type region and the doping concentration N (cm ⁻³ ) of the n-type SiC drift layer 2 are expressed as Wp> It has a relationship of −72 × ln (N) +2585. The width of at least one other internal p-type SiC region 3, specifically, the width Wpn (μm) of the narrow internal p-type region and the doping concentration N (cm ⁻³ ) of the n-type SiC drift layer 2 are Wpn ≦ −72 × ln (N) +2585.

  Of the Schottky barrier diode region width which is the width of the Schottky barrier diode portion, the width between the two wide internal p-type regions 3a and 3b facing each other in the n-type SiC drift layer 2 is defined as a wide Schottky region width Ws, and n-type SiC A width between the two narrow internal p-type regions 3e to 3n facing each other in the drift layer 2 is defined as a narrow Schottky region width Wsn. Wide Schottky region width Ws corresponds to Schottky barrier diode region width Ws in the first embodiment, and anode electrode 5 is an n-type SiC drift layer between two adjacent wide internal p-type regions 3a and 3b. The length of the portion in contact with 2 is 8. The narrow Schottky region width Wsn is the length 12 of the portion where the anode electrode 5 is in contact with the n-type SiC drift layer 2 between two adjacent narrow internal p-type regions 3e to 3n. In the present embodiment, the narrow Schottky region width Wsn is selected to be smaller than the wide Schottky region width Ws.

If the doping concentration of the n-type SiC drift layer 2 corresponding to FIG. 2 shown in the first embodiment is 2 × 10 ¹⁵ / cm ³ , the current / voltage is obtained when the element region width Wp is 150 μm. There is no bending (kink) in the characteristics, and the current in the pin diode portion rises when a voltage equal to or greater than the forbidden bandwidth is applied. On the other hand, when the element region width Wp is 50 μm, bending is observed, and current does not rise unless a voltage larger than the forbidden band width is applied. However, in a voltage smaller than the forbidden band width, the current value for the same voltage is It can be seen that the resistance is large and low.

  Therefore, in the present embodiment, the element region width Wp of all the portions of the internal p-type SiC region 3 is not set larger than the value of the equation (1), but the element region width Wp is set only for a part of the equation (1). It is set larger than the value of.

  In the current / voltage characteristics, at a voltage up to the vicinity of the forbidden band width, a current flows through a Schottky barrier diode portion between two opposing internal p-type SiC regions 3 having an element region width expressed as Ws or Wsn. At this time, in the present embodiment, as described above, the element region width Wp is set to be larger than the value of the expression (1) only in a part of the internal p-type SiC regions 3, Since not only the wide internal p-type regions 3a and 3b having a large region width Wp but also the narrow internal p-type regions 3e to 3n having a small element region width Wpn exist, the embodiment shown in FIG. Compared with 1, more current flows. Further, at a voltage equal to or higher than the forbidden band width, a current flows through the pin diode portion configured by the wide internal p-type regions 3a and 3b having the element region width Wp larger than the value of the expression (1).

  Therefore, by adopting the configuration of the semiconductor device 40 of the present embodiment, the relatively low current density, that is, the resistance and operating voltage in the low voltage region are made lower than those of the semiconductor device 10 of the first embodiment, and It is possible to reduce the operating voltage at a high current density without bending the current / voltage characteristics, that is, without causing kinking.

  The numbers of the narrow internal p-type regions 3e to 3n and the wide internal p-type regions 3a and 3b are determined according to the current density at which the element is used. For example, when importance is attached to use at a relatively low current density flowing through the Schottky barrier diode portion, the narrow internal p-type regions 3e to 3n having the narrow pin region width Wps may be increased. If importance is attached to the use at a relatively high current density flowing through the pin diode portion, the wide internal p-type regions 3a and 3b having the wide pin region width Wp may be increased.

  The narrow pin region width Wpn and the narrow Schottky region width Wsn may be smaller than 50 μm, which is the minimum value of the range shown in FIG. 2, or may be smaller than 4 μm which is generally used. A value smaller than 50 μm is preferable because a current at a voltage up to the vicinity of the forbidden bandwidth can be increased.

  The narrow pin region width Wpn is such that the depletion layer of the pn junction consisting of the narrow internal p-type regions 3e to 3n and the n-type SiC drift layer 2 is narrow when a voltage close to a withstand voltage is applied in the reverse direction. The lower limit is a value at which the internal p-type regions 3e to 3n are not completely depleted in the lateral direction toward the plane of FIG. 7, that is, in the direction perpendicular to the thickness direction of the n-type SiC substrate 1. Specifically, the width varies depending on the doping concentration of the narrow internal p-type regions 3e to 3n, but the narrow pin region width Wpn is about 1.5 to 2 μm.

  As described above, the narrow Schottky region width Wsn is equal to or larger than the narrow pin region width Wpn (Wpn ≦ Wsn). Therefore, the lower limit of the narrow pin region width Wpn, that is, a value that does not completely deplete the narrow internal p-type regions 3e to 3n laterally toward the plane of FIG. 7 is the width of the narrow Schottky region width Wsn. Lower limit.

  FIG. 8 is a cross sectional view showing a configuration of a semiconductor device 41 using the silicon carbide semiconductor element in the first modification of the fourth embodiment of the present invention. In the example shown in FIG. 7, the wide internal p-type regions 3a and 3b having the wide pin region width Wp, which is the device region width larger than the value of the expression (1), are arranged at the center of the device. The position of the wide internal p-type region 3 is not limited to this. For example, as in Modification 1 shown in FIG. 8, wide internal p-type regions 3a to 3d may be arranged in a region close to the peripheral portion of the element.

  As described above, current flows through the Schottky barrier diode portion at voltages up to the vicinity of the forbidden band width, and is configured by the wide internal p-type regions 3a to 3d having a large element region width Wp at voltages above the forbidden band width. A current flows through the pin diode portion. Therefore, the device region width of the Schottky barrier diode portion is the wide Schottky region width Ws or the narrow Schottky region width Wsn, and the current density becomes non-uniform depending on the driving state of the device due to different positions. .

  By utilizing this, it is possible to obtain a current density state suitable for the driving conditions of the element. Specifically, by appropriately selecting the positions of the wide internal p-type regions 3a to 3d, the current is concentrated in the central part of the element or the current is concentrated in the peripheral part according to the driving conditions of the element. It is possible.

  When the wide internal p-type regions 3a to 3d and the narrow internal p-type regions 3e to 3h are provided and the element region widths Wp and Wpn of the pin diode portion are set to different values as in the present embodiment, the wide The element region widths W1 and W2 of the Schottky barrier diode portion at the boundary between the internal p-type regions 3a to 3d and the narrow internal p-type regions 3e to 3h are either the wide Schottky region width Ws or the narrow Schottky region width Wsn. There may be. For example, a narrow Schottky region width Wsn may be set, such as the element region width W1 at the boundary between the second wide internal p-type region 3b and the first narrow internal p-type region 3e shown in FIG. The wide wide Schottky region width Wsn may be set like the element region width W2 at the boundary between the fourth narrow internal p-type region 3h and the third wide internal p-type region 3c.

  FIG. 9 is a cross-sectional view showing a configuration of semiconductor device 42 using the silicon carbide semiconductor element in the second modification of the fourth embodiment of the present invention, and FIG. 10 shows a third modification of the fourth embodiment of the present invention. It is sectional drawing which shows the structure of the semiconductor device 43 using the silicon carbide semiconductor element in. The wide internal p-type region 3 having a wide pin region width Wp that is an element region width larger than the value of the expression (1) may be arranged as shown in FIG. 9 or FIG.

  In Modification 2 shown in FIG. 9, wide internal p-type regions 3a-3c having a large element region width Wp and narrow internal p-type regions 3e-3h having a small element region width Wpn are alternately arranged, and The Schottky barrier diode region width, which is the length 8 of the Schottky barrier diode portion between two adjacent portions of the internal p-type SiC region 3, is unified to one, specifically, the wide Schottky region width Ws. Yes. Of the internal p-type SiC regions 3, the wide pin region widths Wp of the wide internal p-type regions 3a to 3c having an element region width larger than the value of the expression (1) are unified into one. ing.

  In the third modification shown in FIG. 10, the wide internal p-type regions 3a and 3b and the narrow internal p-type regions 3e to 3j are composed of one narrow internal p-type region 3a and 3b. The mold regions 3e to 3j are alternately arranged at a ratio of two. Similarly to the second modification shown in FIG. 9, the Schottky barrier diode region width Ws between the internal p-type SiC regions 3 is unified to one, and the wide pin region width Wp of the wide internal p-type regions 3a and 3b is also 1 Are unified.

  As described above, a current flows through the Schottky barrier diode portion at a voltage up to the vicinity of the forbidden band, and a pin diode composed of the wide internal p-type regions 3a to 3c having a large element region width Wp at a voltage near the forbidden band. Current flows through the part. In the example shown in FIGS. 9 and 10, since the wide pin region width Wp is unified, the widths of the pin diode portions in the element are all the same value. Therefore, in the examples shown in FIGS. 9 and 10, it is possible to make the current density distribution in the element more uniform than in the examples shown in FIGS.

  In the examples shown in FIGS. 9 and 10, the Schottky barrier diode region width Ws is unified to one, so that the widths of the Schottky barrier diode portions in the element are all the same value. Therefore, in the examples shown in FIGS. 9 and 10, it is possible to make the current density distribution in the element more uniform than in the examples shown in FIGS.

  In particular, in the example shown in FIGS. 9 and 10, the wide internal p-type regions 3a to 3c and the narrow internal p-type regions 3e to 3j are alternately arranged at a constant ratio, and the Schottky barrier diode region width Ws. Are unified into one, and the wide pin region width Wp is also unified into one, so that the widths of the regions where current flows are all the same value in the element. Therefore, in the examples shown in FIGS. 9 and 10, it is possible to make the current density distribution in the element more uniform than in the examples shown in FIGS.

<Embodiment 5>
FIG. 11 is a cross sectional view showing a configuration of semiconductor device 50 using the silicon carbide semiconductor element in the fifth embodiment of the present invention. Since the semiconductor device 50 of the present embodiment is similar in configuration to the semiconductor device 40 of the fourth embodiment, only different parts will be described, and corresponding parts will be denoted by the same reference numerals and common. Description is omitted.

  The semiconductor device 50 of the present embodiment is different from the semiconductor device 40 of the above-described fourth embodiment in that the n-type SiC drift layer 2 is in contact with the anode electrode 5 in the semiconductor device 50 of the present embodiment. This is that the Schottky barrier diode region widths Ws and Wsn, which are the widths of, are larger than the pin diode region widths Wp and Wpn of the adjacent internal p-type SiC region 3. In other words, the pin diode region widths Wp and Wpn of the internal p-type SiC region 3 are smaller than the Schottky barrier diode region widths Ws and Wsn. In the present embodiment, the narrow Schottky region width Wsn is larger than the narrow pin region width Wpn (Wpn <Wsn), and the wide Schottky region width Ws is larger than the wide pin region width Wp. (Wp <Ws).

  The Schottky barrier diode region widths Ws and Wsn are thus made larger than the pin diode region widths Wp and Wpn of the adjacent internal p-type SiC region 3 (Wpn <Wsn, Wp <Ws), whereby the internal p-type SiC region. Thus, the area of the Schottky barrier diode portion formed by the portion where 3 is not formed can be increased. Thereby, the operating voltage at a relatively low current density can be lowered, that is, the on-voltage in a low voltage region where the current of the pin diode portion does not rise can be reduced. Therefore, the semiconductor device 50 having a smaller operating voltage can be realized in a wide current density range.

  Also in the present embodiment, as in the first and fourth embodiments, the internal p-type SiC region 3 is larger than the value of the expression (1) with respect to the doping concentration of the n-type SiC drift layer 2. Wide internal p-type regions 3a to 3c having an element region width Wp are provided. As a result, similar to the first and fourth embodiments, it is possible to reduce the operating voltage at a high current density.

  In the present embodiment, the wide internal p-type regions 3a to 3c satisfying the relationship that the device region width Wp is larger than the value of the expression (1), and the narrow internal p-type region 3e not satisfying the relationship. In both cases, the Schottky barrier diode region widths Ws and Wsn are larger than the pin diode region widths Wp and Wpn, but not necessarily both. For example, only the narrow Schottky region width Wsn may be larger than the narrow pin region width Wpn, or only the wide Schottky region width Ws may be larger than the wide pin region width Wp.

  In the present embodiment, the wide internal p-type regions 3a to 3c are arranged at the center of the element. However, the position of the wide internal p-type region 3 is not limited to this, and the above-described implementation is performed. It is good also as a structure combined with the modifications 1-3 in the form 4. For example, wide internal p-type regions 3a to 3d may be arranged in a region close to the periphery of the element as in Modification 1 in Embodiment 4. Further, as in the second modification or the third modification in the fourth embodiment, the wide internal p-type regions 3a to 3c and the narrow internal p-type regions 3e to 3j are alternately arranged at a constant ratio, and a Schottky barrier diode is provided. The region width Ws may be unified, and the wide pin region width Wp may be unified.

<Embodiment 6>
FIG. 12 is a cross sectional view showing a configuration of a semiconductor device 60 using the silicon carbide semiconductor element in the sixth embodiment of the present invention. Since the semiconductor device 60 of the present embodiment is similar in configuration to the semiconductor device 40 of the fourth embodiment, only different parts will be described, and the corresponding parts will be denoted by the same reference numerals and common. Description is omitted.

  The semiconductor device 60 of the present embodiment differs from the semiconductor device 40 of the above-described fourth embodiment in that the n-type SiC drift layer 2 sandwiched between the internal p-type SiC regions 3 in the semiconductor device 60 of the present embodiment. Region, that is, a Schottky region that is a region between two opposing p-type SiC regions 3 in the n-type SiC drift layer 2, an n-type SiC region 9 formed at a higher doping concentration than the n-type SiC drift layer 2. (9a, 9b, 9c, 9d, 9e...). N-type SiC region 9 corresponds to a second semiconductor region.

  By providing the n-type SiC region 9 in this way and increasing the doping concentration on the surface of the n-type SiC drift layer 2 of the Schottky barrier diode portion constituted by the portion where the internal p-type SiC region 3 is not formed, it is relatively low The operating voltage at the current density can be lowered, that is, the on-voltage in the low voltage region where the current of the pin diode portion does not rise can be reduced. Therefore, the semiconductor device 60 having a smaller operating voltage can be realized in a wide current density range.

  Also in the present embodiment, as in the first and fourth embodiments, the internal p-type SiC region 3 is larger than the value of the expression (1) with respect to the doping concentration of the n-type SiC drift layer 2. Wide internal p-type regions 3a and 3b having an element region width Wp are provided. This makes it possible to reduce the operating voltage at a high current density. Thus, the wide pin region width Wp of the wide internal p-type regions 3 a and 3 b depends on the doping concentration of the n-type SiC drift layer 2, and the n-type SiC region 9 sandwiched between the internal p-type SiC regions 3. It does not depend on the doping concentration.

  In the configuration of the present embodiment, depending on the doping concentration of n-type SiC region 9, Schottky barrier diode region widths Ws and Wsn are larger than pin diode region widths Wp and Wpn of adjacent internal p-type SiC region 3, respectively. Even if the value is small, the operation voltage at a relatively low current density can be reduced. That is, in the present embodiment, Schottky barrier diode region widths Ws and Wsn are set to values smaller than pin diode region widths Wp and Wpn of adjacent internal p-type SiC regions 3 (Wp> Wn, Wpn> Wsn), respectively. Therefore, the semiconductor device 60 can be reduced in size.

  As described above, according to the semiconductor device 60 in the present embodiment, the n-type SiC drift layer 2 of the Schottky barrier diode portion formed by the portion where the n-type SiC region 9 is provided and the internal p-type SiC region 3 is not formed is provided. By increasing the doping concentration on the surface, the on-voltage in the low voltage region where the current of the pin diode portion does not rise can be reduced, and the semiconductor device 60 having a smaller operating voltage can be realized in a wide current density range. Can do. In addition, Schottky barrier diode region widths Ws and Wsn can be set to values smaller than pin diode region widths Wp and Wpn of adjacent internal p-type SiC region 3, so that semiconductor device 60 can be reduced in size. .

  In the present embodiment described above, the wide internal p-type regions 3a and 3b are arranged at the center of the element, but the position of the wide internal p-type region 3 is not limited to this. It is good also as a structure combined with the modifications 1-3 in the above-mentioned Embodiment 4. FIG.

<Embodiment 7>
FIG. 13 is a cross sectional view showing a configuration of semiconductor device 70 using the silicon carbide semiconductor element in the seventh embodiment of the present invention. Since the semiconductor device 70 of the present embodiment is similar in configuration to the semiconductor device 10 of the first embodiment, only different parts will be described, and corresponding parts will be denoted by the same reference numerals and common. Description is omitted.

  The semiconductor device 70 according to the present embodiment is different from the semiconductor device 10 according to the first embodiment described above in that the semiconductor device 70 according to the present embodiment has a termination p-type SiC formed as a termination structure at the periphery of the element. The element region width Wpt of the region 4 is set to a value larger than the value of the following formula (3), and the anode electrode 5 is in ohmic contact with the termination portion p-type SiC region 4. Termination part p type SiC field 4 is equivalent to a termination part semiconductor field.

  The element region width Wpt of the termination portion p-type SiC region 4 is the length 13 of the portion of the n-type SiC drift layer 2 where the termination portion p-type SiC region 4 is formed. The anode electrode 5 is provided in contact with a part of the terminal end p-type SiC region 4, specifically, a part closer to the inside.

  In semiconductor device 70 of the present embodiment, whether or not element region width Wp of internal p-type SiC region 3 (3a, 3b, 3c, 3d...) Is a region width larger than the value of equation (1). Regardless, the element region width Wpt of the termination p-type SiC region 4 is set to a region width larger than the value of the expression (3).

  Thus, by setting the element region width Wpt of the termination p-type SiC region 4 to a value larger than the value of the expression (3), when a voltage corresponding to the forbidden band width of the semiconductor material is applied, n The potential of the type SiC drift layer 2 is sufficiently increased, and the current of the pin diode portion composed of the termination portion p-type SiC region 4 and the n-type SiC drift layer 2 rises. As a result, in the forward characteristics, the current component flowing through the Schottky barrier diode portion is mainly at a relatively low current density, and the current component flowing through the pin diode portion formed of the termination p-type SiC region 4 is mainly at a high current density. A diode configuration can be realized. Therefore, the semiconductor device 70 having a smaller operating voltage can be realized in a wide current density range.

  In the present embodiment, termination p-type SiC region 4 and anode electrode 5 are in ohmic contact, which affects high-speed operation when the switch is turned on and off in a circuit combined with a switching element. Specifically, since the element region width Wpt of the termination p-type SiC region 4 is larger than the value of the expression (3), a current can flow with a smaller voltage, which is effective for high-speed switching.

  FIG. 14 is a cross sectional view showing a configuration of a semiconductor device 71 using a silicon carbide semiconductor element in a modification of the seventh embodiment of the present invention. The configuration of the termination p-type SiC region 4 is not limited to the case where the internal p-type SiC region 3 is provided as in the semiconductor device 70 shown in FIG. The present invention can also be applied to a Schottky barrier diode in which the p-type SiC region 3 does not exist. Also in the case of the Schottky barrier diode shown in FIG. 14, the width Wpt of the termination portion p-type SiC region 4 is set to a value larger than the value of the expression (3).

  Thus, by setting the width Wpt of the termination p-type SiC region 4 to a value larger than the value of the expression (3), the semiconductor material is formed in the same manner as when the internal p-type SiC region 3 shown in FIG. When a voltage corresponding to the forbidden band width is applied, the potential of the n-type SiC drift layer 2 rises sufficiently, and the pin diode portion composed of the termination p-type SiC region 4 and the n-type SiC drift layer 2 Current will rise. As a result, in the forward characteristics, the current component flowing through the Schottky barrier diode portion is mainly at a relatively low current density, and the current component flowing through the pin diode portion formed of the termination p-type SiC region 4 is mainly at a high current density. A diode configuration can be realized. Therefore, the semiconductor device 71 having a smaller operating voltage can be realized in a wide current density range. It is also effective for high-speed switching.

  The pin diode part may be provided only at the terminal end as shown in FIG. 14, but if the pin diode part is only the terminal end, the area operating as the pin diode part is limited. As shown in FIG. 13, it is preferable to provide an internal p-type SiC region 3 and form a pin diode portion inside the element. That is, whether or not the internal p-type SiC region 3 is provided may be appropriately selected depending on the current density of the element. For example, when importance is attached to the use at a relatively low current density flowing through the Schottky barrier diode portion, the termination portion p-type SiC region 4 is provided, and the element region width Wpt is larger than the value of the expression (3). The internal p-type SiC region 3 may not be provided. When importance is attached to the use at a relatively high current density flowing through the pin diode portion, an internal p-type SiC region 3 is provided together with the termination portion p-type SiC region 4, and the element region width Wp is expressed by equation (1). The value may be set to a value larger than the value of.

  The structure of termination portion p-type SiC region 4 shown in FIGS. 13 and 14 may be combined with the structure having the element portion shown in the first to sixth embodiments.

  As described above, the first to seventh embodiments have described the case where silicon carbide (SiC) is used as an example of the semiconductor element. However, gallium nitride (GaN), aluminum gallium nitride (AlGaN), and aluminum gallium indium nitride (AlGaInN) are described. In the device structure in which a Schottky barrier diode and a pin diode are connected in parallel in a wide gap semiconductor such as a group III nitride such as zinc oxide (ZnO), etc., there is a similar effect and drift. By setting the pin diode region width Wp according to the layer doping concentration, the operating voltage in a high current density region can be reduced. The above-described wide gap semiconductor has a forbidden band width of 3 to 3.5 eV.

  Further, the present invention is not limited to the above-described embodiment, and for example, is applied to a semiconductor device in which the conductivity type of a semiconductor layer of a diode is reversed, that is, a semiconductor device in which p is changed to n and n is changed to p. It goes without saying that it is possible.

  1 n-type SiC substrate, 2 n-type SiC drift layer, 3 internal p-type SiC region, 4 termination p-type SiC region, 5 anode electrode, 6 cathode electrode, 7 pin diode region width, 8 Schottky barrier diode region width, 9 n-type SiC region, 10, 20, 30, 40, 41, 42, 43, 50, 60, 70, 71 Semiconductor device.

Claims (8)

A first conductivity type semiconductor substrate;
A semiconductor layer of a first conductivity type formed on the semiconductor substrate at a lower doping concentration than the semiconductor substrate;
A first semiconductor region of a second conductivity type juxtaposed with a predetermined interval on a surface layer of the semiconductor layer;
A first electrode formed on the semiconductor layer and the first semiconductor region, in Schottky contact with the semiconductor layer and in ohmic contact with the first semiconductor region;
A second electrode formed on the back surface of the semiconductor substrate,
The width Wp (μm) of the first semiconductor region and the doping concentration N (cm ⁻³ ) of the semiconductor layer are
Wp> −72 × ln (N) +2585
A semiconductor device having the relationship The width Wp (μm) of the first semiconductor region and the doping concentration N (cm ⁻³ ) of the semiconductor layer are
−108 × ln (N) +4027.5>Wp> −72 × ln (N) +2585
The semiconductor device according to claim 1, having the relationship: The width Wp (μm) of the first semiconductor region has two or more values, of which at least one width Wp (μm) of the first semiconductor region and the doping concentration N (cm ^{− of the} semiconductor layer). ³ )
Wp> −72 × ln (N) +2585
Have the relationship
The width Wpn (μm) of at least one other first semiconductor region and the doping concentration N (cm ⁻³ ) of the semiconductor layer are:
Wpn ≦ −72 × ln (N) +2585
The semiconductor device according to claim 1, having the relationship: The width Wp (μm) of the first semiconductor region has two or more values, and the doping concentration N (cm ⁻³ ) of the semiconductor layer;
Wp> −72 × ln (N) +2585
4. The semiconductor device according to claim 1, wherein a width Wp of the first semiconductor region having the relationship is unified to one value. 5. The semiconductor layer comprises a plurality of Schottky regions sandwiched between two opposing first semiconductor regions;
5. The semiconductor device according to claim 1, wherein a width Ws of the plurality of Schottky regions is unified to one value. 6.   6. The semiconductor according to claim 1, wherein a width Wp of the first semiconductor region is smaller than a width Ws of a Schottky region between two opposing first semiconductor regions in the semiconductor layer. apparatus.   The semiconductor layer further includes a second semiconductor region of a first conductivity type formed at a higher doping concentration than the semiconductor layer in a Schottky region between the two opposing first semiconductor regions in the semiconductor layer. The semiconductor device according to any one of the above. A first conductivity type semiconductor substrate;
A semiconductor layer of a first conductivity type formed on the semiconductor substrate at a lower doping concentration than the semiconductor substrate;
A first semiconductor region of a second conductivity type formed in a surface layer of at least a peripheral portion of the semiconductor layer;
A first electrode formed on the semiconductor layer and the first semiconductor region, in Schottky contact with the semiconductor layer and in ohmic contact with the first semiconductor region;
A second electrode formed on the back surface of the semiconductor substrate,
Of the first semiconductor region, the width Wpt (μm) of the termination semiconductor region formed in the surface layer around the semiconductor layer as a termination structure and the doping concentration N (cm ⁻³ ) of the semiconductor layer are:
Wpt> −72 × ln (N) +2585
A semiconductor device having the relationship

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