JP2010087157A - Method of producing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve processability in the etching process of a polycrystal silicon film having a high aspect ratio. <P>SOLUTION: A gate insulating film 4 is formed on the upper surface of a silicon substrate 1. On the upper surface of this film, a processing object film formed of a laminating film of a gate electrode constituted with polycrystal silicon films 5, 7 and an electrode-to-electrode insulating film 6 is further formed. On the upper surface of this film, moreover, a silicon nitride film 8 and an aluminum oxide film 9 functioning as hard masks are laminated. The silicon nitride film 10 corresponding to the existing film contributes to reduction in thickness of the hard mask in comparison with the hard mask formed of single layer. Therefore, the final processing width C1 can be reduced for C2 in comparison with a pattern width A in lithography and thereby a process conversion difference can be reduced. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including an etching process of a film mainly composed of a polycrystalline silicon film formed on a semiconductor substrate via an insulating film.

  In the manufacturing method of a semiconductor device, when a polycrystalline silicon film formed on a semiconductor substrate is etched, a method as disclosed in, for example, Patent Document 1 is conventionally used. In this method, a silicon oxide film, a silicon nitride film, or the like is formed as a processing film on a polycrystalline silicon film to be processed and used as a hard mask.

  However, with the miniaturization of the device, the polycrystalline silicon film having the same film thickness also has a narrow pattern width. Therefore, the aspect ratio in the etching process is increasing, and it is difficult to control the processing shape.

  In particular, in the processing of a polycrystalline silicon film in a structure in which a high aspect ratio is required, such as a nonvolatile semiconductor memory device, or a structure having both a sparse part and a dense part of a pattern but having a gate electrode. If the hard mask film thickness required to process both the control gate and floating gate electrodes is secured, the processing conversion difference that occurs during hard mask processing and the processing conversion difference that occurs during processing of the polycrystalline silicon film of the gate electrode As a result, the processing conversion difference between the sparse pattern portion and the dense pattern portion also increases.

  In other words, in actual etching processing, etching does not proceed perpendicularly to the width dimension of the mask pattern, but tends to narrow the groove width as it is dug down. The difference becomes larger. The difference in the width dimension at the time of processing is a processing conversion difference. Therefore, this etching conversion difference tends to increase as etching with a higher aspect ratio is performed.

For this reason, when the size and shape of the sparse pattern portion are controlled, shape deterioration such as occurrence of side etching of the polycrystalline silicon film in the dense pattern portion occurs, and conversely the size and shape of the dense pattern portion. If this control is performed, the processing conversion difference in the sparse pattern portion will increase, making it difficult to achieve both control in the sparse pattern portion and the dense pattern portion.
JP 2007-184489 A

  An object of the present invention is to provide a semiconductor device manufacturing method capable of improving workability in etching a polycrystalline silicon film having a high aspect ratio.

  According to one aspect of the method for manufacturing a semiconductor device of the present invention, a step of forming a gate insulating film and a polycrystalline silicon film on a semiconductor substrate, and aluminum (Al) and hafnium (Hf) on the upper surface of the polycrystalline silicon film. Forming an etching process film made of any one of aluminum oxide (AlOx) and hafnium oxide (HfOy), patterning the etching process film into a predetermined shape, and forming a hard mask; and And using the step of selectively etching the polycrystalline silicon film.

  According to the method for manufacturing a semiconductor device of the present invention, it is possible to improve workability in etching a polycrystalline silicon film having a high aspect ratio.

  Hereinafter, an embodiment in which the present invention is applied to a NAND flash memory device will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  First, the configuration of the NAND flash memory device of this embodiment will be described. FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device.

  The memory cell array of the NAND flash memory device includes two selection gate transistors Trs1 and Trs2, and a plurality (for example, 8: 2 to the nth power (n is a positive number) connected in series between the selection gate transistors Trs1 and Trs2. The memory cell transistor Trm includes a NAND cell unit (memory unit) Su, and the NAND cell units Su are arranged in a matrix. In the NAND cell unit Su, a plurality of memory cell transistors Trm share a source / drain region with adjacent ones.

  The memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the gate width direction) in FIG. 1 are commonly connected by a word line (control gate line) WL. Further, the selection gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a selection gate line SGL1, and the selection gate transistors Trs2 are commonly connected by a selection gate line SGL2. A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in the Y direction (corresponding to the gate length direction and the bit line direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  FIG. 2A shows a partial layout pattern of the memory cell region, and FIG. 2B is a plan view showing a high voltage transistor or a low voltage transistor in the peripheral circuit portion. 2A, a plurality of element isolation insulating films 2 formed by STI (shallow trench isolation) method are formed on a silicon substrate 1 as a semiconductor substrate at a predetermined interval along the Y direction in FIG. Thus, the active region 3 is formed separately in the X direction in FIG. Word lines WL of the memory cell transistors are formed at predetermined intervals along the X direction in FIG. 2A orthogonal to the active region 3. Further, a selection gate line SGL1 of a pair of selection gate transistors is formed along the X direction in FIG. Bit line contacts CB are formed in the active region 3 between the pair of select gate lines SGL1. The gate electrode MG of the memory cell transistor that is the first gate electrode is on the active region 3 that intersects the word line WL, and the selection gate that is the second gate electrode is on the active region 3 that intersects the selection gate line SGL1. A gate electrode SG of the transistor is formed.

  In FIG. 2B, the transistor TrP formed in the peripheral circuit portion is provided in a portion where the element isolation insulating film 2 is formed on the silicon substrate 1 so as to leave the active region 3a in a rectangular shape. A gate electrode PG is formed across the active region 3a, and source / drain regions formed by diffusing impurities are provided on both sides thereof. Contact plug CP is formed in source / drain region 1c and gate electrode PG.

  FIGS. 3A and 3B are cross-sectional views taken along section line AA in FIG. 2A and section line BB in FIG. 2B, respectively. That is, a schematic diagram in the middle of the manufacturing process of the memory cell transistor Trm in the memory cell region having the narrowest pattern interval and the transistor TrP in the peripheral circuit portion having the wide pattern interval shown with the gate electrode MG portion in the active region 3 as the center. It is sectional drawing and shows one step of the formation process of gate electrodes MG and PG.

3A and 3B, the gate electrodes MG and PG formed on the silicon substrate 1 through the tunnel insulating film 4 as a gate insulating film are polycrystalline layers which are conductive layers for floating gate electrodes. Silicon film 5, inter-electrode insulating film 6 made of ONO (oxide-nitride-oxide) film, NONON (nitride-oxide-nitride-oxide-nitride) film or high dielectric (high-k material) film, control gate electrode A polycrystalline silicon film 7 as a conductive layer is laminated, and a silicon nitride film 8 as an etching processed film serving as a hard mask and aluminum oxide (AlOx: x is a composition ratio with respect to Al) is formed thereon. A film 9 is laminated. Instead of the silicon nitride film 8, a BSG (boron silicate glass) film, a TEOS (tetraethyl orthosilicate) film, or the like can be used. Instead of the alumina film 9, an aluminum (Al) film, an alumina (Al ₂ O ₃ ) film, a hafnium (Hf) film, a hafnium oxide (HfOy: y is a composition ratio with respect to Hf) film, or the like is used as a single film or a composite film. Can be used as

  As shown in FIG. 3B, the interelectrode insulating film 6 of the gate electrode PG is formed with an opening 6a for conducting the polycrystalline silicon film 5 and the polycrystalline silicon film 7, and this opening. A polycrystalline silicon film 7 is embedded in 6a. In the transistor TrP in the peripheral circuit portion, a gate insulating film 4a having a different thickness may be formed with respect to the gate insulating film 4 of the memory cell transistor Trm. For example, a high-voltage transistor forms a thick gate insulating film, and a low-voltage transistor forms a gate insulating film having a thickness equal to or thinner than that of a memory cell transistor.

  In the above configuration, the silicon nitride film 8 and the aluminum oxide film 9 used as etching processed films are used to etch the polycrystalline silicon film 7, the interelectrode insulating film 6 and the polycrystalline silicon film 5 as shown in the figure. It is necessary to set the required film thickness. In this case, for example, when only the silicon nitride film 10 is used as an etching processed film as in the prior art, the total film thickness Ds of the film thickness Da of the silicon nitride film 8 and the film thickness Db of the aluminum oxide film 9 described above. A thicker film thickness Dp is required. In this regard, when the aluminum oxide film 9 is used, the etching selectivity can be made high with respect to the polycrystalline silicon films 7 and 5, so that the thickness of the hard mask can be reduced as a whole.

For this reason, a processing conversion difference S as shown in FIGS. 4A and 4B taking the memory cell transistor as an example is generated. That is, FIG. 4A shows the configuration of the etching processed film in the present embodiment, and FIG. 4B shows the etching processed film having the conventional configuration in comparison. Here, the processing conversion difference S will be described first. The processing conversion error S referred to in the present embodiment is, for example, a pattern width dimension C (C1 or C2 in the figure) at the bottom surface of the pattern actually etched with respect to the width dimension A of the mask pattern in lithography processing. And the difference value. That means
Processing conversion error S = CA
It becomes. In this case, the total film thicknesses Do of the polycrystalline silicon film 5, the interelectrode insulating film 6, and the polycrystalline silicon film 7 to be processed are the same in FIGS. 4A and 4B. .

In FIG. 4A corresponding to the present embodiment, it corresponds to the conventional film thickness Ds (= Da + Db) of the silicon nitride film 8 and the aluminum oxide film 9 of the etching processed film patterned on the hard mask. In FIG. 4B, the film thickness Dp of the silicon nitride film 10 is necessary, and between these,
Ds <Dp
There is a relationship.

  If the etching process is performed by the RIE (reactive ion etching) method under the same conditions, in the case of the present embodiment, in the case where the side wall is inclined as the etching proceeds, The width dimension is B1, and B2 in the conventional equivalent. In this case, the width dimension B2 of the conventional one becomes larger (B1 <B2) as the film thickness, that is, the height is higher.

Therefore, when the hard mask formed in this way is used, the etching process by the RIE method is similarly performed, and the polycrystalline silicon film 7, the interelectrode insulating film 6, and the polycrystalline silicon film 5 are sequentially etched. The thickness Do is dug down, and the width dimensions of the lower end surface of the polycrystalline silicon film 5 are C1 and C2, respectively. In this case, since the width dimension B2 of the conventional equivalent is larger than B1 as described above, the relationship of the width dimension by the final processing conversion is as follows.
C1 <C2
It becomes the relationship.

That is, the processing conversion difference S1 of the present embodiment and the processing conversion difference S2 corresponding to the conventional one have the following values.
S1 = C1-A
S2 = C2-A
S1 <S2
Therefore, the processing conversion difference S1 is reduced by the amount that the thickness Ds of the hard mask using the silicon nitride film 8 and the aluminum oxide film 9 of this embodiment is smaller than the film thickness Dp of the silicon nitride film 10 corresponding to the prior art. Can be processed smoothly.

Next, an example of a manufacturing process having the above-described configuration will be described with reference to FIGS.
First, as shown in FIG. 5, the layers for forming the gate electrodes MG and PG are stacked on the silicon substrate 1. First, the gate insulating film 4 is formed on the entire surface of the silicon substrate 1. The gate insulating film 4 is a silicon oxide film formed by, for example, a thermal oxidation method, and its film thickness is set to a level that can secure a necessary breakdown voltage. The memory cell region is formed with a film thickness of about 8 nm, for example, and the peripheral circuit region is formed with a film thickness of about 8 nm and a film thickness of about 35 nm according to the breakdown voltage of the transistor TrP. The gate insulating film 4 may be a single layer film such as a silicon nitride film or an oxynitride film, or a composite film in which at least one of a silicon oxide film and an oxynitride film is combined.

  Next, a polycrystalline silicon film 5 serving as a floating gate electrode film is formed on the entire surface of the gate insulating film 4 with a film thickness of 95 nm by CVD (chemical vapor deposition), and phosphorus (P) or boron (B) is highly concentrated. Is added to form a film.

  Thereafter, an interelectrode insulating film 6 is formed on the polycrystalline silicon film 5 with a film thickness of 16 nm by the CVD method. As described above, the interelectrode insulating film 6 is an ONO film, a NONON film, or a film of a high dielectric constant material (high-k). In this interelectrode insulating film 6, the gate electrode SG of the select gate transistors Trs1 and Trs2 in the memory cell region and a part of the interelectrode insulating film 6 in the region that becomes the transistor TrP in the peripheral circuit portion are removed to form an opening 6a. And the polycrystalline silicon films 5 and 7 of the floating gate electrode film and the control gate electrode film are electrically connected through the opening 6a.

Next, a polycrystalline silicon film 7 for the control gate electrode film is formed over the entire surface of the interelectrode insulating film 6 with a film thickness of 165 nm by adding phosphorus (P) or boron (B) at a high concentration. Thereafter, a silicon nitride film 8 and an aluminum oxide (AlOx; for example, alumina (Al ₂ O ₃ )) film 9 are formed on the polycrystalline silicon film 7 as a hard mask film by, eg, CVD method. The state shown in 5 is obtained. In this case, a BSG film, a TEOS film, or the like can be used as the etching film instead of the silicon nitride film 8. Further, instead of the aluminum oxide film 9, for example, an aluminum (Al) film, a hafnium (Hf) film, a hafnium oxide (HfOy) film, or the like can be used.

  Next, as shown in FIG. 6, the aluminum oxide film 9 is etched by lithography to form hard masks 9a and 9b. Here, a resist pattern (not shown) is formed on the aluminum oxide film 9, and the aluminum oxide film 9 is dry-etched by a RIE method using a chlorine (Cl) -containing gas using the resist pattern as a mask. A hard mask 9a for transistors, a hard mask 9b for transistors in the peripheral circuit portion, and a hard mask for transistors not shown are formed. Thereafter, the resist pattern is peeled off. Subsequently, using the hard masks 9a and 9b formed as described above as a mask, the silicon nitride film 8 is processed by a dry etching method using a gas containing a fluoromethane-based (CHxFy) gas. Thereby, hard masks 8a and 8b are formed.

  Subsequently, as shown in FIG. 7, the polycrystalline silicon film 7 of the control gate electrode is processed by dry etching using the hard masks 9a, 8a and 9b, 8b as masks. Here, the gas used for etching is hydrogen bromide (HBr) as a main gas and a gas obtained by mixing fluoromethane (CHxFy) gas or chlorine (Cl2) gas.

Next, as shown in FIG. 8, the interelectrode insulating film 6 is processed with a fluorine (F) -containing gas using a dry etching method. When the processing of the interelectrode insulating film 6 is completed, the etching process of the polycrystalline silicon film 5 is continued again using the etching conditions of the polycrystalline silicon film 7. When the polycrystalline silicon film 5 can be processed to a predetermined film thickness, the polycrystalline silicon film 5 is etched using, for example, a mixed gas of hydrogen bromide (HBr) gas, oxygen (O ₂ ) gas, and nitrogen (N ₂ ) gas. Remove the residue. Thereby, the process of the state shown in FIG. 3 can be performed.

Thereafter, a NAND flash memory device is formed through a processing step for forming the gate electrode G, a diffusion region forming step, a wiring step, and the like.
In the case of the above manufacturing process, the thickness of the silicon nitride film 8 and the aluminum oxide film 9 used as a hard mask will be briefly described. That is, as an example, in the case of the above-described process for processing a gate electrode in a design design with an aspect ratio of up to about 5, a hard mask with a silicon nitride film 10 equivalent to the conventional case is used ( As shown in FIG. 4B, the silicon nitride film 10 having a thickness of 200 nm or more is required.

  On the other hand, when the film structure of the present embodiment is used, when the alumina film is used as the aluminum oxide film 9, the polycrystalline silicon film 7 can be etched by using, for example, a hard mask having a film thickness of about 60 nm. Further, the processing conversion difference S in the portion where the pattern when the hard mask film thickness of the silicon nitride film 10 corresponding to the conventional film is 200 nm is sparse is about 100 nm, whereas the hard film of the alumina film is used when this embodiment is used. It is possible to reduce the processing conversion difference S in a portion where the pattern becomes sparse when the mask film thickness is 60 nm to about 45 nm.

From the above results, according to the present embodiment, the hard mask film thickness is reduced when the polycrystalline silicon films 7 and 5 are etched by using the etching film for the aluminum oxide film 9 and the silicon nitride film 8. Therefore, the difference depending on the density area of the pattern of the processing conversion difference S can be reduced.
In particular, when the aspect ratio of the dense pattern portion is 5 or more, it is possible to suppress the occurrence of an etching difference due to the shape density difference, and the workability of the gate electrode film can be improved.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
As the gate insulating film 4, in addition to the silicon oxide film, a single layer film such as a silicon nitride film or an oxynitride film, or a composite film combining at least one of a silicon oxide film and an oxynitride film may be used. it can.

The film to be processed may be a single film of a polycrystalline silicon film or a structure in which another insulating film or the like is interposed.
Although the case where the laminated film of the aluminum oxide film 9 and the silicon nitride film 8 is used as the etching processed film has been described, only the aluminum oxide film 9 can be used. Furthermore, a film configuration in which other etching processed films are stacked can also be used.

1 is an equivalent circuit diagram showing a part of a memory cell array of a NAND flash memory device showing an embodiment of the present invention; Schematic plan view showing a layout pattern of a part of the memory cell region and peripheral circuit transistors Sectional drawing of the part shown by the cutting lines AA and BB in FIG. Diagram for explaining machining process difference Schematic cross-sectional view at one stage of the manufacturing process (Part 1) Schematic cross-sectional view at one stage of the manufacturing process (Part 2) Schematic cross-sectional view at one stage of the manufacturing process (Part 3) Schematic cross-sectional view at one stage of the manufacturing process (Part 4)

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 4 is a gate insulating film, 4a is a polycrystalline silicon film, 6 is an inter-electrode insulating film, 7 is a polycrystalline silicon film, and 8 is a silicon nitride film (for etching processing). Films 9 and 9 are aluminum oxide films (etching films).

Claims (4)

Forming a gate insulating film and a polycrystalline silicon film on a semiconductor substrate;
Forming an etching processed film made of any of aluminum (Al), hafnium (Hf), aluminum oxide (AlOx), and hafnium oxide (HfOy) on the upper surface of the polycrystalline silicon film;
Patterning the etched film into a predetermined shape to form a hard mask;
And a step of selectively etching the polycrystalline silicon film using the hard mask. Forming an insulating film, a first polycrystalline silicon film, an interelectrode insulating film, and a second polycrystalline silicon film on a semiconductor substrate;
Forming an etching processed film made of any of aluminum (Al), hafnium (Hf), aluminum oxide (AlOx), and hafnium oxide (HfOy) on the upper surface of the second polycrystalline silicon film;
Patterning the etched film into a predetermined shape to form a hard mask;
And a step of selectively etching the second polycrystalline silicon film, the interelectrode insulating film, and the first polycrystalline silicon film using the hard mask. Production method. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The etching processed film is formed as a film including a plurality of types of films among aluminum (Al), hafnium (Hf), aluminum oxide (AlOx), and hafnium oxide (HfOy). Method. In the manufacturing method of the semiconductor device in any one of Claims 1 thru | or 3,
The method for manufacturing a semiconductor device is characterized in that the etching film includes at least one of a silicon oxide film (SiO 2), a silicon nitride film (SiN), and a silicon carbide film (SiC) as a lower layer. .

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