JP2010085935A - Display panel module, semiconductor integrated circuit and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose a driving technology suitable for a high resolution display panel. <P>SOLUTION: In this self-emitting display panel module in which driving timing of a power line is made common per a plurality of horizontal lines, starting timing of a correction operation of characteristic variation of a thin film transistor for current drive constituting a pixel circuit is optimized. Specifically, when latency until a threshold correction operation is started for the head line of the power line in which the driving timing is made common after potential of the power line is switched to a light-emitting potential is controlled to the same pixel grayscale as all of the plurality of horizontal lines in which the driving timing is made common, the latency is set after the point of time when luminance difference between a luminance level of the head line and a luminance level of the last line becomes <1%. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The invention described in this specification relates to a driving technique of a pixel circuit that drives a current-driven self-luminous element. Note that the invention proposed in this specification also has a side surface as a display panel module, a semiconductor integrated circuit, and an electronic device on which the display panel module is mounted.

Hereinafter, an example of an organic EL panel module adopting an active matrix driving method will be described as an example of a panel structure and a driving operation thereof.
FIG. 1 shows a panel structure example of an organic EL panel module. The organic EL panel module 1 shown in FIG. 1 includes a pixel array unit 3, a signal line driving unit 5, a writing control line driving unit 7, and a power supply line driving unit 9 that are driving circuits thereof.
In the pixel array unit 3, one pixel constituting the white unit is arranged with a prescribed resolution in the vertical direction and the horizontal direction in the screen.

FIG. 2 shows an arrangement example of the sub-pixels 11 constituting one pixel as a white unit. In the case of FIG. 2, one pixel is configured as an aggregate of R (red) pixel 11, G (green) pixel 11, and B (blue) pixel 11. Therefore, if the vertical resolution of the pixel array unit 3 is M and the horizontal resolution is N, the total number of sub-pixels of the pixel array unit 3 is given by M × N × 3.
FIG. 1 shows a connection relationship between the sub-pixel 11 that is the minimum unit of the pixel structure constituting the pixel array unit 3 and its drive circuit unit.

The signal line driver 5 is a drive device that supplies a signal potential Vsig and the like corresponding to the pixel data Din to the signal line DTL. The individual signal lines DTL are arranged so as to extend in the Y direction, and 3N lines are arranged in the horizontal direction (X direction) of the screen.
The write control line driving unit 7 transmits a signal potential Vsig to the sub-pixel 11 through the write control line WSL.
It is a drive device that controls writing such as line-sequentially. In the case of FIG. 1, the write control line drive unit 7 performs an operation of designating the write timings of the offset potential Vofs and the signal potential Vsig sequentially in units of horizontal lines.

The power supply line drive unit 9 is a drive device that controls the operation state of the sub-pixel 11 through potential control of the power supply line DSL having a function as a current supply line. Specifically, the power supply line driving unit 9 drives the power supply line DSL with two values of the high potential Vcc and the low potential Vss.
Note that both the write control line WSL and the power supply line DSL described above are arranged along the X direction in the drawing. That is, these two lines are wired as a set for each horizontal line.

  FIG. 3 shows a pixel structure of the sub-pixel 11. As shown in FIG. 3, the sub-pixel 11 includes a thin film transistor N1 (hereinafter referred to as “sampling transistor N1”), a thin film transistor N2 (hereinafter referred to as “drive transistor N2”), and a storage capacitor Cs that holds gradation information. And an organic EL element OLED.

  Among these, one main electrode of the sampling transistor N1 is connected to the signal line DTL, and the other main electrode is connected to the gate electrode (control electrode) of the driving transistor N2. The gate electrode (control electrode) of the sampling transistor N1 is connected to the write control line WSL.

One main electrode of the drive transistor N2 is connected to the power supply line DSL, and the other main electrode is connected to the anode side of the organic EL element OLED. The storage capacitor Cs that holds the gradation information is connected between the gate electrode of the drive transistor N2 and the anode of the organic EL element OLED. In the case of FIG. 3, the thin film transistors are all assumed to be N-channel type.
JP 2003-271095 A JP 2003-255897 A JP 2005-173434 A JP 2006-215213 A

As described above, the panel structure shown in FIG. 1 requires the same number of write control lines WSL and power supply lines DSL as the vertical resolution. For this reason, the write control line drive unit 7 and the power supply line drive unit 9 need the same number of final output stage buffers as these control lines.
However, nowadays, the vertical resolution is very high. Along with this, many expensive final output stage buffers are required, and the manufacturing cost is high.

Therefore, a mechanism capable of driving the pixel array unit 3 with a smaller number of final output stage buffers than the present is required from the viewpoint of manufacturing cost reduction.
As one of such mechanisms, a driving method for sharing the driving timing of the power supply line DSL for a plurality of horizontal lines is conceivable. In this case, the power supply line driving unit 9 drives the common power supply line CDSL obtained by bundling a plurality of power supply lines. Therefore, on the surface, the number of wires to be driven by the power supply line driving unit 9 is reduced to a fraction of the vertical resolution.

FIG. 4 shows a panel structure example of an organic EL panel module in which two power supply lines DSL are bundled with one common power supply line CDSL. In the following description, the range of the horizontal line or power supply line DSL corresponding to one common power supply line CDSL is referred to as one unit.
The organic EL panel module 21 shown in FIG. 4 includes a pixel array unit 3, a signal line drive unit 23, a write control line drive unit 25, and a power supply line drive unit 27, which are drive circuits thereof.

In this way, the number of final output stage buffers used in the power supply line driving unit 27 can be halved compared to FIG. 1 simply by bundling the two power supply lines DSL into one. Accordingly, the cost of the power supply line drive unit 27 can be reduced. Of course, as the number of bundles is increased, the manufacturing cost of the power supply line driving unit 27 can be reduced.
By the way, with the increase in vertical resolution and double speed driving (higher driving frequency), measures for shortening the horizontal scanning period are required.

  For example, in the case of the pixel structure shown in FIG. 3, in order to ensure the uniformity of the screen luminance, it is necessary to correct the threshold variation of the drive transistor N2 for all the subpixels. However, when the horizontal scanning period is shortened as described above, this correction operation cannot be completed within one horizontal scanning period.

  Therefore, the organic EL panel module 21 shown in FIG. 4 employs a driving method in which the correction preparation operation and the threshold correction operation (Vth correction operation) are each divided into a plurality of times. FIG. 5 shows a driving method in which the correction preparation operation and the threshold correction operation (Vth correction operation) are each divided into three times.

  Note that FIG. 5A shows a driving waveform of the signal line DTL. FIG. 5B shows a driving waveform of the nth common power supply line CDSLn. FIG. 5C shows a drive waveform of the first write control line WSL (n, 1) of the two horizontal lines corresponding to the nth common power supply line CDSLn. FIG. 5D shows a drive waveform of the second write control line WSL (n, 2) of the two horizontal lines corresponding to the nth common power supply line CDSLn.

  FIG. 5E shows a driving waveform of the (n + 1) th common power supply line CDSLn + 1. FIG. 5F shows a drive waveform of the first write control line WSL (n + 1,1) among the two horizontal lines corresponding to the (n + 1) th common power supply line CDSLn + 1. FIG. 5G shows a drive waveform of the second write control line WSL (n + 1,2) of the two horizontal lines corresponding to the (n + 1) th common power supply line CDSLn + 1.

  As shown in FIG. 5, the signal line driving unit 23 drives the signal line DTL with three values. The three values are a signal potential Vsig corresponding to the pixel gradation, an offset potential Vofs as a reference potential, and an initialization potential Vini. The offset potential Vofs here corresponds to the first correction potential in the claims. The initialization potential Vini corresponds to the second correction potential in the claims.

  In addition, the write control line driving unit 25 operates so as to give a write timing of the signal line potential so as to match the potential change of the signal line DTL. The power supply line drive unit 27 drives the common power supply line CDSL with the low potential Vss from the start of the non-light emission period to the completion of the correction preparatory operation. The common power supply line CDSL is driven at the high potential Vcc until the light emission period.

As described above, the correction preparation operation is performed by applying the offset potential Vofs to the gate electrode of the drive transistor N2 while the common power line CDSL is at the low potential Vss. By this operation, the source potential Vs of the drive transistor N2 gradually decreases, and decreases to the low potential Vss when the correction preparation operation is completed.
FIG. 6 shows the relationship between the drive waveform focused on the sub-pixel 11 corresponding to the first horizontal line of the n-th unit and the potential waveform of the drive transistor N2.

  FIG. 6A shows a driving waveform of the signal line DTL. FIG. 6B shows a drive waveform of the common power supply line CDSL corresponding to the subpixel 11 of interest. FIG. 6C shows a drive waveform of the write control line WSL corresponding to the subpixel 11 of interest. FIG. 6D shows the gate potential Vg of the driving transistor N2. FIG. 6E shows the source potential Vs of the driving transistor N2.

  Note that when the correction preparatory operation is completed, the gate potential Vg of the drive transistor N2 is the initialization potential Vini, and the source potential Vs is the low potential Vss. Therefore, the gate-source voltage Vgs of the driving transistor N2 is given by Vini−Vss.

Note that Vini−Vss is determined to be smaller than the threshold voltage Vth of the drive transistor N2.
Therefore, even if the common power supply line CDSL rises to the high potential Vcc after completing the correction preparation, the cut-off state of the drive transistor N2 continues. That is, no drive current flows through the drive transistor N2. As a result, even when the common power supply line CDSL is at the high potential Vcc, the operating point of the drive transistor N2 maintains the state at the time when the correction preparation is completed until the threshold correction operation is started.

  Strictly speaking, as shown in FIG. 7, there is a leakage current in the sub-pixel. For example, there is an off-leakage current of the driving transistor N2 and an off-leakage current of the organic EL element OLED. For this reason, when the waiting time T from the completion of correction preparation to the start of the threshold value correction operation becomes longer, the amount of off-leakage current flowing during that time changes, and the operating point of the drive transistor N2 changes gradually.

In addition, as shown in FIG. 8, the change in the amount of leakage current has a non-linear characteristic that changes more greatly as the waiting time T is shorter.
For this reason, if there is a large difference in the amount of leakage current between two horizontal lines corresponding to the same common power supply line CDSL, a difference in luminance is caused even in the same pixel gradation due to a difference in operating point of the drive transistor N2. There is a possibility of being visually recognized.

In addition, the difference in leakage current increases as the number of power supply lines DSL bundled with one common power supply line CDSL increases.
FIG. 9 shows the relationship between the waiting times T1 to T30 until the threshold value correcting operation for each horizontal line is started when the number of power supply lines DSL bundled with one common power supply line CDSL is 30.

  Note that FIG. 9A shows a part of the driving waveform of the nth common power supply line CDSL. 9B1 to 9B30 show write control lines WSL (n, 1) to WSL (n, corresponding to 30 power supply lines DSL bundled with the nth common power supply line CDSLn. 30) shows a driving waveform.

  As shown in FIG. 9, when 30 power supply lines DSL are bundled, the time difference of the waiting time until the threshold value correction operation starts in the first line and the last line among the 30 power supply lines DSL is 29 in the horizontal scanning period. It will be minutes. Of course, it goes without saying that this time difference increases as the number of power supply lines DSL to be bundled increases.

  FIG. 10 shows the relationship recognized between the waiting time difference and the leakage current amount. The horizontal axis is the waiting time, and the vertical axis is the leakage current amount. As shown in FIG. 10, there is a non-linear relationship between the waiting time and the amount of leak current, and there is a relationship in which the change in the amount of leak current is larger as the waiting time is shorter. Accordingly, as shown by the thick line in the figure, when the waiting time is set short, the difference between the first leakage current amount and the thirty leakage current amount becomes very large.

It can be easily imagined that when the difference in the leakage current amount at the start of the threshold value correction operation becomes so large between the horizontal lines, the difference in the operating point of the drive transistor N2 also becomes large.
Actually, paying attention to the waiting time T1 (ms) for the first horizontal line corresponding to the first row in the unit, and measuring the maximum luminance difference in the unit, the relationship shown in FIG. 11 was recognized.

  In addition, the line which connected the black circle with the broken line has shown the change of the largest luminance difference in case one unit is comprised with 30 power supply lines DSL. Further, a line obtained by connecting white circles with a solid line indicates a change in the maximum luminance difference when one unit includes 60 power supply lines DSL.

The luminance difference is measured by writing the signal potential Vsig corresponding to the same pixel gradation to each horizontal line. At this time, the maximum luminance difference is given as a difference between the luminance of the first horizontal line and the luminance of the 30th horizontal line in each unit.
That is, it is obtained as the difference between the luminance of the horizontal line with the smallest leakage current and the luminance of the horizontal line with the largest leakage current.

  However, the shorter the waiting time T1, the greater the difference in brightness at both ends of the unit or at the unit boundary. For example, in the measurement result of FIG. 11, when one unit is composed of 30 horizontal lines, a luminance difference of 4% or more occurs when the waiting time T1 is 0.2 ms.

  By the way, a general human can visually recognize a luminance difference of 1%. For this reason, when the waiting time T1 (corresponding to the first horizontal line in the unit) is short, it is considered that the seam of the unit is visually recognized as a line as shown in FIG. This streak causes a significant deterioration in display quality.

  Therefore, the inventors have (a) a pixel array unit in which sub-pixels each including a current-driven self-light-emitting element and a pixel circuit that drives and controls the self-light-emitting element are arranged in a matrix; And (c) a display panel module having a power supply line drive unit that shares the drive timing of the power supply line in units of horizontal lines, and (c) a write control line drive unit that controls the write timing of the signal line potential. Proposes the following conditions.

  The pixel circuit described above includes a first thin film transistor that controls writing of a potential of a signal line to a storage capacitor, and a second thin film transistor that controls supply of a driving current based on potential information written in the storage capacitor. is doing.

In addition, the writing control line driving unit executes the following three operations before writing of the signal potential corresponding to the pixel gradation.
(A) A first correction potential is written to the gate electrode of the second thin film transistor in a state where the potential of the power supply line is maintained at a non-light emitting potential, and the voltage across the storage capacitor is set to be equal to or higher than the threshold voltage of the second thin film transistor. First operation to widen (b) The potential applied to the gate electrode of the second thin film transistor is switched from the first correction potential to the second correction potential while the potential of the power supply line is maintained at the non-light-emitting potential, Second operation for forcibly controlling the thin film transistor in the off state (c) Waiting for a certain period to elapse after the power supply line is switched to the light emission potential in a state in which the second thin film transistor is in the off control. Third operation for starting writing of the first correction potential in order from the first row among a plurality of horizontal lines corresponding to the power supply line having a common timing. The period is set after the time when the luminance difference between the luminance level of the first row and the luminance level of the last row becomes less than 1% when the same pixel gradation is controlled for all of the plurality of horizontal lines.

The invention can also be realized as a semiconductor integrated circuit incorporating the above-described write control line driving unit.
The invention can also be realized as an electronic device equipped with the display panel module described above. Here, the electronic device includes a display panel module, a system control unit that controls the operation of the entire system, and an operation input unit that receives an operation input to the system control unit.

  In the case of the invention proposed by the inventors, the drive timing is set so that the difference between the luminance levels of the first row and the last row of the plurality of horizontal lines corresponding to the power supply line with the common drive timing is 1% or less. Is set to the waiting time until the threshold value correction operation for the first row of the power supply lines that are made common is started.

  With this setting, even when the drive timings of the power supply lines are made common in units of a plurality of horizontal lines, the boundaries of the shared horizontal lines on the screen can be prevented from being visually recognized. As a result, it is possible to reduce the cost of the display panel module without sacrificing display quality.

Hereinafter, the case where the invention is applied to an active matrix driving type organic EL panel module will be described.
In addition, the well-known or well-known technique of the said technical field is applied to the part which is not illustrated or described in particular in this specification. Moreover, the form example demonstrated below is one form example of invention, Comprising: It is not limited to these.

(A) Appearance Configuration In this specification, a drive circuit (for example, a signal line drive unit, a write control line drive unit, a power supply line drive unit, etc.) manufactured as an application-specific IC is placed on the same substrate as the pixel array unit. The mounted one is called a display panel module. In this specification, a display panel module in which a pixel array portion and a driver circuit are formed over the same substrate using the same semiconductor process is also referred to as a display panel module.

FIG. 13 shows an external configuration example of the organic EL panel module. The organic EL panel module 31 has a structure in which the counter substrate 35 is bonded to the formation region of the pixel array portion of the support substrate 33.
The support substrate 33 is made of glass, plastic or other base material. The counter substrate 35 is also made of a transparent member such as glass, plastic or the like as a base material.

The counter substrate 35 is a member that seals the surface of the support substrate 33 with a sealing material interposed therebetween.
Note that the transparency of the substrate only needs to be ensured only on the light emission side, and the other substrate side may be an impermeable substrate. In addition, the organic EL panel module 31 is provided with an FPC (flexible printed circuit) 37 for inputting external signals and driving power.

(B) Form 1
(B-1) System Configuration FIG. 14 shows a system configuration example of the organic EL panel module 41 according to this embodiment. In FIG. 14, the same reference numerals are given to the portions corresponding to FIG. 4.
The organic EL panel module 41 shown in FIG. 14 includes a pixel array unit 3, a signal line driving unit 23, a writing control line driving unit 43, and a power supply line driving unit 27 that are driving circuits thereof.

(A) Pixel Array Unit Also in this embodiment, one pixel constituting the white unit is arranged in the pixel array unit 3 with a specified resolution in the vertical direction and the horizontal direction in the screen. The arrangement of the sub-pixels 11 constituting the white unit is the same as the arrangement described with reference to FIG. 2 and is configured as an aggregate of R (red) pixels 11, G (green) pixels 11, and B (blue) pixels 11. Is done.

Also in this embodiment, it is assumed that the power supply lines DSL are bundled in units of two and connected to one common power supply line CDSL. FIG. 15 shows a connection relationship between the sub-pixels 11 corresponding to two horizontal lines and the common power supply line CDSL.
Further, as shown in FIG. 16, the sub-pixel 11 includes a thin film transistor N1, a thin film transistor N2, a storage capacitor Cs that stores gradation information, and an organic EL element OLED.

(B) Configuration of Signal Line Drive Unit The signal line drive unit 23 is a circuit device that drives and controls the signal line DTL. Also in this example, the signal line drive unit 23 assumes a case where the signal line DTL is driven with three values.
FIG. 17 shows an internal configuration example of the signal line driving unit 23. The signal line drive unit 23 includes a shift register 51, a latch unit 53, a digital / analog conversion unit 55, a buffer circuit 57, and a selector 59.
The shift register 51 is a circuit device that provides the capture timing of the pixel data Din based on the clock signal CK.

The latch unit 53 is a storage circuit that captures the pixel data Din into the corresponding storage area based on the timing signal supplied from the shift register 51.
The digital / analog conversion circuit 55 is a circuit device that converts the pixel data Din captured by the latch unit 53 into an analog signal voltage Vsig. The conversion characteristic of the digital / analog conversion circuit 55 is defined by the H level reference potential VrefH and the L level reference potential VrefL.

The buffer circuit 57 is a circuit device that converts the signal amplitude to a signal level suitable for panel driving.
The selector 59 is a circuit device that selectively outputs any one of the signal potential Vsig corresponding to the pixel gradation, the offset potential Vofs for threshold correction, and the initialization potential Vini within one horizontal scanning period. . FIG. 18 shows an example of the output timing of each potential by the selector 59.

(C) Configuration of Power Supply Line Drive Unit The power supply line drive unit 27 in this embodiment is a circuit device that drives the power supply lines DSL for two horizontal lines at the same timing through the common power supply line CDSL. The power supply line drive unit 27 applies the low potential Vss (non-emission potential) to the supply power line CDSL only during the correction preparation operation in the non-emission period, and supplies the high potential Vcc (emission potential) during the other periods. Apply to.

FIG. 19 shows a partial configuration example constituting the output stage of the power supply line driving unit 27. The configuration shown in FIG. 19 corresponds to the nth common power supply line CDSLn. Accordingly, in the vertical direction in the screen, one output stage circuit having the configuration shown in FIG.
Note that the output stage circuit shown in FIG. 19 is an inverter circuit. In the case of FIG. 19, the CMOS circuit is realized by an N-channel thin film transistor N11 and a P-channel thin film transistor P11.

  Among these, one main electrode of the thin film transistor P11 is connected to the power supply wiring of the high potential Vcc, and the other main electrode is connected to the common power supply line CDSL. Note that one main electrode of the thin film transistor N11 is connected to the common power supply line CDSL. The other main electrode of the thin film transistor N11 is connected to a power supply wiring having a low potential Vss.

A common control signal Scnt is input to the gate electrode of the thin film transistor N11 and the gate electrode of the thin film transistor P11.
The control signal Scnt is an output pulse supplied from a shift register (not shown) located in the preceding stage. Incidentally, between adjacent units, the clock phase of the control signal Scnt is determined in such a relationship that the phase moves back and forth for two horizontal scanning periods.

  This output stage circuit controls the common power line CDSL to the high potential Vcc when the control signal Scnt is at the L level, and controls the common power line CDSL to the low potential Vss when the control signal Scnt is at the H level.

(D) Configuration of Write Control Line Drive Unit The write control line drive unit 43 is a drive device that controls line-sequential writing of signal line potentials to the sub-pixels 11 through the write control line WSL.
Also in this embodiment, the control line driving unit 43 performs the execution timing of three correction preparation operations, three threshold correction operations, and one mobility correction / signal potential writing operation for each horizontal line. specify.

The correction preparation operation is executed at the same timing for all horizontal lines in the unit. This is the same as the write control line drive unit 25 described above.
A characteristic point of this embodiment is that the threshold correction operation for the first horizontal line (first line) starts from the timing when the potential of the common power supply line CDSL rises to the light emission potential (high potential Vcc) after the completion of the correction preparation operation. This is a method of determining the waiting time T1 until it is performed.

  Specifically, the waiting time T1 is set after the timing at which the difference between the first leak current amount and the second leak current amount flowing until the threshold correction operation starts becomes substantially the same. In other words, the waiting time T1 is set after the timing at which the operating points of the first and second drive transistors N2 become substantially the same when the threshold value correction operation starts for each horizontal line.

  More specifically, when the same pixel gradation is written in the first and second lines in the unit, the timing at which the difference between the luminance levels becomes 1% or less is specified from the measurement result, and the range that satisfies the condition The waiting time T1 is set at an optimal time.

  FIG. 20 shows a setting image of the waiting time T1 unique to this embodiment. For comparison with FIG. 10, FIG. 20 shows a case where the number of horizontal lines constituting the unit is 30. In the case of this embodiment, the range indicated by the thick line in FIG. 20 is set as the usage range of waiting times T1 to T30. As can be seen from FIG. 20, the difference between the leakage current amount at the time T1 of the first horizontal line in the unit and the leakage current amount at the time T30 of the 30th horizontal line is different from that in FIG. And it is very small.

  If the difference in the leakage current amount is small in this way, the operating point of the driving transistor N2 at the start of the threshold correction operation is almost the same or very small in the first horizontal line and the thirty horizontal line. Easy to predict. However, even if the difference in operating point is reduced, it cannot be said that the conventional problem is solved if the luminance difference on the screen is visually recognized.

  Therefore, attention is paid to the measurement result of the in-unit luminance difference shown in FIG. In the case of FIG. 11, when one unit is composed of 30 horizontal lines, if the first waiting time T1 is 2.2 ms or more, the luminance difference between the first and 30th may be within 1%. I understand.

  Therefore, in this case, the waiting time is 2.2 ms or more, and the first threshold correction operation may be set to start within the timing range in which the threshold correction operation can be arranged. The start timing of the second and subsequent threshold correction operations is set to a timing delayed by one horizontal scanning period with respect to the start point of the first threshold correction operation.

  FIG. 21 also shows an example of threshold correction operation performed by the write control line drive unit 43 when the number of power supply lines DSL bundled with one common power supply line CDSL is 30. FIG. 21A shows a part of the driving waveform of the nth common power supply line CDSL. 21B1 to FIG. 21B30 illustrate write control lines WSL (n, 1) to WSL (n, corresponding to 30 power supply lines DSL bundled with the nth common power supply line CDSL. 30) shows a driving waveform.

  As can be seen from comparison with FIG. 9, in the case of FIG. 21, the waiting time until the threshold value correction operation of the write control line WSL (n, 1) corresponding to the first horizontal line in the unit is started. T1 is long. Of course, the second to thirty horizontal lines are started with a delay of one horizontal scanning period from the execution of the threshold correction operation of the previous row.

Therefore, as shown in FIG. 21, the time difference from the execution of the threshold correction operation for the first horizontal line to the execution of the threshold correction operation for the 30th horizontal line is the same as in FIG. That is, it corresponds to 29 horizontal scanning periods.
Note that the write control line drive unit 43 instructs the execution timing of the mobility correction / signal potential writing operation when these threshold correction operations are completed.

(B-2) Overview of Drive Operation Hereinafter, a drive operation example of the organic EL panel module 41 according to this embodiment will be described.
FIG. 22 shows a change in internal potential when focusing on a certain sub-pixel 11 constituting the pixel array unit 3. FIG. 22A shows a driving waveform of the signal line DTL. FIG. 22B shows a driving waveform of the nth (nth unit) common power supply line. FIG. 22C shows a drive waveform of the write control line WSL (n, 1) corresponding to the first of the n-th unit. FIG. 22D shows a drive waveform of the write control line WSL (n, 2) corresponding to the second of the n-th unit.

  FIG. 22E shows a drive waveform of the (n + 1) th (n + 1th) unit common power supply line. FIG. 22F shows a drive waveform of the write control line WSL (n + 1,1) corresponding to the first of the (n + 1) th unit. FIG. 22G shows a drive waveform of the write control line WSL (n + 1,2) corresponding to the second of the (n + 1) th unit.

  FIG. 23 shows the relationship between the drive waveform focused on the sub-pixel 11 corresponding to the first horizontal line of the n-th unit and the potential waveform of the drive transistor N2. FIG. 23A shows a driving waveform of the signal line DTL. FIG. 23B shows a driving waveform of the corresponding common power supply line CDSL. FIG. 23C shows a drive waveform of the write control line WSL corresponding to the subpixel 11 of interest. FIG. 23D shows the gate potential Vg of the driving transistor N2. FIG. 23E shows the source potential Vs of the driving transistor N2.

The driving operation shown in FIGS. 22 and 23 includes an extinction operation by writing offset voltage Vofs, a correction preparation operation, a threshold correction operation, a mobility correction / signal potential writing operation, and a light emission operation. The basic operation is the same as that shown in FIGS. The difference is that the waiting time T1 until the threshold correction operation for the first row (first line) of each unit is started is delayed until the change in the leakage current amount becomes small.
Hereinafter, the potential state of the sub-pixel 11 at each operation time is shown.

(B-3) Details of Drive Operation (a) Quenching Operation Also in the case of this embodiment, the high potential Vcc is applied to the common power supply line CDSL while the signal potential Vsig is written during the light emission period. The EL element OLED is turned on and the organic EL element OLED is turned off by writing the offset potential Vofs.

  FIG. 24 shows the potential state during this extinguishing operation. This extinction operation is started by turning on the sampling transistor N1 at the timing when the offset potential Vofs (black level) is applied to the signal line DTL.

  By writing the offset potential Vofs, the gate potential Vg of the drive transistor N2 changes to the offset potential Vofs. Further, the source potential of the driving transistor N2 decreases in conjunction with the gate potential Vg due to the coupling operation via the storage capacitor Cs.

At this time, the source potential Vs (FIG. 23E) of the driving transistor N2 is equal to the cathode potential Vcat.
The threshold voltage is controlled to be lower than the threshold voltage Vth (oled) of the organic EL element OLED. Further, by writing the offset potential Vofs, the gate-source voltage Vgs of the driving transistor N2 is compressed, and the driving transistor N2 automatically performs a cutoff operation.
Thus, the organic EL element OLED is turned off and changes to a state in which the organic EL element OLED is continuously turned off regardless of the potential of the power supply line DSL. This is shown in the extinction period of FIG.

(B) Correction Preparation Operation Next, the operation during the non-light emission period will be described. This operation is started by a correction preparation operation. Also in the case of this embodiment, the correction preparation operation is executed by being divided into three times.
First, in the first correction preparation operation, the write control line WSL changes to a high potential while the potential of the common power supply line CDSL is at the low potential Vss and the potential of the signal line DTL is at the offset potential Vofs. Start with.

  Thereby, as shown in FIG. 25, the offset potential Vofs is written to the gate electrode of the drive transistor N2. By this writing, the gate-source voltage Vgs of the drive transistor N2 becomes larger than the threshold voltage Vth. As a result, the driving transistor N2 changes to the on state. As a result, the source potential Vs of the drive transistor N2 starts to decrease toward the low potential Vss applied to the power supply line DSL. Of course, since the potential of the common power supply line CDSL is the low potential Vss, no current flows even when the driving transistor N2 is in the ON state.

  Incidentally, even after the first correction preparation operation is completed, the ON state of the drive transistor N2 continues. For this reason, the decrease in the source potential Vs continues. At this time, the gate potential Vg of the driving transistor N2 is in a floating state. Therefore, as the source potential Vs decreases, the gate potential Vg also decreases.

  Eventually, the second correction preparation operation is started. At this time, the gate Vg of the driving transistor N2 is again fixed to the offset potential Vofs. On the other hand, the decrease in the source potential Vs of the driving transistor N2 continues. When the second correction preparatory operation is completed, the gate potential Vg also decreases as the source potential Vs of the drive transistor N2 continues to decrease.

  Even in the third correction preparation operation, the same operation as the previous two correction preparation operations is executed. In the case of FIG. 23, during the third correction preparation operation, the source potential Vs of the drive transistor T2 converges to the low potential Vss of the power supply line DSL, and the correction preparation operation is completed. FIG. 26 shows the operation state at the time of completion.

(C) Waiting Time Operation until Start of Threshold Correction Operation By the way, when the correction preparation operation is completed, the gate-source voltage Vgs of the drive transistor T2 is wider than the threshold voltage Vth. Therefore, when the power supply line DSL is controlled to the high potential Vcc after the correction preparatory operation is finished, the drive current Ids automatically flows, and the source potential Vs of the drive transistor N2 starts to rise. Therefore, in the case of this embodiment, a method of writing the initialization potential Vini when the correction preparation operation is completed is adopted. FIG. 27 shows the operating state at this point.

  At this time, the gate-source voltage Vgs of the drive transistor T2 is Vini−Vss. As described above, the initialization potential Vini is set such that Vini−Vss is equal to or lower than the threshold voltage Vth. For this reason, the drive transistor T2 is cut off.

(D) Threshold Correction Operation Thereafter, when the power supply line DSL is switched to the high potential Vcc and the waiting time T1 determined as described above elapses, the threshold correction operation is started in order from the first horizontal line in the unit. . FIG. 28 shows the operating state at this point.

  First, when the first threshold correction operation is started, the sampling transistor N1 is controlled to be in an ON state, and the offset potential Vofs is applied to the gate electrode of the driving transistor T2. At this time, since the power supply line DSL is at the high potential Vcc, the drive current Ids starts to flow through the drive transistor N2.

The drive current Ids flows so as to charge the storage capacitor Cs and the parasitic capacitor Cel of the organic EL element OLED. By this charging, the source potential Vs of the driving transistor N2 starts to rise.
Thereafter, the sampling transistor N1 is turned off at the timing when the first threshold correction operation ends. FIG. 29 shows the operating state at this point. As shown in FIG. 29, the ON state of the drive transistor N2 continues even after the first correction operation is completed. For this reason, the rise of the source potential Vs continues.

At this time, the gate potential Vg of the driving transistor N2 is in a floating state. Therefore, as the source potential Vs increases, the gate potential Vg also increases.
Eventually, the second threshold correction operation is started. At this time, the gate Vg of the driving transistor N2 is again fixed to the offset potential Vofs. On the other hand, the rise of the source potential Vs of the drive transistor N2 continues. When the second correction operation is completed, the gate potential Vg also rises as the source potential Vs of the drive transistor N2 continues to rise.

  Even in the third threshold correction operation, the same operation as the previous two threshold correction operations is executed. That is, the threshold value correcting operation is disclosed in a state where the gate potential Vg of the driving transistor N2 is fixed to the offset potential Vofs. In the case of FIG. 23, during the third threshold correction operation, the gate-source voltage Vgs of the drive transistor T2 reaches the threshold voltage Vth, and the threshold correction operation ends at that point. As described above, even when the correction preparation operation and the threshold correction operation are executed by being divided into a plurality of times, the threshold correction operation can be normally terminated.

At this time, the anode potential Vel of the organic EL element OLED (source potential Vs of the drive transistor N2) is in a state satisfying the following equation.
Vel = Vofs−Vth ≦ Vcat + Vth (oled)
That is, the organic EL element OLED maintains a state where it is not lit.

(E) Signal potential writing and mobility correction operation Thereafter, when the signal line DTL becomes the signal potential Vsig, the sampling transistor N1 is turned on again. Of course, the high potential Vcc is applied to the power supply line DSL. FIG. 31 shows the operating state at this point.

  The signal potential Vsig is a potential corresponding to the pixel gradation. At this time, the gate potential Vg of the driving transistor N2 is controlled to the signal potential Vsig through the sampling transistor N1. On the other hand, the source potential Vs of the drive transistor N2 rises with time due to the current flowing from the power supply line DSL.

  If the source potential Vs of the drive transistor N2 does not exceed the sum of the threshold voltage Vth (oled) of the organic EL element OLED and the cathode voltage Vcat, the current of the drive transistor N2 charges the holding capacitor Cs and the parasitic capacitor Cel. used.

At this time, the threshold correction operation of the driving transistor N2 has already been completed. For this reason, the current flowing through the driving transistor N2 takes a value reflecting the mobility μ of the driving transistor N2.
That is, in the drive transistor N2 having a high mobility μ, the amount of current increases and the source potential Vs rises faster. On the other hand, in the drive transistor T2 having a low mobility μ, the amount of current is small, and the rise of the source potential Vs is also slow.

  As a result, the gate-source voltage Vgs of the driving transistor N2 is reduced to reflect the mobility μ, and after a certain time has elapsed, the gate-source voltage Vgs is obtained by completely correcting the mobility of the individual driving transistor N2. Transition to.

(F) Light Emission Operation Finally, the sampling transistor N1 is turned off to complete writing, and the organic EL element OLED starts to emit light.
At this time, the gate-source voltage Vgs of the driving transistor N2 is constant. Accordingly, the driving transistor N2 passes a constant current Ids ′ to the organic EL element OLED.

  Note that the anode potential Vel of the organic EL element OLED rises to a voltage Vx at which the drive current Ids' flows through the organic EL element OLED. Thereby, the organic EL element OLDE starts light emission. FIG. 32 shows an operation state in the pixel circuit at this point.

(B-4) Effect In this embodiment, the same pixel gradation is written for the waiting time T1 from when the power supply line DSL rises to the light emission potential until the threshold correction operation for the first row in the unit is started. It is set after the time when the luminance difference between the first row and the last row becomes 1% or less.

  As a result, even when the entire screen is displayed with the same pixel gradation, as shown in FIG. 33, the luminance difference at the joint portion of the unit can be suppressed to less than 1%. If the luminance difference is less than 1%, most humans cannot identify the luminance difference. By adopting this driving method, it is possible to increase the number of power supply lines DSL sharing the driving timing without degrading the display quality.

Thus, an organic EL panel module having high display quality and low manufacturing cost can be realized.
Further, by increasing the number of power supply lines DSL to be bundled, the number of final output stage buffers constituting the power supply line drive unit 27 can be reduced, and the manufacturing cost of the power supply line drive unit 27 can be reduced correspondingly.

  Similarly, by increasing the number of power supply lines DSL to be bundled, the number of shift stages of the shift register constituting the power supply line drive unit 27 can be reduced, and the manufacturing cost of the power supply line drive unit 27 can be reduced correspondingly. In addition, the circuit area for arranging the shift register can be reduced. This also leads to the fact that the number of output terminals can be significantly reduced when the power supply line driving unit 27 is built in a semiconductor integrated circuit.

This reduction in the number of terminals is particularly effective when a semiconductor integrated circuit incorporating a drive circuit (for example, a write control line drive unit and a power supply line drive unit) is mounted on the outer periphery of the pixel array unit 3.
For example, in the case of the panel structure shown in FIG. 1, it is necessary to arrange two control lines (write control line WSL and power supply line DSL) for each horizontal line. Therefore, as shown in FIG. 34, when the write control line drive unit 7 and the power supply line drive unit 9 are built in a semiconductor integrated circuit, a terminal (write control line terminal) having at least twice the vertical resolution. 61, a power supply drive terminal 63) needs to be arranged.

  However, in the case of the organic EL panel module having the structure according to this embodiment, as shown in FIG. 35, the number of terminals (write control line terminal 61, power supply drive terminal 63) can be greatly reduced. . From FIG. 35, it can be seen that the terminal pitch of the power supply drive terminal 63 is expanded several times the pixel pitch in the vertical direction in the screen (Y direction). This means that there is a margin in the terminal layout. Therefore, the manufacturing cost of the semiconductor integrated circuit can also be reduced.

(C) Other embodiment examples (C-1) Other setting examples of the waiting time T1 In the case of the embodiment example 1 described above, one unit has 30 horizontal lines in relation to the measurement results illustrated in FIG. In the case where the holding time T1 is set to an optimal time point of 2.2 ms or more, the case has been described. However, even when one unit is formed by two horizontal lines, an optimal waiting time T1 may be set by preparing similar measurement results in advance.

When the measurement results shown in FIG. 11 are obtained, for an organic EL panel module in which one unit is composed of 60 horizontal lines, the waiting time T1 corresponding to each unit may be set to 3 ms or more.
Of course, the number of horizontal lines constituting one unit is arbitrary, and the light emission characteristics vary depending on individual panels. Therefore, the waiting time T1 for specifying the start timing of the threshold correction operation for the first line (first line) in the unit may be optimized based on the measurement result or simulation result for each panel.

(C-2) Other Structures of Subpixel In the case of the first embodiment described above, the case where the number of thin film transistors constituting the subpixel 11 is two has been described.
However, the configuration of the sub-pixel 11 can be applied to cases other than these. For example, the number of thin film transistors may be three or more.

  In the case of the above-described embodiment, the case where the thin film transistor is an N-channel thin film transistor has been described. However, the thin film transistor may be a P-channel thin film transistor.

(C-3) Other driving operation example 1
In the case of the first form example described above, as shown in FIG. 23, the case where the ON state of the drive transistor N2 is continued during the period between the threshold value correcting operation and the threshold value correcting operation has been described.
However, when the source potential Vs rises rapidly due to the operating speed, if the ON operation of the drive transistor N2 is continued even when the threshold correction operation is interrupted, the amount of increase of the source potential Vs becomes too large, and the threshold correction operation is performed. It may not end normally.

Therefore, in such a case, a driving method is adopted in which the driving transistor N2 is controlled to be in an off state during the interruption period of the threshold correction operation that is dividedly executed.
FIG. 36 shows an example of a driving waveform corresponding to this type of driving method. FIG. 36 shows the relationship between the drive waveform focused on the sub-pixel 11 corresponding to the first horizontal line of the n-th unit and the potential waveform of the drive transistor N2.

  FIG. 36A shows a driving waveform of the signal line DTL. FIG. 36B shows a driving waveform of the corresponding common power supply line CDSL. FIG. 36C shows a drive waveform of the write control line WSL corresponding to the subpixel 11 of interest. FIG. 36D shows the gate potential Vg of the driving transistor N2. FIG. 36E shows the source potential Vs of the driving transistor N2.

Among these, the difference between the drive waveform shown in FIG. 36 and the drive waveform shown in FIG. 23 is the control pulse length (H level period length) of the write control line WSL that specifies the period length of the threshold correction operation. In the case of FIG. 36C, the control pulse length (H level period length) applied to the write control line WSL is set to overlap with the appearance period of the initialization potential Vini applied to the signal line DTL. Yes.
FIG. 37 shows an operation state of the sub-pixel 11 in a gap period between a certain threshold value correction operation and the next threshold value correction operation.

  At this time, the gate potential Vg of the drive transistor N2 is controlled to the initialization potential Vini. On the other hand, the source potential Vs of the drive transistor N2 maintains the potential at the time when the offset potential Vofs is applied to the gate potential Vg. As a result, as shown in FIGS. 36D and 36E, the gate potential Vg of the drive transistor N2 becomes lower than the source potential Vs.

  That is, the drive transistor N2 is controlled to be in a reverse bias state. Of course, since the driving transistor N2 controlled to the reverse bias is in an OFF state, the source potential Vs of the driving transistor N2 maintains the previous potential state until the threshold value correcting operation is resumed. For this reason, when the threshold value correcting operation is resumed, the potential increase can be resumed from the source potential Vs at the time of the previous interruption.

  As a result, the source potential Vs can be increased only during the period in which the gate potential Vg of the drive transistor N2 is controlled to the offset potential Vofs. When the gate-source voltage Vgs of the drive transistor N2 reaches the threshold voltage Vth, the drive transistor N2 is automatically cut off. For this reason, even when the current driving capability of the driving transistor N2 is high, the threshold value correcting operation can be normally terminated.

(C-4) Other driving operation example 2
In the description of the first embodiment described above, the case where the correction preparation operation and the threshold value correction operation are executed in three divided portions has been described.
However, the present invention can be applied to the case where each operation is executed only once. Even when each operation is divided into a plurality of times, the number of divisions is not limited to two.

(C-5) Product Example (a) System Configuration In the above description, the panel structure and driving method of the organic EL panel module alone have been described. However, the organic EL panel module described above is also distributed in the form of products mounted on various electronic devices. Examples of mounting on other electronic devices are shown below.

  FIG. 38 shows a conceptual configuration example of the electronic device 71. The electronic device 71 includes a display panel module 73 on which the drive circuit described above is mounted, a system control unit 75, and an operation input unit 77. The processing content executed by the system control unit 75 varies depending on the product form of the electronic device 71. The operation input unit 77 is a device that receives an operation input to the system control unit 75. For the operation input unit 77, for example, a switch, a button, other mechanical interfaces, a graphic interface, or the like is used.

(B) Specific Example FIG. 39 shows an example of an external appearance when the electronic device is a television receiver. The television receiver 81 has a structure in which a display screen 85 is arranged in front of the housing 83. The portion of the display screen 85 here corresponds to the organic EL panel module described in the embodiment.

  Also, for example, a digital camera is assumed as this type of electronic apparatus. FIG. 40 shows an example of the appearance of the digital camera 91. FIG. 40A shows an example of the appearance on the front side (subject side), and FIG. 40B shows an example of the appearance on the back side (photographer side).

The digital camera 91 includes a protective cover 93 that slides in the direction of the arrow in the drawing, an imaging lens unit 95, a display screen 97, a control switch 99, and a shutter button 101. Of these, the display screen 97 corresponds to the organic EL panel module described in the embodiment.
In addition, for example, a video camera is assumed as this type of electronic apparatus. FIG. 41 shows an appearance example of the video camera 111.

  The video camera 111 includes an imaging lens 115 that images a subject in front of the main body 113, a shooting start / stop switch 117, and a display screen 119. Among these, the display screen 119 corresponds to the organic EL panel module described in the embodiment.

  Moreover, for example, a portable terminal device is assumed as this type of electronic apparatus. FIG. 42 shows an example of the appearance of a mobile phone 121 as a mobile terminal device. The cellular phone 121 illustrated in FIG. 42 is a foldable type, and FIG. 42A illustrates an appearance example in a state where the housing is opened, and FIG. 42B illustrates an appearance example in a state where the housing is folded.

  The mobile phone 121 includes an upper housing 123, a lower housing 125, a connecting portion (in this example, a hinge portion) 127, a display screen 129, an auxiliary display screen 131, a picture light 133, and an imaging lens 135. Among these, the display screen 129 and the auxiliary display screen 131 correspond to the organic EL panel module described in the embodiment.

Also, for example, a computer is assumed as this type of electronic apparatus. FIG. 43 shows an example of the appearance of the notebook computer 141.
The notebook computer 141 includes a lower housing 143, an upper housing 145, a keyboard 147, and a display screen 149. Among these, the display screen 149 corresponds to the organic EL panel module described in the embodiment.
In addition to these, an audio playback device, a game machine, an electronic book, an electronic dictionary, and the like are assumed as electronic devices.

(C-6) Other Display Device Examples In the above-described embodiments, the case where the invention is applied to an organic EL panel module has been described.
However, the configuration of the power supply circuit described above can also be applied to other self-luminous display panel modules.
For example, the present invention can be applied to a display device in which LEDs are arranged in a matrix or a display panel module in which light emitting elements having a diode structure are arranged on a screen. For example, it can be applied to an inorganic EL panel.

(C-7) Others Various modifications can be considered for the above-described embodiments within the scope of the gist of the invention. Various modifications and applications created or combined based on the description of the present specification are also conceivable.

It is a figure explaining the system structural example of an organic electroluminescent panel module. It is a figure explaining a pixel arrangement. It is a figure explaining the pixel structure example of a sub pixel. It is a figure explaining the system structure of an organic electroluminescent panel module. It is a figure explaining the phase relationship of the drive waveform of a write control line. It is a figure which shows the relationship between the drive waveform in a sub pixel, and an electrical potential state. It is a figure explaining the leakage current which exists when the correction | amendment preparation operation is completed. It is a figure which shows the time-dependent change of leak current amount. It is a figure explaining the relationship of the waiting time in a unit. It is a figure explaining the leakage current distribution in the unit by the difference at the time of threshold value operation start. It is a figure explaining the relationship between the waiting time of the first line in a unit and the maximum luminance difference generated in the unit. It is a figure which shows the example of a display screen in case the waiting time of the first line is short. It is a figure which shows the example of an external appearance of a display panel. It is a figure explaining the system structural example of an organic electroluminescent panel module (form example). It is a figure explaining pixel arrangement (form example). It is a figure explaining the pixel structure example of a sub pixel (form example). It is a figure which shows the circuit structural example of a signal line drive part. It is a figure which shows the drive waveform example of a signal line. It is a figure which shows the circuit structural example used for the output stage of a power supply line drive part. It is a figure explaining the leakage current distribution in the unit by the difference at the time of threshold value operation start (form example). It is a figure explaining the relationship of the waiting time in a unit (form example). It is a figure explaining the phase relationship of the drive waveform of a write control line (form example). It is a figure which shows the relationship between the drive waveform in a sub pixel, and a potential state (form example). It is a figure which shows the equivalent circuit of the sub pixel at the time of light extinction operation | movement. It is a figure which shows the equivalent circuit of the sub pixel at the time of the start of correction | amendment preparation operation. It is a figure which shows the equivalent circuit of the sub pixel at the time of completion | finish of correction | amendment preparation operation | movement. It is a figure which shows the equivalent circuit of a sub pixel in the waiting time from completion of correction | amendment preparation operation | movement to the start of threshold value correction | amendment operation | movement. It is a figure which shows the equivalent circuit of the sub pixel at the time of the start of threshold value correction operation. It is a figure which shows the equivalent circuit of the sub pixel immediately after the threshold value correction operation is interrupted. It is a figure which shows the equivalent circuit of the sub pixel in the time of complete | finishing threshold value correction | amendment operation | movement. It is a figure which shows the equivalent circuit of a sub pixel at the time of signal potential writing and mobility correction | amendment operation | movement. It is a figure which shows the equivalent circuit of the sub pixel after light emission start. It is a figure explaining the example of a display screen to which the drive method concerning a form example is applied. It is a figure explaining the connection relation of a wiring structure and a terminal when not making the drive timing of a power supply line common. It is a figure explaining the connection relation of the wiring structure in the case of making the drive timing of a power supply line common, and a terminal. It is a figure explaining the other example of a drive of threshold value correction operation. It is a figure which shows the equivalent circuit of the sub pixel immediately after the threshold value correction operation is interrupted. It is a figure which shows the example of a conceptual structure of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device. It is a figure which shows the example of goods of an electronic device.

Explanation of symbols

3 pixel array unit 11 sub pixel 23 signal line drive unit 27 power supply line drive unit 41 organic EL panel module 43 write control line drive unit

Claims (3)

A pixel array unit in which sub-pixels configured by current-driven self-luminous elements and pixel circuits that drive and control the self-luminous elements are arranged in a matrix;
A power line drive unit that shares the drive timing of the power line in units of horizontal lines of a plurality of rows;
A display panel module having a write control line drive unit for controlling the write timing of the signal line potential,
The pixel circuit includes:
A first thin film transistor that controls writing of the potential of the signal line to the storage capacitor; and a second thin film transistor that controls supply of a drive current based on potential information written to the storage capacitor;
The write control line drive unit
Before writing the signal potential according to the pixel gradation,
A first correction potential is written to the gate electrode of the second thin film transistor in a state where the potential of the power supply line is maintained at a non-light-emitting potential, and the voltage across the storage capacitor is set to be equal to or higher than the threshold voltage of the second thin film transistor. A first action to spread,
The potential applied to the gate electrode of the second thin film transistor is switched from the first correction potential to the second correction potential while the potential of the power supply line is maintained at a non-light-emitting potential, thereby forcing the second thin film transistor. A second operation for controlling to an off state;
In a state where the second thin film transistor is controlled to be off, a plurality of horizontal lines corresponding to the power supply lines with common drive timings are waited for a certain period of time after the power supply line is switched to the light emission potential. In the third operation of starting writing the first correction potential in order from the first row of the lines, the fixed period is controlled to the same pixel gradation in all of the horizontal lines of the plurality of rows. And a third operation set after the time point when the difference between the luminance level of the first row and the luminance level of the last row is less than 1%. A pixel array unit in which sub-pixels composed of current-driven self-light-emitting elements and pixel circuits that drive and control the self-light-emitting elements are arranged in a matrix, and the driving timing of the power supply lines is a horizontal line of a plurality of rows Among the drive circuits that drive the pixel array unit that is shared in units, a semiconductor integrated circuit that includes a write control line drive unit that controls the write timing of the signal line potential,
The pixel circuit includes a first thin film transistor that controls writing of the potential of the signal line to the storage capacitor, and a second thin film transistor that controls supply of the drive current based on potential information written in the storage capacitor. In addition,
The write control line drive unit
Before writing the signal potential according to the pixel gradation,
A first correction potential is written to the gate electrode of the second thin film transistor in a state where the potential of the power supply line is maintained at a non-light-emitting potential, and the voltage across the storage capacitor is set to be equal to or higher than the threshold voltage of the second thin film transistor. A first action to spread,
The potential applied to the gate electrode of the second thin film transistor is switched from the first correction potential to the second correction potential while the potential of the power supply line is maintained at a non-light emitting potential, and the second thin film transistor is forcibly changed. A second operation for controlling to an off state;
In a state where the second thin film transistor is controlled to be off, a plurality of horizontal lines corresponding to the power supply lines with common drive timings are waited for a certain period of time after the power supply line is switched to the light emission potential. In the third operation of starting writing the first correction potential in order from the first row of the lines, the fixed period is controlled to the same pixel gradation in all of the horizontal lines of the plurality of rows. And a third operation set after the time point when the difference between the luminance level of the first row and the luminance level of the last row is less than 1%. A pixel array unit in which sub-pixels composed of current-driven self-light-emitting elements and pixel circuits that drive and control the self-light-emitting elements are arranged in a matrix, and driving timing of power supply lines in units of horizontal lines of a plurality of rows A display panel module having a power supply line drive unit that shares the same and a write control line drive unit that controls the write timing of the signal line potential;
A system controller that controls the operation of the entire system;
An operation input unit for the system control unit;
The pixel circuit includes a first thin film transistor that controls writing of the potential of the signal line to the storage capacitor, and a second thin film transistor that controls supply of the drive current based on potential information written in the storage capacitor. In addition,
The write control line drive unit
Before writing the signal potential according to the pixel gradation,
A first correction potential is written to the gate electrode of the second thin film transistor in a state where the potential of the power supply line is maintained at a non-light-emitting potential, and the voltage across the storage capacitor is set to be equal to or higher than the threshold voltage of the second thin film transistor. A first action to spread,
The potential applied to the gate electrode of the second thin film transistor is switched from the first correction potential to the second correction potential while the potential of the power supply line is maintained at a non-light emitting potential, and the second thin film transistor is forcibly changed. A second operation for controlling to an off state;
In a state where the second thin film transistor is controlled to be off, a plurality of horizontal lines corresponding to the power supply lines with common drive timings are waited for a certain period of time after the power supply line is switched to the light emission potential. In the third operation of starting writing the first correction potential in order from the first row of the lines, the fixed period is controlled to the same pixel gradation in all of the horizontal lines of the plurality of rows. An electronic device that executes a third operation that is set after the time when the difference between the luminance level of the first row and the luminance level of the last row is less than 1%.