JP2010085675A - Image display device and method for driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a common-cathode, sequential light-emitting image display device improving write efficiency, and a method for driving the image display device. <P>SOLUTION: Each pixel circuit includes: a light-emitting element OLED; a driving transistor T<SB>d</SB>for controlling a current flowing between a second terminal t12 and a third terminal t13 according to a potential difference between a first terminal t11 and the third terminal t13 connected to an anode of the light-emitting element OLED; a first capacitor element C<SB>s1</SB>for holding a threshold voltage of the driving transistor T<SB>d</SB>, a V<SB>DD</SB>line connected to the second terminal t12 and connected to a plurality of pixel circuit lines in common; and a second capacitor element C<SB>s2</SB>for holding an image signal voltage. A voltage difference between the first terminal t11 and the third terminal t13 becomes equal to the voltage obtained by combining voltages held in the first capacitor element C<SB>s1</SB>and the second capacitor element C<SB>s2</SB>during the light-emitting period of the light-emitting element OLED, and a current flows from the V<SB>DD</SB>line to the light-emitting element OLED through the driving transistor T<SB>d</SB>. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image display device such as an organic EL display and a driving method of the image display device.

  An image display device using an organic EL (Electro Luminescence) element that emits light by recombination of holes and electrons injected into a light emitting layer has been proposed. As such an image display device, for example, a pixel circuit including a thin film transistor (hereinafter referred to as “TFT”) formed of amorphous silicon, polycrystalline silicon, or the like, an organic light emitting diode, or the like is formed. An organic EL element that forms one pixel is known (for example, see Patent Document 1). The image display device described in Patent Document 1 includes a drive transistor that drives an organic EL element, a first capacitor element that holds a threshold voltage of the drive transistor, a second capacitor element that holds an image signal voltage, It has.

  The image display device described in Patent Document 1 has a common cathode type structure in which an anode electrode of an organic EL element and a source of a driving transistor are connected, and a cathode electrode of the organic EL element is common to a plurality of pixels. ing. Such an image display device has a sequential light emitting structure in which pixels arranged in a matrix form sequentially emit light for each line.

JP 2005-99715 A

By the way, in the image display device described in Patent Document 1, when the data write voltage is stored in the second capacitor element, the first capacitor element and the second capacitor element are electrically connected in series. Write efficiency for writing voltage to the second capacitor element is small. Specifically, if the capacities of the first and second capacitive elements are C _s1 and C _s2 , respectively, the write efficiency is C _s1 / (C _s1 + C _s2 ), which is inefficient.

  The present invention has been made in view of the above, and it is an object of the present invention to provide a common cathode type and sequentially light emitting type image display apparatus and driving method capable of improving writing efficiency.

An image display device according to an embodiment of the present invention is an image display device having a plurality of pixel circuits, and each of the plurality of pixel circuits is commonly connected to an anode electrode and the plurality of pixel circuits. A light emitting device having a cathode electrode, a first terminal, a second terminal, and a third terminal connected to the anode electrode, wherein the potential difference between the first terminal and the third terminal is And a driver element that controls the amount of current flowing between the second terminal and the third terminal, a first electrode, and a second electrode connected to the first terminal, A first capacitor that holds a voltage corresponding to a threshold voltage; a power supply line connected to the second terminal and commonly connected to each line of the plurality of pixel circuits; and one end connected to the first electrode. And the other end is connected to the anode electrode A second capacitive element that holds an image signal voltage corresponding to the light emission luminance of the light emitting element, and during the light emission period of the light emitting element, the voltage difference between the first terminal and the third terminal is: The voltage held by the first capacitive element and the image signal voltage held by the second capacitive element are combined, and current flows from the power line to the light emitting element through the driver element. Features.
In the image display device according to the embodiment of the invention, the second capacitor element includes the first electrode of the first capacitor element and the third terminal of the driver element during the light emission period of the light emitting element. It is characterized by being connected between.
The image display apparatus according to an embodiment of the present invention further includes an image signal line that supplies an image signal voltage to the second capacitor element, and the image signal line is electrically connected to the second capacitor element via a switching element. When the image signal line is connected to the first electrode of one capacitive element and the one end of the second capacitive element, and the image signal line supplies an image signal voltage to the second capacitive element, the first capacitive element is The driver element is connected to the image signal line.
The image display device according to an embodiment of the present invention further includes a voltage applying element connected between the power supply line and the first electrode of the first capacitive element, and the voltage applying element includes: When the threshold voltage of the driver element is detected, the first capacitor element is connected between the driver element and the power supply line.

In addition, a driving method of an image display device according to an embodiment of the present invention includes a plurality of pixel circuits arranged in a matrix, and each pixel circuit has a common anode electrode and the plurality of pixel circuits. A light emitting element having a cathode electrode to be connected, a first terminal, a second terminal, and a third terminal connected to the anode electrode, wherein the potential difference between the first terminal and the third terminal And a first capacitive element having a driver element that controls the amount of current flowing between the second terminal and the third terminal, a first electrode, and a second electrode connected to the first terminal; A second capacitance element having one end connected to the first electrode and the other end connected to the anode electrode, the driving method for an image display device comprising: The threshold voltage of the driver element is detected and is compared with the threshold voltage. A threshold voltage detecting step of holding the voltage to be held in the first capacitor element, a writing step of holding the image signal voltage corresponding to the light emission luminance of the light emitting element in the second capacitor element, the first capacitor element and the first capacitor element. Two capacitive elements are electrically connected in series, and the voltage corresponding to the threshold voltage held in the first capacitive element and the voltage of the image signal voltage held in the second capacitive element are added, A light emitting step of causing the light emitting element to emit light by applying the added voltage between the first terminal and the third terminal of the driver element.
The image display device driving method according to an embodiment of the present invention further includes a power supply line connected to the second terminal and commonly connected to each line of the plurality of pixel circuits. A voltage is applied to each line of the plurality of pixel circuits through the power line, and the light emitting element is caused to emit light for each line to which the voltage is applied.
In the image display apparatus driving method according to an embodiment of the present invention, the light emitting element emits light when current flows from the anode electrode side to the cathode electrode side, and the cathode electrode side to the anode electrode side. Includes a step of initializing a light emitting element that discharges the charge accumulated in the light emitting element after the threshold voltage detecting step and before the writing step. And

  According to the present invention, it is possible to provide a common cathode type and sequentially light emitting type image display apparatus and driving method capable of improving writing efficiency.

  Hereinafter, an image display device according to a preferred embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

  First, terms used in the following embodiments will be described. The term “electrically connected” means that one member and the other member are always connected in a conductive manner via wiring or the like, and that one member and the other member are electrically conductive. It is used in the meaning including not only the wiring etc. which have but the aspect indirectly connected by the other member. In other words, the term “electrically connected” means that one member and the other member are different depending on the state of another member (for example, a conductive state in which a current can flow between the source and the drain of the transistor). Is used in the meaning including a mode in which the wiring is conductively connected by wiring and other members.

The “gate-source voltage” means a voltage applied to the gate with respect to the source of the transistor and is appropriately expressed as “V _gs ”.

  The “threshold voltage” means a gate-source voltage that becomes a boundary when a transistor changes from an off state (a state where a drain current does not flow) to an on state (a state where a drain current flows). .

[First Embodiment]
FIG. 1 is a diagram schematically illustrating a configuration of an image display apparatus 100 according to the first embodiment. As shown in the figure, the image display device 100 includes a display panel 20 in which pixel circuits 10 to be described later are arranged in a matrix (two-dimensional plane), a control circuit 31, a power supply control circuit 32, and control lines. A drive circuit 33 and an image signal line drive circuit 34 are provided. FIG. 2 shows an example in which pixel circuits 10 for m columns and n rows are arranged in a matrix.

The display panel 20 is provided with a V _DD line 21, a T _th control line 23, a T _rst control line 24, and a scanning line 25 in the horizontal direction of the screen (the row direction in the figure). An image signal line 26 is arranged in the vertical direction of the screen (column direction in the figure). Here, the V _DD line 21 is electrically connected to the power supply control circuit 32, and the T _th control line 23, the T _rst control line 24, and the scanning line 25 are electrically connected to the control line drive circuit 33. ing. The image signal line 26 is electrically connected to the image signal line driving circuit 34. Although not shown, it is assumed that the GND line 22 serving as the ground of the display panel 20 is connected to each of the pixel circuits 10.

The control circuit 31 can be configured using a control device such as a driving IC or counter that includes an arithmetic circuit, a logic circuit, and the like, for example, and displays input image data and the image data on the display panel 20. The timing for supplying power (V _gL , V _gH , V _DD , −V _p , V _data, etc.) to be supplied from the power control circuit 32, the control line drive circuit 33 and the image signal line drive circuit 34 is controlled.

The power supply control circuit 32 can be configured using, for example, a driving IC that includes a switching element and the like. The power supply control circuit 32 controls the timing of applying the power (potential) generated inside itself to the V _DD line 21 based on the clock signal input from the control circuit 31.

The control line drive circuit 33 can be configured using, for example, a drive IC that includes a switching element and the like. The control line drive circuit 33 controls the timing of applying various control signals generated therein to the T _th control line 23, the T _rst control line 24, and the scanning line 25 based on the clock signal input from the control circuit 31. To do.

  The image signal line driving circuit 34 can be configured by using, for example, a driving IC that includes an arithmetic circuit and the like. The image signal line drive circuit 34 generates a voltage corresponding to the image signal (hereinafter referred to as an image signal voltage) based on the image signal input from the control circuit 31, and a clock signal input from the control circuit 31. Based on the above, the timing for supplying the generated image signal voltage to the image signal line 26 is controlled.

1, the V _DD line 21, the T _th control line 23, the T _rst control line 24, the scanning line 25 and the image signal line 26, the control circuit 31, the power supply control circuit 32, the control line drive circuit 33, and The layout relating to the image signal line driving circuit 34 is an example, and is not limited to these layouts. For example, in FIG. 1, the control circuit 31, the power supply control circuit 32, the control line drive circuit 33, and the image signal line drive circuit 34 are arranged outside the display panel 20, but any or all of these circuits are displayed. It is good also as a form arrange | positioned inside the panel 20. FIG.

<Configuration of pixel circuit>
FIG. 2 is a diagram showing an example of the configuration of the pixel circuit 10 (one pixel) shown in FIG. As shown in the figure, the pixel circuit 10 includes an organic EL element OLED that is a light emitting element, a drive transistor _Td that is a driver element for driving the organic EL element OLED, and a threshold voltage of the drive transistor _Td. A threshold voltage detection transistor T _th that is a threshold voltage detection element used in detection, a reset transistor T _rst as a voltage application element that controls voltage application to the first capacitor element C _s1 , and a switching element The switching transistor T _{s includes} a first capacitive element C _s1 that holds a threshold voltage as a first capacitive element, and a second capacitive element C _s2 that holds an image signal voltage as a second capacitive element. Since the organic EL element OLED functions as a capacitor when a reverse voltage is applied, this is equivalently represented as an organic EL element capacitance C _{oled in} FIG.

The drive transistor _Td has a first terminal t11, a second terminal t12, and a third terminal t13. The first terminal t11 is electrically connected to the electrode 1b of the first capacitor element C _s1 . The second terminal t12 is electrically connected to the V _DD line 21, and the third terminal t13 is electrically connected to the anode electrode of the organic EL element OLED. Here, the first terminal t11 corresponds to a gate electrode (gate), one of the second terminal t12 and the third terminal t13 corresponds to a drain electrode (drain), and the other corresponds to a source electrode (source). Note that the relative potential relationship between the second terminal t12 and the third terminal t13 varies according to each control period described later. “Drain” and “source” are defined by the conductivity type and relative potential relationship of the transistor.

  In the n-type transistor used in this embodiment, of the two terminals (that is, the second terminal t12 and the third terminal t13) arranged with the channel region interposed therebetween, the terminal on the high potential side is “drain”. ”And the terminal on the low potential side becomes“ source ”. Further, in a p-type transistor, of two terminals arranged with a channel region interposed therebetween, a low potential side terminal is a “drain” and a high potential side terminal is a “source”.

In the driving transistor _Td , the potential applied to the first terminal t11, more specifically, the voltage value applied to the gate with respect to the source (gate-source voltage) is adjusted, so that the drain and the source The amount of current flowing between them is adjusted. A state in which current can flow between the drain and source (on state) and a state in which current cannot flow (off state) are selectively set by the potential applied to the first terminal t11. .

  In the organic EL element OLED, when a potential difference equal to or higher than the conduction voltage of the organic EL element OLED is generated between the anode electrode and the cathode electrode, a current flows through the light emitter layer between the anode electrode and the cathode electrode, and the light emitter The layer emits light. Specifically, a metal such as aluminum, silver, copper, or gold, or an alloy thereof can be used as the anode electrode. As the cathode electrode, a light-transmitting conductive material such as indium tin oxide film (ITO), a material such as magnesium, silver, aluminum, or calcium can be used. Note that the light emitter layer generates light by recombination of holes and electrons injected into the light emitter layer.

  In the present embodiment, the image display device is a common cathode type. That is, an anode electrode, a light emitting layer, and a cathode electrode are sequentially formed on the pixel circuit, and the cathode electrode is an electrode common to all pixels. The common cathode type image display device in which the cathode electrode is a common electrode does not use a cutting technique for dividing the cathode electrode that is the upper electrode for each pixel as compared with the common anode type image display device. Therefore, the manufacturing process can be simplified.

  Examples of the phosphor layer include (poly) fluorene derivative (PF), (poly) paraphenylene vinylene derivative (PPV), polyphenylene derivative (PP), polyparafinylene derivative (PPP), polyvinyl carbazole (PVK), and polythiophene derivative. Polysilanes such as polymethylphenylsilane (PMPS) can be used. For the phosphor layer, a high molecular material such as a perylene dye, a coumarin dye or a rhodamine dye, or a low molecular material such as rubrene, perylene, tetraphenylbutadiene, quinacridone or Nile red is added to these materials. Can be used.

The anode electrode of the organic EL element OLED is electrically connected to the third terminal t13 of the drive transistor _Td , and the cathode electrode is electrically connected to the GND line 22. In the pixel circuit 10 used in the present embodiment, the cathode electrode of the organic EL element OLED is a common cathode type common to all the pixels constituting the image display device.

The threshold voltage detection transistor T _th has a first terminal t21, a second terminal t22, and a third terminal t23. The first terminal t21 is electrically connected to the T _th control line 23. The second terminal t22 is conductively connected to a wiring that electrically connects the first terminal t11 of the driving transistor _Td and the electrode 1b of the first capacitor element _Cs1 . The third terminal t23 is electrically connected to a wiring that electrically connects the third terminal t13 of the driving transistor _Td and the anode electrode of the organic EL element OLED. Here, the first terminal t21 corresponds to the gate electrode, one of the second terminal t22 and the third terminal t23 corresponds to the source electrode, and the other corresponds to the drain electrode. Note that the relative potential relationship between the second terminal t22 and the third terminal t23 varies according to each control period to be described later, like the drive transistor _Td .

In the threshold voltage detection transistor T _th , the potential applied to the first terminal t21, more specifically, the voltage value (gate-source voltage) applied to the gate with respect to the source is adjusted, so that the drain and The amount of current flowing between the source and the source is adjusted. The potential applied to the first terminal t21 selectively sets a state where current can flow between the drain and source (on state) and a state where current cannot flow (off state). .

Further, the threshold voltage detection transistor T _th can electrically connect the gate and the drain of the drive transistor T _d when it is turned on. Then, until the gate-source voltage of the driving transistor T _d is the threshold voltage V _th of the driving transistor T _d, a current flows to the drain from the gate of the driving transistor T _d. As a result, the threshold voltage V _th of the drive transistor T _d is detected.

That is, the threshold voltage detecting transistor T _th, by setting based on a gate-source voltage of the driving transistor T _d for each pixel in the previous emission of the organic EL element OLED to the threshold voltage V _th, the driving transistor T _d It is provided to realize a V _th compensation function that compensates for variations in the threshold voltage V _th . Note that when the gate-source voltage of the drive transistor T _d becomes the threshold voltage V _th , no current flows through the drive transistor T _d , so that the gate-source voltage at this time, that is, V _th is the first capacitance. _Applied to element C _s1 .

Reset transistor T _rst has a first terminal t31, and a second terminal t32 and the third terminal t33. The first terminal t31 is T _rst control line 24 is electrically connected to the second terminal t32 is electrically connected to the V _DD line 21. The third terminal t33 is conductively connected to a wiring that electrically connects the third terminal t43 of the switching transistor T _s and the electrode 1a of the first capacitor element C _s1 . The first terminal t31 corresponds to the gate electrode, the second terminal t32 corresponds to the drain electrode, and the third terminal t33 corresponds to the source electrode.

In the reset transistor T _rst , the potential applied to the first terminal t31, more specifically, the voltage value (gate-source voltage) applied between the first terminal t31 and the third terminal t33 is adjusted. Thus, the amount of current flowing between the drain and the source is adjusted. Then, a state in which current can flow between the drain and source (on state) and a state in which current cannot flow (off state) are selectively set by the potential applied to the first terminal t31. .

In addition, the reset transistor T _rst applies a predetermined potential to the electrode 1a of the first capacitor element C _s1 when the transistor T _rst is turned on, so that a threshold voltage is applied to the first capacitor element C _s1. .

The switching transistor T _s has a first terminal t41, a second terminal t42, and a third terminal t43. The first terminal t41 is electrically connected to the scanning line 25, and the second terminal t42 is electrically connected to the image signal line 26. The third terminal t43 is conductively connected to a wiring that electrically connects the third terminal t33 of the reset transistor T _rst and the electrode 1a of the first capacitor element C _s1 . The first terminal t41 corresponds to the gate electrode, the second terminal t42 corresponds to the drain electrode, and the third terminal t43 corresponds to the source electrode.

In the switching transistor T _s , the potential applied to the first terminal t41, more specifically, the voltage value (gate-source voltage) applied between the first terminal t41 and the third terminal t43 is adjusted. Thus, the amount of current flowing between the drain and the source is adjusted. A state in which current can flow between the drain and source (on state) and a state in which current cannot flow (off state) are selectively set by the potential applied to the first terminal t41. .

Further, when the switching transistor T _s is turned on and an image signal voltage is supplied to the image signal line 26, the image signal voltage is applied to the second capacitor element C _s2 .

The first capacitor element C _s1 has a function of holding a charge amount corresponding to the threshold voltage V _th of the drive transistor T _d during a V _th detection period described later. Note that one electrode 1a of the first capacitor element C _s1 is electrically connected to the third terminal t43 of the switching transistor T _s . The other electrode 1b is electrically connected to the first terminal t11 (gate) of the drive transistor _Td .

The second capacitor element C _s2 has a function of holding a charge amount corresponding to the image signal voltage during a writing period to be described later. Note that one electrode 2a of the second capacitive element C _s2 is conductively connected to a wiring that electrically connects the third terminal t43 of the switching transistor T _s and the electrode 1a of the first capacitive element C _s1. Has been. The other electrode 2b is connected to a wiring that electrically connects the third terminal t13 of the drive transistor _Td and the anode electrode of the organic EL element OLED so as to be conductive.

The drive transistor T _d , threshold voltage detection transistor T _th , reset transistor T _rst, and switching transistor T _s described above are configured by, for example, TFTs. In each drawing referred to below, the type (n-type or p-type) of the TFT channel is not clearly shown, but it is either n-type or p-type. In this embodiment, the n-type is used. This TFT is used.

<Operation of pixel circuit>
Next, the operation of the pixel circuit 10 will be described with reference to FIGS. Note that the operation of the pixel circuit 10 described below is realized by the control of the drive control unit (the control circuit 31, the power supply control circuit 32, the control line drive circuit 33, and the image signal line drive circuit 34) illustrated in FIG. Is. In FIGS. 3 to 9, portions where no current flows are indicated by dotted lines.

  FIG. 3 is a timing chart for explaining a driving method of the pixel circuit 10 and shows a signal waveform (driving waveform) when the organic EL element OLED emits light sequentially by the light emission method. Here, the sequential light emission method refers to writing control of an image signal voltage for each pixel circuit for each frame and light emission control of each pixel circuit for each group of pixel circuits commonly connected to the same control line or power supply line ( (For example, every row, every column, etc.) In the present embodiment, it is assumed that writing control and light emission control are performed for each row of the display panel 20 shown in FIG.

In FIG. 3, “nth row” and “n + 1th row” indicate row numbers on the display panel 20 shown in FIG. In the sequence for each row, the cycle for each row in which the six control periods of the light emission stop period, the reset period, the V _th detection period, the OLED initialization period, the writing period, and the light emission period are one cycle is shifted in time. However, the operation of each pixel circuit group in the period of one cycle is the same in each row. Therefore, in the following description, the operation will be described focusing on the pixel circuit group in the nth row. Note that the GND line 22 common to all the pixel circuits is always at zero potential (0 V), and thus description thereof is omitted as appropriate.

<Light emission stop period>
FIG. 4 is a diagram illustrating an operation state of the pixel circuit 10 during the light emission stop period. In the light emission stop period, as shown in FIG. 3, the V _DD line 21 is zero potential (0 V), the T _th control line 23 is low potential (V _gL ), the T _rst control line 24 is low potential (V _gL ), The scanning line 25 is set to a low potential (V _gL ), and the image signal line 26 is set to a zero potential (0 V). By this control, as shown in FIG. 4, the threshold voltage detection transistor T _th is turned off, the reset transistor T _rst is turned off, and the switching transistor T _s is turned off.

When the V _DD line 21 becomes zero potential, the anode potential of the organic EL element OLED takes a positive value near the conduction voltage of the organic EL element OLED. At this time, charges corresponding to the threshold voltage V _th of the drive transistor T _d are accumulated in the first capacitor element C _s1 during the V _th detection period for the previous frame. In addition, the charge of the image signal voltage V _data ′ is accumulated in the second capacitor element C _s2 during the writing period for the previous frame. Therefore, the potential (gate voltage) applied to the first terminal t11 of the drive transistor _Td is V _th + V _data ′. Here, if the image signal voltage at the 0th gradation is 0V, the gate-source voltage is equal to or higher than the threshold voltage _Vth, and thus the drive transistor _Td is turned on.

Further, since the second terminal t12 of the driving transistor _Td has a lower potential than the third terminal t13 connected to the anode of the organic EL element OLED, the second terminal t12 serves as the source, and the third terminal t13 serves as the drain. Become. At this time, since the gate-source voltage of the drive transistor T _d is at least the threshold voltage V _th or more, a current flows from the organic EL element capacitance C _oled toward the V _DD line 21, and the anode potential of the organic EL element OLED Becomes approximately 0V. Thereby, light emission of organic EL element OLED stops.

<Reset period>
FIG. 5 is a diagram illustrating an operation state of the pixel circuit 10 during the reset period. In the reset period, as shown in FIG. 3, the T _th control line 23 and the T _rst control line 24 are set to a high potential (V _gH ), the zero potential (V _gH ) of the V _DD line 21, and the low level of the scanning line 25. The potential (V _gL ) and the zero potential (0 V) of the image signal line 26 are maintained. By this control, as shown in FIG. 5, the threshold voltage detection transistor T _th is turned on and the reset transistor T _rst is turned on.

By turning on the threshold voltage detection transistor T _th and the reset transistor T _rst , charges corresponding to the threshold voltage V _th accumulated in the first capacitor element C _s1 in the light emission control of the previous frame and the second capacitor element C _s2 are applied. The charge corresponding to the stored image signal voltage V _data ′ and the charge stored in the organic EL element capacitance C _oled are combined. At this time, if the capacitance of the organic EL element capacitance C _oled is very large compared to the capacitance of the first capacitance element C _{s1 and} the capacitance of the second capacitance element C _s2 , the electric potential after the combination of the charges matches the charge. The anode potential of the previous organic EL element OLED becomes approximately 0V.

In the present embodiment, the zero potential in the V _DD line 21 and the GND line 22 is set to 0 V, but any voltage that offsets the voltage stored in the first capacitor element C _s1 (= the reference potential of the power supply line) may be used. However, the present invention is not limited to this. Further, the potential of the image signal line 26 is set to zero potential, but this may be a potential for defining luminance when the image signal has 0 gradation, that is, a reference potential of the image signal line 26. It is not limited.

<V _th detection period>
FIG. 6 is a diagram illustrating an operation state of the pixel circuit 10 during the V _th detection period. In the V _th detection period, as shown in FIG. 3, the V _DD line 21 is set to a low potential (−V _p ), the T _th control line 23 has a high potential (V _gH ), and the T _rst control line 24 has a high potential. (V _gH ), the low potential (V _gL ) of the scanning line 25, and the zero potential (0 V) of the image signal line 26 are maintained.

When the V _DD line 21 becomes −V _p , the organic EL element capacitance C _oled , the first capacitance element C _s1, and the second capacitance element C _s2 until the gate potential of the drive transistor T _d reaches “−V _p + V _th ”. The electric charge accumulated in is discharged, and a current flows through the path of the drive transistor T _d → V _DD line 21. When the gate potential of the driving transistor T _d reaches "-V _p + V _th", the driving transistor T _d is turned off, the first capacitor element C _s1, charge corresponding to the threshold voltage V _th is accumulated It becomes a state. As described above, in the V _th detection period, charges corresponding to the threshold voltage V _th of the drive transistor T _d are accumulated in the first capacitor element C _s1 , thereby compensating for variations in the threshold voltage V _{th that} are different for each pixel. The

Further, in the V _th detection period, the electrodes 1a of the first capacitive element C _s1, so are connected to the V _DD line 21 through the reset transistor T _rst, first capacitive element C _s1 is the driving transistor T _d The connection is established between the first terminal and the V _DD line 21. At this time, the first capacitive element C _s1 viewed from first terminal t11 of the driving transistor T _d is sufficiently larger than the parasitic capacitance between the first terminal t11 and the image signal line 26 of the driving transistor T _d . That is, a configuration in which the potential variation due to the parasitic capacitance of the image signal line 26 is small can be achieved. As a result, the influence of the potential fluctuation of the image signal line on which the image signal voltage of another line is written on the pixel circuit can be suppressed, and the detection operation of the threshold voltage V _th by the first capacitor element C _s1 can be performed. Therefore, the _Vth compensation accuracy can be further improved.

Further, upon detection of the threshold voltage V _th of the driving transistor, since a configuration in which the first capacitive element C _s1 is connected between the V _DD line 21 and the first terminal t11 of the driving transistor T _d, the driving transistor T _d The influence of parasitic capacitance can be reduced. That is, the potential fluctuation due to the parasitic capacitance of the drive transistor _Td can be reduced, and the influence of the image signal voltage of the previous frame can be suppressed.

By the way, when the drive transistor T _d is turned off, the anode potential of the organic EL element OLED becomes −V _p + V _th , but by adjusting V _p so that this potential does not exceed the threshold value of the organic EL element OLED. Even when V _th increases, the V _th detection operation can be performed. In order to perform V _th detection, it is necessary that the gate-source voltage of the drive transistor T _d at the start of V _th detection is greater than the threshold voltage V _th . That is, the difference between the potential of the first terminal t11 of the driving transistor _Td at the start of _Vth detection and the potential applied to the V _DD line 21 must be larger than the threshold voltage _Vth . The anode potential of the organic EL element OLED at the end of the reset period is substantially 0 V as described above. In this state, when the V _DD line 21 is set to −V _p , the V _DD line has a lower potential than the anode electrode side of the organic EL element OLED. Therefore, the drive transistor T _d connected to the anode electrode of the OLED. Is the drain, and the terminal of the drive transistor _Td connected to the V _DD line is the source. At this time, the gate-source voltage V _gs of the drive transistor T _d is V _gs = 0 − (− V _p ) = V _p . Since this must be larger than the threshold voltage V _th, it is necessary that V _p> V _th.

<OLED initialization period>
FIG. 7 is a diagram illustrating an operation state of the pixel circuit 10 during the OLED initialization period. In the OLED initialization period, as shown in FIG. 3, after the T _th control line 23 is set to a low potential (V _gL ), the V _DD line 21 is set to a zero potential (0 V) at a predetermined timing. The high potential (V _gH ) of the _Trst control line 24, the low potential (V _gL ) of the scanning line 25, and the zero potential (0 V) of the image signal line 26 are maintained. By this control, as shown in FIG. 7, the threshold voltage detection transistor T _th is turned off.

When the T _th control line 23 becomes low potential and the V _DD line 21 becomes zero potential (0 V), the threshold voltage V _th is applied to the first terminal t11 of the drive transistor T _d by the first capacitive element C _s1 , The drive transistor _Td is turned on. At this time, the potential of the second terminal t12 of the driving transistor _Td is higher than the potential of the third terminal t13. Therefore, in this OLED initialization period, the second terminal t12 serves as a drain and the third terminal t13 serves as a source. As a result, current flows from the V _DD line 21 to the organic EL element capacitance C _oled and the second capacitance element C _s2 , so that the potential across the organic EL element capacitance C _oled becomes 0 V, and the potential across the second capacitance element C _s2 is also 0V. That is, the anode potential of the organic EL element OLED is 0V.

<Writing period>
FIG. 8 is a diagram illustrating an operation state of the pixel circuit 10 during the writing period. In the writing period, as shown in FIG. 3, after the T _rst control line 24 is set to a low potential (V _gL ), the image signal voltage V _data corresponding to the image signal of the frame to be displayed is the image signal line 26. Are supplied for a predetermined period. Further, the potential of the scanning line 25 is set to a high potential (V _gH ) in synchronization with the supply timing of the image signal voltage V _data . Note that the zero potential (0 V) of the V _DD line 21 and the low potential (V _gL ) of the T _th control line 23 are maintained. By this control, as shown in FIG. 8, the reset transistor T _rst is turned off, and the switching transistor T _s is turned on while the image signal voltage V _data is supplied.

When the _Trst control line 24 becomes V _gL and the scanning line 25 becomes V _gH , the potential of the third terminal t13 of the driving transistor _Td becomes higher than the potential of the second terminal t12. Therefore, in this writing period, the second terminal t12 is a source and the third terminal t13 is a drain. A current according to V _data supplied from the image signal line 26, flows through a path of the switching transistor T _s → second capacitor element C _s2 → driving transistor T _d → V _DD line 21. As a result, the second capacitor element C _s2 accumulates charges corresponding to V _data that is the difference between the image signal voltage V _data of the image signal line 26 and the anode potential 0 V of the organic EL element OLED.

Further, the potential difference between the first terminal t11 (gate) and the second terminal t12 (source) of the drive transistor _Td at this time, that is, the gate-source voltage is the potential difference accumulated in the first capacitor element _Cs1 . And the potential difference accumulated in the second capacitor element C _s2 . Since the potential difference stored in the first capacitor element C _s1 is V _th , the gate-source voltage V _gs of the drive transistor T _d is V _gs = V _th + V _data .

In the configuration of the present embodiment, since the anode potential of the organic EL element OLED can be kept at 0 V in the preceding OLED initialization period, the organic EL element regardless of the image signal voltage written to the second capacitor element C _s2 The anode potential of the OLED does not fluctuate, and even when a relatively high voltage is written in the second capacitor element C _s2 , it is possible to suppress the gradation characteristics from becoming nonlinear.

<Light emission period>
FIG. 9 is a diagram illustrating an operation state of the pixel circuit 10 during the light emission period. In the light emission period, as shown in FIG. 3, the potential of the V _DD line 21 is set to a high potential (V _DD ), the low potential of the T _th control line 23 (V _gL ), and the low potential of the T _rst control line 24 ( V _gL), a low potential (V _gL scan lines 25), the zero potential of the image signal line 26 (0V) is maintained.

When the V _DD line 21 becomes a high potential, the potential of the second terminal t12 of the drive transistor _Td becomes higher than the potential of the third terminal t13. Therefore, in this light emission period, the second terminal t12 serves as a drain and the third terminal t13 serves as a source. As a result, the first capacitor element C _s1 that holds the threshold voltage V _th and the second capacitor element C _s2 that holds the image signal voltage V _data are connected in series, and the gate-source voltage V of the drive transistor T _{d. gs} is V _gs = V _th + V _data . As a result, the drive transistor T _d is turned on, a current corresponding to V _data flows through a path of V _DD line 21 → drive transistor T _d → organic EL element OLED → GND line 22, and the organic EL element OLED emits light.

At this time, when the organic EL element OLED emits light, the potential of the third terminal t13 (source) of the drive transistor _Td becomes the same value as the anode potential of the organic EL element OLED, and thus varies from the potential of the data writing period. become. At this time, since the gate of the drive transistor _Td is connected to the anode side of the organic EL element OLED via the first capacitor element _Cs1 and the second capacitor element _Cs2 , the gate potential is the same as that of the organic EL element OLED. It fluctuates following the fluctuation of the potential on the anode side. Therefore, the gate voltage keeps the value in the data writing period, that is, V _th + V _data .

<About writing efficiency>
As described above, in the V _th detection period, a voltage corresponding to the threshold voltage V _th of the drive transistor T _d is applied to and held in the first capacitor element C _s1 . In the writing period, the image signal supplied from the image signal line 26 is applied and held only to the second capacitor element C _s2 . In addition, during the light emission period, an addition voltage of the threshold voltage held in the first capacitor element C _s1 and the image signal voltage held in the second capacitor element C _s2 is applied to the drive transistor T _d , so that the writing efficiency is theoretically Therefore, it becomes “1”. That is, in the image display device according to the present embodiment, the writing efficiency is theoretically 100%.

As described above, according to the image display device 100 of the present embodiment, the threshold voltage V _th of the drive transistor T _d is controlled to be held in the first capacitor element C _s1 , and the image signal voltage V _data is the second value. Since control is performed so as to be held by the capacitive element C _s2 and the cathode of the organic EL element OLED is used as a common electrode, writing efficiency can be improved and the manufacture of the image display device can be facilitated. It has the effect of being able to.

Further, since the first capacitor element C _s1 is connected to the gate of the drive transistor T _d when the threshold voltage V _th is detected, the image signal is strong against parasitic capacitance and performs data write operation on other lines. It can be made less susceptible to line voltage fluctuations. Further, the threshold voltage of the drive transistor _Td can be detected regardless of the magnitude of the conduction voltage of the organic EL element OLED.

In the present embodiment, the potential of the V _DD line from the OLED initialization period to the writing period is set to zero potential (0 V), but the luminance adjustment of the organic EL element OLED is adjusted by adjusting the potential in this period. Is possible. Hereinafter, this control method will be described as a modification of the present embodiment.

FIG. 10 is a timing chart for explaining a driving method of the pixel circuit 10 according to the modification of the first embodiment. In FIG. 10, “nth row” and “n + 1th row” indicate row numbers on the display panel 20 as in FIG. In the following description, focusing on the pixel circuit group in the nth row, the operation will be described. Note that the GND line 22 common to all the pixel circuits is always at zero potential (0 V), and thus description thereof is omitted as appropriate. The operations in the light emission stop period, the reset period, and the V _th detection period are the same as those in the first embodiment described above, and thus the description thereof is omitted.

<OLED initialization period>
FIG. 11 is a diagram showing an operation state of the pixel circuit 10 during the OLED initialization period shown in FIG. In this OLED initialization period, as shown in FIG. 10, after the T _th control line 23 is set to the low potential (V _gL ), the V _DD line 21 is set to the offset potential (V _offset ) at a predetermined timing. . The high potential (V _gH ) of the _Trst control line 24, the low potential (V _gL ) of the scanning line 25, and the zero potential (0 V) of the image signal line 26 are maintained.

When the _Tth control line 23 is at a low potential and the V _DD line 21 is at an offset potential, the drive transistor _Td is turned on, so that the organic EL element capacitance C _oled is initialized to the offset potential. As a result, the anode potential of the organic EL element OLED (the potential of the third terminal t13 of the driving transistor _Td ) becomes the offset potential, so that even when a relatively high voltage is written in the subsequent writing period, The anode potential of the EL element OLED can be maintained at the offset potential.

<Writing period>
FIG. 12 is a diagram showing an operation state of the pixel circuit 10 during the writing period shown in FIG. In this writing period, as shown in FIG. 10, after the _Trst control line 24 is set to a low potential (V _gL ), the image signal voltage V _data corresponding to the image signal of the frame to be displayed is displayed on the image signal line. 26 is supplied for a predetermined period. Further, in synchronization with the supply timing of the image signal voltage V _data , the potential of the scanning line 25 is set to a high potential (V _gH ), and the switching transistor T _s is turned on. The offset potential (V _offset ) of the V _DD line 21 and the low potential (V _gL ) of the T _th control line 23 are maintained.

When the T _rst control line 24 is set to V _gL and the scanning line 25 is set to V _gH , the potential of the third terminal t13 of the driving transistor _Td becomes higher than the potential of the second terminal t12. Therefore, in this writing period, the second terminal t12 is a source and the third terminal t13 is a drain. As a result, a current corresponding to V _data supplied from the image signal line 26 flows to the V _DD line 21 through the path shown in FIG. 8, and as a result, the image of the image signal line 26 is supplied to the second capacitor element C _s2. Charge corresponding to V _data − (V _offset ), which is the difference between the signal voltage V _data and the anode potential V _offset of the organic EL element OLED, is accumulated. For example, _assuming that V _offset is 0.5V, charges corresponding to V _data − (0.5) = V _data −0.5V are accumulated. In addition, since the organic EL element OLED emits light when the potential applied to the V _DD line 21 as V _offset exceeds the conduction voltage of the organic EL element OLED, the potential may be within the range of the conduction voltage of the organic EL element OLED. preferable.

At this time, the gate potential of the drive transistor _Td is the sum of the potential difference stored in the first capacitor element C _s1 and the potential difference stored in the second capacitor element C _s2 . Since the potential difference stored in the first capacitor element C _s1 is V _th , the gate-source voltage V _gs of the drive transistor T _d is V _gs = V _th + V _data −V _offset . That is, V _gs is _offset by a value corresponding to V _offset as compared with the writing period of the first embodiment described above.

As described above, according to this modification, by setting the potential of the V _DD line 21 during the OLED initialization period and the writing period to V _offset , the gate-source voltage of the drive transistor T _d during light emission is It can be offset by -V _offset . As a result, the amount of current passing through the drive transistor _Td during the light emission period can be adjusted, so that the brightness can be adjusted. For example, when a change occurs in the luminance distribution in the display unit due to the influence of a voltage drop or the like due to the large screen of the display panel 20, the luminance distribution can be improved by adjusting the value of V _offset .

[Second Embodiment]
Next, a second embodiment of the image display device according to the present invention will be described. In addition, the same code | symbol is provided about the component similar to 1st Embodiment mentioned above, and description is abbreviate | omitted.

  FIG. 13 is a diagram schematically illustrating a configuration of an image display apparatus 200 according to the second embodiment. As shown in the figure, the image display device 200 includes a display panel 40 in which pixel circuits 11 described later are arranged in a matrix (two-dimensional plane), a control circuit 35, a booster circuit 36, and a power supply control circuit. 32, a control line drive circuit 33, and an image signal line drive circuit 34. FIG. 13 shows an example in which pixel circuits 11 for m columns and n rows are arranged in a matrix.

The display panel 40 is provided with a V _DD line 21, a T _th control line 23, a T _rst control line 24, a scanning line 25, and a V _offset line 27 in the horizontal direction of the screen (the row direction in the figure). An image signal line 26 is arranged in the vertical direction of the screen (column direction in the figure). Here, the V _offset line 27 is electrically connected to the booster circuit 36. Although not shown, it is assumed that the GND line 22 serving as the ground of the display panel 40 is connected to each pixel circuit 11.

Similar to the control circuit 31, the control circuit 35 can be configured using a control device such as a driving IC or a counter that includes an arithmetic circuit, a logic circuit, and the like. The input image data and the image data _Are displayed on the display panel 20 (V _gL , V _gH , V _DD , −V _p , V _data , V _f, etc.), power supply control circuit 32, control line drive circuit 33, image signal line drive circuit 34. And the timing supplied from the booster circuit 36 is controlled.

The booster circuit 36 can be configured using a DC / DC converter or the like, boosts the signal input from the control circuit 35 to a predetermined potential (V _f ), and applies it to the V _offset line 27.

In the configuration of FIG. 13, the V _DD line 21, GND line 22, T _th control line 23, T _rst control line 24, scanning line 25, image signal line 26 and V _offset line 27, control circuit 35, power supply control The layout relating to the circuit 32, the control line drive circuit 33, the image signal line drive circuit 34, and the booster circuit 36 is an example, and is not limited to these layouts.

<Configuration of pixel circuit>
FIG. 14 is a diagram illustrating an example of the configuration of the pixel circuit 11 (one pixel) illustrated in FIG. 13. As shown in the figure, the pixel circuit 11 includes an organic EL element OLED that is a light emitting element, a drive transistor _Td that is a driver element for driving the organic EL element OLED, and a threshold voltage that is a threshold voltage detection element. A detection transistor T _th , a reset transistor T _rst as a voltage application element that controls voltage application to the first capacitor element C _s1 , a switching transistor T _s as a switching element, and a threshold voltage as a first capacitor element A first capacitive element C _s1 to be held and a second capacitive element C _s2 to hold an image signal voltage as a second capacitive element are provided. The organic EL element OLED functions as a capacitor when a reverse voltage is applied. Therefore, in FIG. 14, this is equivalently expressed as the organic EL element capacitance C _oled .

As shown in FIG. 14, the configuration of the pixel circuit 11, the connection of the second terminal t32 of the reset transistor T _rst of the pixel circuit 10 shown in FIG. 2, is a constant potential line from V _DD line 21 The V _offset line 27 is changed.

<Operation of pixel circuit>
Next, the operation of the pixel circuit 11 will be described with reference to FIGS. 15 and 16. The driving of the pixel circuit 11 is realized by the control of the drive control unit (control circuit 35, power supply control circuit 32, control line drive circuit 33, image signal line drive circuit 34, and booster circuit 36) shown in FIG. Is.

FIG. 15 is a timing chart for explaining a driving method of the pixel circuit 11. Here, the control sequence shown in FIG. 15 shows a case where the pixel circuit groups shown in FIG. 13 are sequentially controlled to emit light by the light emission method (for each row). Note that the operations during the light emission stop period, the reset period, and the writing period are the same as those in the first embodiment described above, and thus the description thereof is omitted. Further, since the GND line 22 common to all the pixel circuits is always zero potential (0 V) and the V _offset line 27 is always V _f (for example, −V _p +1 V), description thereof will be omitted as appropriate.

FIG. 16 is a diagram showing an operation state of the pixel circuit 11 during the V _th detection period shown in FIG. In the V _th detection period, as shown in FIG. 15, the V _DD line 21 is set to a low potential (−V _p ), the T _th control line 23 has a high potential (V _gH ), and the T _rst control line 24 has a high potential. (V _gH ), the low potential (V _gL ) of the scanning line 25, and the zero potential (0 V) of the image signal line 26 are maintained.

Here, _assuming that the V _offset line 27 has a potential of V _f = −V _p + 1V, the organic EL element capacitance C _oled and the first capacitance until the gate potential of the drive transistor T _d reaches −V _p + V _th. The charges accumulated in the element C _s1 and the second capacitor element C _s2 are discharged, and a current flows through the path of the drive transistor T _d → V _DD line 21. When the gate potential of the driving transistor T _d reaches -V _p + V _th, the driving transistor T _d is turned off. At this time, the electric charge corresponding to −V _p + V _th −V _f = V _th −1 is accumulated in the first capacitive element C _s1 by the action of the V _offset line 27. That is, the first implementation described above. Compared with the V _th detection period in the embodiment, charges offset by the potential of the V _offset line 27 are accumulated.

By the way, in the modified example of the first embodiment described above, the organic EL element OLED emits light when the potential V _offset at the V _DD line 21 exceeds the conduction voltage of the organic EL element OLED. The brightness can be adjusted only within the range of the conduction voltage of the element OLED or less. However, in the configuration of the present embodiment, the amount of charge accumulated in the first capacitor element C _s1 can be adjusted using the V _offset line 27 independent of the V _DD line 21, so that the luminance can be adjusted. There is no limit. Therefore, it is possible to adjust the luminance within a larger range as compared with the modification of the first embodiment.

  The embodiment according to the present invention has been described above, but the present invention is not limited to this, and various modifications, substitutions, additions, and the like are possible without departing from the spirit of the present invention.

It is the figure which showed typically the structure of the image display apparatus which concerns on 1st Embodiment. FIG. 2 is a diagram illustrating an example of a configuration of a pixel circuit illustrated in FIG. 1. 3 is a timing chart for explaining a method of driving the pixel circuit shown in FIG. 2. FIG. 4 is a diagram illustrating an operation state of the pixel circuit during the light emission stop period illustrated in FIG. 3. FIG. 4 is a diagram illustrating an operation state of the pixel circuit during the reset period illustrated in FIG. 3. FIG. 4 is a diagram illustrating an operation state of the pixel circuit during the V _th detection period illustrated in FIG. 3. FIG. 4 is a diagram illustrating an operation state of the pixel circuit during the OLED initialization period illustrated in FIG. 3. FIG. 4 is a diagram illustrating an operation state of the pixel circuit during the writing period illustrated in FIG. 3. It is the figure which showed the operation state of the pixel circuit at the time of the light emission period shown in FIG. FIG. 10 is a sequence diagram for explaining a driving method of a pixel circuit according to a modified example of the first embodiment. It is the figure which showed the operation state of the pixel circuit at the time of the OLED initialization period shown in FIG. FIG. 11 is a diagram illustrating an operation state of the pixel circuit during the writing period illustrated in FIG. 10. It is the figure which showed typically the structure of the image display apparatus which concerns on 2nd Embodiment. It is the figure which showed an example of the structure of the pixel circuit shown in FIG. 15 is a timing chart for explaining a method of driving the pixel circuit shown in FIG. FIG. 16 is a diagram illustrating an operation state of the pixel circuit during the V _th detection period illustrated in FIG. 15.

Explanation of symbols

_{DESCRIPTION OF SYMBOLS} 100 Image display apparatus 200 Image display apparatus 10 Pixel circuit 11 Pixel circuit 20 Display panel 21 V _DD line 22 GND line 23 T _th control line 24 T _rst control line 25 Scan line 26 Image signal line 27 V _offset line 31 Control circuit 32 Power supply Control circuit 33 Control line drive circuit 34 Image signal line drive circuit 35 Control circuit 36 Booster circuit 40 Display panel C _oled organic EL element capacitance C _s1 first capacitance element C _s2 second capacitance element OLED organic EL element T _d drive transistor T _rst Reset transistor T _s Switching transistor T _th Threshold voltage detection transistor

Claims (7)

An image display device having a plurality of pixel circuits,
Each of the plurality of pixel circuits is
A light emitting element having an anode electrode and a cathode electrode commonly connected in the plurality of pixel circuits;
A first terminal; a second terminal; a third terminal connected to the anode electrode; and the second terminal and the third terminal according to a potential difference between the first terminal and the third terminal. A driver element that controls the amount of current flowing between
A first capacitive element having a first electrode and a second electrode connected to the first terminal and holding a voltage corresponding to a threshold voltage of the driver element;
A power line connected to the second terminal and commonly connected to each line of the plurality of pixel circuits;
A second capacitive element having one end connected to the first electrode and the other end connected to the anode electrode and holding an image signal voltage corresponding to the light emission luminance of the light emitting element;
With
During the light emission period of the light emitting element, the voltage difference between the first terminal and the third terminal is such that the voltage held by the first capacitive element and the image signal voltage held by the second capacitive element are And an electric current flows from the power supply line to the light emitting element through the driver element. The image display device according to claim 1,
The second capacitive element is connected between the first electrode of the first capacitive element and the third terminal of the driver element during a light emission period of the light emitting element. . The image display device according to claim 1,
An image signal line for supplying an image signal voltage to the second capacitive element;
The image signal line is electrically connected to the first electrode of the first capacitive element and the one end of the second capacitive element via a switching element,
When the image signal line supplies an image signal voltage to the second capacitor element, the first capacitor element is connected between the driver element and the image signal line. An image display device. The image display device according to claim 1,
A voltage applying element connected between the power line and the first electrode of the first capacitor;
The voltage applying element is in a state where the first capacitor element is connected between the driver element and the power supply line when detecting the threshold voltage of the driver element. Display device. It has a plurality of pixel circuits arranged in a matrix, and each pixel circuit has
A light emitting element having an anode electrode and a cathode electrode commonly connected in the plurality of pixel circuits;
A first terminal; a second terminal; a third terminal connected to the anode electrode; and the second terminal and the third terminal according to a potential difference between the first terminal and the third terminal. A driver element that controls the amount of current flowing between
A first capacitive element having a first electrode and a second electrode connected to the first terminal;
A second capacitive element having one end connected to the first electrode and the other end connected to the anode electrode;
A method of driving an image display device comprising:
For each line of the plurality of pixel circuits,
A threshold voltage detection step of detecting a threshold voltage of the driver element and holding the voltage corresponding to the threshold voltage in the first capacitor element;
A writing step of causing the second capacitor element to hold an image signal voltage corresponding to the light emission luminance of the light emitting element;
The first capacitive element and the second capacitive element are electrically connected in series, and a voltage corresponding to the threshold voltage held in the first capacitive element and the image signal held in the second capacitive element A light emitting step of causing the light emitting element to emit light by adding a voltage to the voltage and applying the added voltage between the first terminal and the third terminal of the driver element. Method for driving an image display device. In the driving method of the image display device according to claim 5,
A power line connected to the second terminal and commonly connected to each line of the plurality of pixel circuits;
In the light emitting step, a voltage is applied to each line of the plurality of pixel circuits through the power line, and the light emitting element is caused to emit light for each line to which the voltage is applied. Method. In the driving method of the image display device according to claim 5,
The light emitting element emits light when current flows from the anode electrode side to the cathode electrode side, current does not flow from the cathode electrode side to the anode electrode side, and charges are accumulated,
A driving method of an image display device, further comprising: a light emitting element initializing step of discharging charges accumulated in the light emitting element after the threshold voltage detecting step and before the writing step.

Images