JP2010080497A - Non-volatile semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device for suppressing advance of silicide formation of a lower electrode part in a selection gate transistor at the time of forming a silicide film of a control gate electrode film in a post-process and to provide a manufacturing method of the device. <P>SOLUTION: In a NAND flash memory device, a gate electrode MG of a memory cell transistor is obtained by laminating a floating gate electrode part 51, an inter-electrode insulating film 6 and a control gate electrode part 71 through a gate insulating film 4 on a silicon substrate 1. The control gate electrode part 71 is silicided after a polycrystalline silicon film is formed. A gate electrode SG of the selection gate transistor is obtained by sequentially laminating a lower electrode part 5, an inter-electrode insulating film 6, an intermediate electrode part 7, an inter-electrode insulating film 8 and an upper electrode part 9. Since silicide reaction advances in the intermediate electrode part 7 and the lower electrode part 5 through opening parts 6a and 8a at the time of siliciding the upper electrode part 9 formed of the polycrystalline silicon film, advance of silicide reaction can be stopped before it reaches the gate insulating film 4. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device in which data is electrically written and erased and has a stacked gate structure, and a method for manufacturing the same.

  In a nonvolatile semiconductor memory device typified by a NAND flash memory device, a floating gate electrode or an interelectrode insulating film is not required in other transistors as compared to a film configuration adopted as a gate electrode of a memory cell transistor. Therefore, for example, as disclosed in Patent Document 1, a configuration is adopted in which an opening is formed in the interelectrode insulating film so that the control gate electrode and the floating gate electrode are short-circuited.

  On the other hand, as the design rule becomes finer, the width dimension of the word line connecting the control gate electrodes of the memory cell transistors becomes smaller and the wiring resistance becomes larger, so that a metal silicide layer having a smaller resistance value is formed. Configuration is considered. Even in the case of forming a metal silicide layer, in order to reduce the resistance, it is considered to form a silicide by alloying a metal such as nickel (Ni) with polycrystalline silicon.

However, when the silicidation process is performed after the gate electrode is stacked and formed while adopting the configuration disclosed in Patent Document 1, it is difficult to control the progress of silicidation. When there is a part that suppresses the progress of the silicidation reaction due to the interelectrode insulating film like a memory cell transistor, it does not cause a problem as a characteristic of the element that the silicide reaction reaches the interelectrode insulating film, In the transistors other than the memory cell transistor, an opening is formed in the interelectrode insulating film, so that the silicide reaction proceeds to the polycrystalline silicon film serving as the lower floating gate electrode through the opening. There is no problem if the silicide reaction can be reliably stopped at the intermediate portion of the floating gate electrode. However, since there are no components such as a stopper, it is expected that the gate insulating film is reached in some cases. For this reason, it is conceivable that an adverse effect may occur on the characteristics of the element, such as a deterioration of the reliability of the gate oxide film and an adverse effect such as a change in threshold value of the select gate transistor.
JP 2002-176114 A

  An object of the present invention is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same, which can appropriately control the progress of silicidation even when a silicide film of a gate electrode is formed in a later step.

  One aspect of a nonvolatile semiconductor memory device according to the present invention includes a semiconductor substrate, a gate insulating film formed on an upper surface of the semiconductor substrate, a floating gate electrode portion formed on the gate insulating film, and the floating gate electrode portion. A first gate electrode formed on the first inter-electrode insulating film, a control gate electrode portion formed on the inter-electrode insulating film, and adjacent to the first gate electrode; A lower electrode part formed on the insulating film and having the same film thickness as the floating gate electrode part, and having a film thickness equal to the film thickness of the first inter-electrode insulating film formed on the lower electrode part A second inter-electrode insulating film in which a first opening is formed, and the first opening is formed on the second inter-electrode insulating film and has the same film thickness as the control gate electrode part. An intermediate electrode part connected to the lower electrode part via the intermediate electrode part A third interelectrode insulating film formed thereon and having a second opening corresponding to the first opening, and the second opening formed on the third interelectrode insulating film. A second gate electrode including an upper electrode portion connected to the intermediate electrode portion, and the control gate electrode portion, the upper electrode portion, the first opening portion of the intermediate electrode portion, and the second gate electrode The portion located between the two openings is characterized by being formed of a silicide film.

  Another embodiment of the method for manufacturing a nonvolatile semiconductor memory device of the present invention is a method for manufacturing a nonvolatile semiconductor memory device having a memory cell transistor and a select gate transistor, wherein a gate insulating film is formed on the upper surface of the semiconductor substrate, and the first Sequentially forming the polycrystalline silicon film and the processing insulating film, patterning the processing insulating film into a predetermined pattern, and using the patterned processing insulating film as a mask, the first polycrystalline silicon film, Etching the gate insulating film and the semiconductor substrate to form a first groove; and embedding the insulating film in the first groove; the height of the upper end is the height of the upper surface of the first polycrystalline silicon film; Forming an element isolation insulating film lower than the height and higher than the height of the surface of the semiconductor substrate; and after removing the processing insulating film, the first polycrystalline silicon A step of sequentially forming an interelectrode insulating film, a second polycrystalline silicon film and a silicon oxide film on the upper surface of the film and the element isolation insulating film; and a step of forming the silicon oxide film, Forming a second trench over a portion of the polycrystalline silicon film, the interelectrode insulating film, and the first polycrystalline silicon film, and filling the upper surface of the silicon oxide film and the second trench. Forming a third polycrystalline silicon film, and the third polycrystalline silicon film, the silicon oxide film, the second polycrystalline silicon film, the interelectrode insulating film, and the first polycrystalline silicon film. The film is processed to form a first gate electrode in the gate electrode formation region of the memory cell transistor and a second gate electrode in the gate electrode formation region of the selection gate transistor. Forming a first electrode, embedding and forming an interlayer insulating film between the first and second gate electrodes, the third polycrystalline silicon film and the silicon oxide film of the first gate electrode And exposing the upper surface of the second polycrystalline silicon film of the first gate electrode, siliciding the second polycrystalline silicon film of the first gate electrode, and And a step of silicidizing the third polycrystalline silicon film on the inter-electrode insulating film of the second gate electrode and in the second groove portion.

  According to the present invention, the progress of silicidation can be appropriately controlled even when the silicide film of the gate electrode is formed in a later step.

(First embodiment)
Hereinafter, a first embodiment in which the nonvolatile semiconductor memory device of the present invention is applied to a NAND flash memory device having a stacked gate structure will be described with reference to FIGS. The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

FIG. 1 is an equivalent circuit diagram showing a part of a memory cell array formed in a memory cell region of a NAND flash memory device.
In FIG. 1, the memory cell array in the memory cell region has a configuration in which a plurality of NAND cell units Su are arranged. The NAND cell unit Su includes two select gate transistors Trs1 and Trs2, and a plurality of select gate transistors Trs1 and Trs2 connected in series (for example, 8: n to the power of 2 (n is a positive number)). Memory cell transistor Trm. In the NAND cell unit Su, a plurality of memory cell transistors Trm are formed by sharing adjacent source / drain regions (see reference numeral 1a in FIG. 3).

  In FIG. 1, the memory cell transistors Trm arranged in the X direction (corresponding to the word line direction and the second direction) are commonly connected by a word line WL. Further, the select gate transistors Trs1 arranged in the X direction in FIG. 1 are commonly connected by a select gate line SGL1. Similarly, the select gate transistors Trs2 arranged in the X direction in FIG. 1 are commonly connected by a select gate line SGL2.

  A bit line contact CB is connected to the drain region of the select gate transistor Trs1. The bit line contact CB is connected to a bit line BL extending in a Y direction (bit line direction, corresponding to the first direction) orthogonal to the X direction in FIG. The select gate transistor Trs2 is connected to a source line SL extending in the X direction in FIG. 1 through a source region.

  2A is a plan view showing a layout pattern of a part of the memory cell region, and FIG. 2B is a plan view showing a layout pattern of transistors in the peripheral circuit region. First, in FIG. 2A, a plurality of element isolation insulating films 2 formed by an STI (shallow trench isolation) structure are formed on a silicon substrate 1 as a semiconductor substrate at predetermined intervals along the Y direction in FIG. As a result, the active region (element forming region) 3 is separately formed in the X direction in FIG. Word lines WL of the memory cell transistors are formed at predetermined intervals along the X direction in FIG. 2 orthogonal to the active region 3.

  A selection gate line SGL1 of a pair of selection gate transistors is formed along the X direction in FIG. Bit line contacts CB are formed in the active region 3 between the pair of select gate lines SGL1. A gate electrode MG of the memory cell transistor is formed on the active region 3 intersecting with the word line WL, and a gate electrode SG of the selection gate transistor is formed on the active region 3 intersecting with the selection gate line SGL1.

  FIG. 3A is a cross-sectional view taken along the section line AA in FIG. 2, along the direction in which the word line WL is formed in the active region 3 of the memory cell transistor in the memory cell region (Y direction in FIG. 2). FIG. FIG. 3B is a cross-sectional view taken along the cutting line BB in FIG. 2 and is a cross-sectional view taken along the direction in which the gate electrode of the select gate transistor is formed. FIG. 3C is a cross-sectional view taken along the section line C-C in FIG. 2, and is a cross-sectional view along the formation direction of the gate electrode of the memory cell transistor.

  3A, in the surface layer portion of the silicon substrate 1, a plurality of active regions 3 which are element formation regions are separately formed by the element isolation insulating film 2 as described above. A gate insulating film 4 is formed on the upper surface of the active region 3, and a gate electrode MG of a memory cell transistor and a gate electrode SG of a selection gate transistor, which are first gate electrodes, are formed on the active region 3 at a predetermined interval. ing.

  The gate electrode MG has a floating gate electrode portion 51 composed of a polycrystalline silicon film as a floating gate electrode film from below, an interelectrode insulating film 6, and a control gate electrode portion 71 composed of a silicide film as a control gate electrode film. It is the structure which was made. Note that the silicide film constituting the control gate electrode portion 71 is formed by an alloying reaction (silicidation) of a polycrystalline silicon film with a metal film.

  The gate electrode SG includes a lower electrode portion 5 formed on the gate insulating film 4, an interelectrode insulating film 6 formed on the lower electrode portion, an intermediate electrode portion 7 formed on the interelectrode insulating film 6, an intermediate electrode The electrode electrode insulating film 8 formed on the part 7 and the upper electrode part 9 formed on the interelectrode insulating film 8 are formed. The lower electrode portion 5 is composed of a polycrystalline silicon film 5a and a silicide film 5b. The interelectrode insulating film 6 is composed of an ONO (oxide-nitride-oxide) film. The intermediate electrode portion 7 is composed of a polycrystalline silicon film 7a and a silicide film 7b. The interelectrode insulating film 8 is composed of a silicon oxide film. The upper electrode portion 9 is composed of a silicide film 9. A groove V is formed in the center of the gate electrode SG along the direction of the word line WL, so that an opening 6a is formed in the center of the interelectrode insulating film 6 and an opening 6a is formed in the center of the interelectrode insulating film 8. Correspondingly, an opening 8a is formed.

  The silicide film 5b of the lower electrode portion 5 is formed with a predetermined film thickness in a portion in contact with the opening 6a. The silicide film 5b is not preferable in terms of electrical characteristics when formed to a thickness that reaches the gate insulating film 4, but the thickness is not particularly limited as long as the thickness does not reach the gate insulating film 4. Absent. The lower electrode portion 5 may have a configuration in which the silicide film 5b is not formed.

  The silicide film 7b of the intermediate electrode portion 7 is formed in a region between the opening 6a and the opening 8a. The silicide film 7b is formed so that the width dimension of the upper surface on the interelectrode insulating film 8 side is larger than the width dimension of the bottom surface on the interelectrode insulating film 6 side. That is, the silicide film 7b is formed to have a narrow width in the lower portion near the interelectrode insulating film 6 and gradually spreads upward, and a portion in contact with the interelectrode insulating film 8 is formed to have the widest width. The shape of the silicide film 7b is not limited to the illustrated shape described above, and is silicided in the manufacturing process. The thickness or shape of the silicide film is not limited, and the intermediate electrode portion 7 is entirely formed of the silicide film 7b. It may be formed as.

  The height of the upper surface of the upper electrode portion 9 constituting the gate electrode SG with respect to the surface of the silicon substrate 1 is formed to be higher than the height of the upper surface of the control gate electrode portion 7 constituting the gate electrode MG. That is, the gate electrode SG is higher than the gate electrode MG by the amount that the interelectrode insulating film 8 and the upper electrode portion 9 are stacked.

  An interlayer insulating film 10 made of a silicon oxide film or the like is buried between the gate electrode MG and the gate electrode SG. In the state shown in the drawing, the height of the upper surface of the interlayer insulating film 10 is lower than the upper surface and higher than the lower surface of the upper electrode portion 9 of the gate electrode SG, and the control gate electrode portion of the gate electrode MG because of the relationship shown in the middle of processing. It is formed to be higher than the height of the upper surface of 71.

  Next, in FIGS. 3B and 3C, the silicon substrate 1 has a plurality of trenches formed in the surface layer portion, and an element isolation insulating film 2 made of a silicon oxide film or the like is embedded in the trench. The active region 3 described above is isolated and formed by the element isolation insulating film 2. A gate insulating film 4 is formed on the upper surface of each active region 3, and a lower electrode portion 5 of the gate electrode SG and a floating gate electrode portion 51 of the gate electrode MG are formed on the upper surface.

  As shown in FIG. 3B, in the gate electrode SG portion, the lower electrode portion 5 is formed to be approximately the same as the height of the element isolation insulating film 2, and the upper portion is a silicide film 5b. The interelectrode insulating film 6 is formed only on the upper surface of the element isolation insulating film 2 and is in a state of being divided at the active region 3 portion. An upper electrode portion 9 made of a silicide film is laminated on the upper surfaces of the silicide film 5 b and the interelectrode insulating film 6.

  The above configuration is shown in the middle of the manufacturing process. Actually, after this, the wafer process is completed through various processes such as a contact formation process and an interlayer wiring process, and then cut into chips. A NAND flash memory device is formed.

  Next, a manufacturing process for manufacturing the above configuration will be schematically described with reference to FIGS. Each of FIGS. 4A to 13C (a) to (c) shows the same part as FIGS. 3A to 3C.

  First, as shown in FIG. 4, a gate insulating film 4 having a thickness of about 10 nm is formed on the upper surface of the silicon substrate 1 by using a thermal oxidation technique. Next, a polycrystalline silicon film 5a to which phosphorus (P) is added as an impurity is deposited with a film thickness of 70 to 80 nm by using a low pressure CVD (chemical vapor deposition) method. The polycrystalline silicon film 5a is formed as a floating gate electrode portion of the gate electrode MG and a lower electrode portion of the gate electrode SG. Subsequently, a silicon nitride film 11 for processing having a film thickness of about 70 nm is laminated and formed by the low pressure CVD method.

  Next, as shown in FIG. 5, a trench 1 a is formed in the silicon substrate 1. First, a photoresist (not shown) is processed into a desired pattern by a lithography technique. The silicon nitride film 11, the polycrystalline silicon film 5a, and the gate insulating film 4 are etched and removed by RIE (reactive ion etching) using the photoresist as a mask, and the silicon substrate 1 is etched to form the trench 1a. . Subsequently, the photoresist is removed using an ashing technique, and the surface layer portion of the silicon substrate 1 is separated as shown in the drawing to form an element formation region, that is, an active region 3.

  Subsequently, as shown in FIG. 6, an element isolation insulating film 2 is formed. First, heat treatment is performed in an oxygen atmosphere to form a thin thermal oxide film on the inner wall surface of the trench 1a, and then a silicon oxide film or the like as the element isolation insulating film 2 is formed in the trench 1a by HDP (high density plasma) method or the like. Deposit to embed. Next, the silicon nitride film 11 is polished using a CMP (chemical mechanical polishing) method as a stopper. As a result, the element isolation insulating film 2 formed above the upper surface of the silicon nitride film 11 is removed, and the element isolation insulating film 2 is buried only in the trench 1a and planarized to obtain the configuration shown in FIG.

  Next, as shown in FIG. 7, the element isolation insulating film 2 is processed to a low height, and the processing silicon nitride film 11 is removed. Here, the element isolation insulating film 2 is etched under the condition of etching the silicon oxide film by the RIE method, and its height is lowered to the middle of the side surface of the polycrystalline silicon film 5a. Further, the silicon nitride film 11 is removed by etching by wet processing or the like. The reason why the upper surface of the element isolation insulating film 2 is dropped is to increase the contact area between the polycrystalline silicon film 5a serving as the floating gate electrode film and the interelectrode insulating film 6 in the configuration of the gate electrode MG.

  Subsequently, as shown in FIG. 8, an interelectrode insulating film 6, a polycrystalline silicon film 7a, and a silicon oxide film 8 are sequentially stacked on the upper surface of the above structure. The interelectrode insulating film 6 is made of a material such as an ONO (oxide-nitride-oxide) film, a NONON (nitride-oxide-nitride-oxide-nitride) film, or a high dielectric film (high-k) by a low pressure CVD method. Deposit to form. The polycrystalline silicon film 7a is formed by the low pressure CVD method, with a film thickness of about 40 nm, with phosphorus (P) added as an impurity. After the polycrystalline silicon film 7a is deposited, heat treatment is performed in an oxidizing atmosphere, and the polycrystalline silicon film 7a is thermally oxidized to form a thin silicon oxide film 8 having a thickness of about 5 nm.

  Next, as shown in FIG. 9, a trench V is formed in the formation region of the gate electrode SG. The photoresist is patterned corresponding to the formation position of the slit-like short opening 6a formed in the interelectrode insulating film 6 by lithography. Using this photoresist as a mask, the silicon oxide film 8, the polycrystalline silicon film 7a, and the interelectrode insulating film 6 are etched into a slit shape by the RIE method, and the polycrystalline silicon film 5a is etched to a predetermined depth to form a groove V. . Thereafter, the photoresist is removed by an ashing process. As a result, as shown in FIG. 9B, as the cross section of the portion where the groove V is formed, the polycrystalline silicon film 5a is etched to a predetermined depth, and the height of the upper surface of the polycrystalline silicon film 5a is set to the element height. It is in a state of being dropped to almost the same level as the upper surface of the interelectrode insulating film 6 formed on the isolation insulating film 2. In addition, a slit-shaped short-circuit opening 6 a is formed in the interelectrode insulating film 6, and a slit-shaped short-circuit opening 8 a is formed in the silicon oxide film 8.

  Next, as shown in FIG. 10, a polycrystalline silicon film 9a and a processing silicon nitride film 12 are stacked. The polycrystalline silicon film 9a is formed as a film added with phosphorus (P) as an impurity with a predetermined film thickness by a low pressure CVD method. As a result, the polycrystalline silicon film 9a is buried in the trench V formed in the formation region of the gate electrode SG via the short-circuit opening 8a. Thereafter, the silicon nitride film 12 is formed with a predetermined film thickness by a low pressure CVD method.

  Subsequently, as shown in FIG. 11, the gate electrode MG as the first gate electrode and the gate electrode SG as the second gate electrode are separately formed. First, a photoresist is processed into a gate electrode pattern by lithography. Next, the silicon nitride film 12, the polycrystalline silicon film 9a, the silicon oxide film 8, the polycrystalline silicon film 7a, the interelectrode insulating film 6, and the polycrystalline silicon film 5a are etched by RIE using a photoresist as a mask. Thereafter, the photoresist is removed using an ashing technique to form gate electrodes MG and SG. In this case, on the gate electrode SG side, patterning is performed so that the short-circuit opening 6a of the interelectrode insulating film 6 and the short-circuit opening 8a of the silicon oxide film 8 described above remain.

  Next, as shown in FIG. 12, the interlayer insulating film 10 is deposited so as to be buried between gate electrodes (not shown) such as between the gate electrodes MG-SG, between MG-MG, and between SG-SG. Subsequently, the silicon nitride film 12 is removed, and a part of the upper layer of the interlayer insulating film 10 is removed using an ion etching method such as the RIE method to expose part of the upper surface and side surfaces of the polycrystalline silicon film 9a. . Thereafter, the photoresist 13 is patterned by lithography to cover the word lines WL, that is, the portions other than the portion of the polycrystalline silicon film 9a of the gate electrode MG.

  Next, as shown in FIG. 13, the polycrystalline silicon film 9a formed on the upper part of the gate electrode MG of the memory cell transistor corresponding to the word line WL is etched using the photoresist 13 as a mask using the RIE method. The photoresist 13 is removed by an ashing process. At this time, the silicon oxide film 8 formed between the polycrystalline silicon films 7a and 9a of the gate electrode MG functions as a stopper when the polycrystalline silicon film 9a is etched.

  Thereafter, as shown in FIG. 3, the polysilicon film 9a of the gate electrode MG is silicided into a silicide film 9b, and part of the polysilicon films 9a, 7a, 5a of the gate electrode SG is converted into a silicide film 9b. , 7b, 5b. That is, first, the silicon oxide film 8 remaining on the upper surface of the gate electrode MG is removed. At this time, the surface of the polycrystalline silicon films 7a and 9a exposed on the upper surfaces of the gate electrodes MG and SG is subjected to surface treatment so that the natural oxide film and the like are removed.

  Thereafter, a metal material such as nickel (Ni) or cobalt (Co) for forming the silicide films 9b, 7b and 5b is formed by sputtering. Subsequently, heat treatment is performed to react the metal film with the polycrystalline silicon films 9a, 7a, and 5a to form low-resistance silicide films 9b, 7b, and 5b. At this time, the temperature and time for silicidation by heat treatment are controlled so that, for example, the entire polycrystalline silicon film 7a of the gate electrode MG becomes the silicide film 7b, so that excessive silicide reaction does not occur. .

  Thereby, on the gate electrode MG side, the polycrystalline silicon film 7a in contact with the metal film becomes a silicide film 7b by the progress of the silicidation reaction, but the progress stops on the upper surface of the interelectrode insulating film 6. . Therefore, as shown in FIG. 3C, the polycrystalline silicon film 7a is silicided into a shape along the step between the polycrystalline silicon film 5a serving as the floating gate electrode film and the element isolation insulating film 2.

  On the other hand, in the gate electrode SG, the polycrystalline silicon film 9a that is in contact with the metal film undergoes a silicidation reaction to become a silicide film 9b, and further, the groove V on the lower layer side through the opening of the silicon oxide film 8. It proceeds to the polycrystalline silicon film 7a through the polycrystalline silicon film 9a formed therein. Unlike the gate electrode MG, the gate electrode SG has a short-circuit opening 6a formed in the interelectrode insulating film 6 serving as a stopper. Therefore, the polycrystalline silicon film in the lower layer is formed through the short-circuit opening 6a. 5a is also silicided to form a silicide film 5b. In this case, the polycrystalline silicon films 9a, 7a and 5a are formed of the same material. However, since the time of film formation is different, a natural oxide film is formed at the boundary portion. It is expected that the progress of the silicidation will be slightly slower than that.

  The height of the gate electrode SG is higher than the height of the gate electrode MG by the film thickness of the interelectrode insulating film 8 and the polycrystalline silicon film 9a, and the polycrystalline silicon film on the gate electrode MG side. Since the heat treatment is completed to the extent that 7a is silicified, the silicidation of the gate electrode SG proceeds through the silicidation of the polycrystalline silicon film 5a through the short-circuit opening 6a of the interelectrode insulating film 6. However, it is possible to suppress the silicidation reaction from being completed and the silicidation from proceeding to the gate insulating film 4. Accordingly, the silicidation of the polycrystalline silicon films 7a and 5a in the gate electrode SG is stopped by a certain amount of silicidation reaction from the portion in contact with the groove V. Further, the silicidation of the polycrystalline silicon film 9a in the trench V proceeds from the opening 8a of the silicon oxide film 8 toward the polycrystalline silicon film 5a, so that the polycrystalline silicon film 9a in the trench V is in contact with the polycrystalline silicon film 9a. In the crystalline silicon film 7a, the progress of silicidation on the silicon oxide film 8 side proceeds compared to the progress of silicidation on the interelectrode insulating film 6 side. Accordingly, the width of the upper surface in contact with the silicon oxide film 8 is larger in the silicide film 7 b than the width in contact with the bottom surface in contact with the interelectrode insulating film 6, and the silicide film 7 b is formed in a narrow width in the lower part near the interelectrode insulating film 6. It is formed so that it gradually expands as it goes upward, and the portion in contact with the silicon oxide film 8 has the widest width. As a result, silicide films 7b and 5b as shown in FIG. 3A are formed.

  Thereafter, the wafer process is completed through various processes such as a contact formation process and an interlayer wiring process, and the NAND flash memory device is formed by cutting into chips. In the above description, the description and illustration of the formation process of the impurity diffusion region, which becomes the source / drain region, is omitted for the memory cell transistor and the select gate transistor. It is carried out at the timing.

  According to such a first embodiment, the gate electrode SG of the selection gate transistor, which is a transistor other than the gate electrode MG of the memory cell transistor, has a relatively high height of the polycrystalline silicon film serving as the control gate electrode film. Since the height is increased, when the upper portion of the polycrystalline silicon film serving as the control gate electrode is silicided, the progress of the silicidation reaction is transferred to the polycrystalline silicon film 5a serving as the floating gate electrode film via the short-circuit opening 6a. Even when it proceeds, it can be prevented that the gate insulating film 4 is reached.

  Thereby, the resistance of the word line WL can be reduced by reliably forming the polycrystalline silicon film 7a as the silicide film 7b in the gate electrode MG of the memory cell transistor, and the silicide reaction in the gate electrode SG of other transistors. Can be a stable processing process that does not proceed excessively.

  Further, when the polycrystalline silicon film 9a of the gate electrode MG is etched, the silicon oxide film 8 is formed as an etching stopper film between the polycrystalline silicon film 7a and the polycrystalline silicon film 9a is surely formed. It is possible to leave only the polycrystalline silicon film 7a and not etch the polycrystalline silicon film 7a.

(Second Embodiment)
FIGS. 14 to 17 show a second embodiment of the present invention. Hereinafter, parts different from the first embodiment will be described.
FIG. 14 is a configuration diagram in a state equivalent to FIG. 3 in the first embodiment. In FIG. 14, the difference from the first embodiment is that it has a step portion 10a formed such that the height of the upper surface of the interlayer insulating film 10 is low at the gate electrode MG side portion of the memory cell transistor. As a result, the control gate electrode portion 71 made of the silicide film above the gate electrode MG is formed such that the upper surface is exposed and the side surface is exposed to a position slightly lower than the upper surface.
Since this state is an intermediate stage of the manufacturing process, there may be a configuration in which the stepped portion 10a described above is eliminated in the state where the NAND flash memory device is formed.

Next, regarding the manufacturing process having the above-described configuration, parts different from those of the first embodiment will be described with reference to FIGS.
FIG. 15 illustrates a process following the manufacturing process illustrated in FIG. 11 in the first embodiment, and therefore, the processes up to the process illustrated in FIG. 11 are the same as those in the first embodiment. As shown in FIG. 15, the interlayer insulating film 10 is deposited so as to be buried between gate electrodes (not shown) such as between the gate electrodes MG-SG, or between MG-MG, and between SG-SG. Subsequently, the silicon nitride film 12 is polished by the CMP method as a stopper, and the excess interlayer insulating film 10 is removed so that the interlayer insulating film 10 is buried only between the gate electrodes MG and SG. Thereafter, the photoresist 14 is patterned by lithography so as to cover other than the word line WL, that is, the gate electrode MG.

  Next, as shown in FIG. 16, etching is performed by the RIE method using the photoresist 14 as a mask. In this etching, the word line WL, that is, the silicon nitride film 12 of the memory cell transistor is removed, and the upper surface of the polycrystalline silicon film 9a is exposed, and the silicon oxide film is exposed in the pattern of the photoresist 14. A part of the interlayer insulating film 10 is also etched to form a step 10a. Subsequently, the polycrystalline silicon film 9a is removed by etching using the silicon oxide film 8 as a stopper by RIE to expose the upper surface of the silicon oxide film 8. Thereafter, the photoresist 14 is removed by an ashing process.

  Subsequently, as shown in FIG. 17, the silicon nitride film 12 formed on the upper surface of the gate electrode SG other than the word line WL, that is, other than the word line WL is etched and removed by the RIE method. Expose the top surface. In this etching, the silicon oxide film 8 exposed on the upper surface of the gate electrode MG is removed at the same time, and the height of the upper surface of the interlayer insulating film 10 is also lowered by the etching. For example, as shown in the figure, the height of the upper surface of the interlayer insulating film 10 is slightly lower than the upper surface of the polycrystalline silicon film 9a on the gate electrode SG side, and the polycrystalline silicon film on the gate electrode MG side. The position is slightly lower than the upper surface of 7a.

Thereafter, as shown in FIG. 14, the polycrystalline silicon film 9 of the gate electrode MG is silicided into the silicide film 9a, and part of the polycrystalline silicon films 9a, 7a, 5a of the gate electrode SG is converted into the silicide film 9. , 7b, 5b. This processing step is substantially the same as in the first embodiment.
The effect similar to 1st Embodiment can be acquired also by such 2nd Embodiment.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
In the above embodiment, the gate electrode SG of the selection gate transistor has been described as an example. However, the present invention can also be applied to the case where other transistors such as a peripheral circuit transistor exist.
In the above-described embodiment, the polycrystalline silicon film 7a is shown as having a thickness of 80 nm. However, the thickness is not necessarily limited to 80 nm, and it may be formed thicker or thinner.
The silicon oxide film 8 formed on the polycrystalline silicon film 7a is not necessarily limited to a thermal oxide film by heat treatment in an oxidizing atmosphere, and a method of forming by depositing using a low pressure CVD method is adopted. You can also.

  Further, the silicon oxide film 8 is necessary as a stopper when the polycrystalline silicon film 9a on the gate electrode MG side is etched, but the difficulty in processing the gate electrode, that is, the polycrystalline silicon film 7a as the control gate electrode film. In consideration of the structure in which the silicon oxide film 8 is present between 1 and 9a, the film thickness is preferably in the range of 2 nm or more and 5 nm or less.

1 schematically shows an electrical configuration of a part of a memory cell region of a flash memory device according to a first embodiment of the invention. FIG. A plan view schematically showing a partial structure of a memory cell region Typical sectional drawing of the part shown by the cutting lines AA, BB, and CC in FIG. Schematic cross-sectional view at one stage of the manufacturing process (Part 1) Schematic cross-sectional view at one stage of the manufacturing process (Part 2) Schematic cross-sectional view at one stage of the manufacturing process (Part 3) Schematic cross-sectional view at one stage of the manufacturing process (Part 4) Schematic cross-sectional view at one stage of the manufacturing process (Part 5) Schematic sectional view at one stage of the manufacturing process (No. 6) Schematic cross-sectional view at one stage of the manufacturing process (Part 7) Schematic cross-sectional view at one stage of the manufacturing process (No. 8) Schematic cross-sectional view at one stage of the manufacturing process (No. 9) Schematic cross-sectional view at one stage of the manufacturing process (No. 10) Typical sectional drawing of the part shown by cutting line AA, BB, CC in FIG. 2 in the 2nd Embodiment of this invention. Schematic cross-sectional view at one stage of the manufacturing process (Part 1) Schematic cross-sectional view at one stage of the manufacturing process (Part 2) Schematic cross-sectional view at one stage of the manufacturing process (Part 3)

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 2 is an element isolation insulating film, 3 is an active region (element forming region), 4 is a gate insulating film, 5 is a lower electrode portion, 6 is an interelectrode insulating film, and 7 is an interelectrode insulating film. Intermediate electrode portion, 8 is a silicon oxide film, 9 is an upper electrode portion, 5a, 7a and 9a are polycrystalline silicon films, 5b, 7b and 9b are silicide films, 51 is a floating gate electrode portion, 71 is a control gate electrode portion, MG is a gate electrode of the memory cell transistor, and SG is a gate electrode of the selection gate transistor.

Claims (5)

A semiconductor substrate;
A gate insulating film formed on the upper surface of the semiconductor substrate;
A floating gate electrode portion formed on the gate insulating film; a first inter-electrode insulating film formed on the floating gate electrode portion; and a control gate electrode portion formed on the inter-electrode insulating film. A gate electrode;
A lower electrode portion provided adjacent to the first gate electrode, formed on the gate insulating film and having the same thickness as the floating gate electrode portion, and formed on the lower electrode portion. A second inter-electrode insulating film having the same thickness as the inter-electrode insulating film and having a first opening formed thereon, and is formed on the second inter-electrode insulating film. An intermediate electrode portion having the same thickness as the film thickness and connected to the lower electrode portion through the first opening; and a second electrode formed on the intermediate electrode portion and corresponding to the first opening portion A third inter-electrode insulating film in which an opening is formed; and an upper electrode portion formed on the third inter-electrode insulating film and connected to the intermediate electrode through the second opening. A second gate electrode;
Nonvolatile, characterized in that portions of the control gate electrode portion, the upper electrode portion, and the intermediate electrode portion that are located between the first opening and the second opening are formed of a silicide film. Semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The first and second interelectrode insulating films are composed of a laminated film having a silicon oxide film and a silicon nitride film, and the third interelectrode insulating film is composed of a silicon oxide film. A nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
A part of the lower electrode film is formed of a silicide film within a range not reaching the first inter-electrode insulating film. A method of manufacturing a nonvolatile semiconductor memory device having a memory cell transistor and a select gate transistor,
Sequentially forming a gate insulating film, a first polycrystalline silicon film, and a processing insulating film on the upper surface of the semiconductor substrate;
The processing insulating film is patterned into a predetermined pattern, and the first polycrystalline silicon film, the gate insulating film and the semiconductor substrate are etched using the patterned processing insulating film as a mask, and the first groove is formed. Forming, and
Embedding an insulating film in the first trench, and forming an element isolation insulating film having an upper end height lower than the upper surface height of the first polycrystalline silicon film and higher than the surface height of the semiconductor substrate;
Forming an interelectrode insulating film, a second polycrystalline silicon film, and a silicon oxide film on the top surfaces of the first polycrystalline silicon film and the element isolation insulating film after removing the processing insulating film;
Forming a second groove over the silicon oxide film, the second polycrystalline silicon film, the interelectrode insulating film, and a part of the first polycrystalline silicon film in a gate electrode formation region of the select gate transistor; When,
Forming a third polycrystalline silicon film so as to fill the upper surface of the silicon oxide film and the second groove;
Processing the third polycrystalline silicon film, the silicon oxide film, the second polycrystalline silicon film, the interelectrode insulating film, and the first polycrystalline silicon film to form a gate electrode formation region of the memory cell transistor Forming a first gate electrode and a second gate electrode in a gate electrode formation region of the select gate transistor;
Embedding and forming an interlayer insulating film between the first and second gate electrodes;
Removing the third polycrystalline silicon film and the silicon oxide film of the first gate electrode and exposing an upper surface of the second polycrystalline silicon film of the first gate electrode;
The second polycrystalline silicon film of the first gate electrode is silicided, and the third polycrystalline silicon film on the interelectrode insulating film of the second gate electrode and in the second groove portion And a step of silicidizing the semiconductor in order. The method for manufacturing a nonvolatile semiconductor memory device according to claim 4,
The method of manufacturing a nonvolatile semiconductor memory device, wherein the silicon oxide film is formed by thermally oxidizing the upper surface of the second polycrystalline silicon film.

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