JP2010074379A - Driver circuit, and electronic circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driver circuit which accurately acquires a load current at a specified ratio to a reference current. <P>SOLUTION: A drain terminal of a MOS transistor M3 is connected with two resistances R1 and R2, and their other ends are connected with a current generator IREF and a load LOAD. Both resistance values are the same. The connection part of the drain terminal of the transistor M3 and both of the resistances is a connection point A. In the electronic circuit device, the connection part of the resistance R1 and the current generator IREF is a connection point B, the connection part of the resistance R2 and the load LOAD is a connection point C, and they are connected to input terminals of a differential amplifier A1. In the differential amplifier, a gate terminal of the transistor M3 is connected with an output terminal that is a control input terminal, and the connection part is a connection point G. The differential amplifier functions as a circuit which feeds back the potential difference between the connection points B and C. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a driver circuit and an electronic circuit device, and more particularly to a driver circuit that allows a required current value to flow to a load with high accuracy based on a reference current.

In order to solve the problem that a desired mirror ratio cannot be obtained if the drain-source voltages of the transistors existing in the two current paths of the current mirror circuit are different, Patent Document 1 discloses a current mirror circuit. There are a first transistor in the first path and a second transistor in the second path, and the sources of both transistors are grounded. In order to equalize the drain-source voltages of these transistors, an operational amplifier for inputting the drain voltages of both transistors and a third transistor having the output of the operational amplifier connected to the gate are provided, and this third transistor is connected to the first path. Put in. As a result, the current flowing through the third transistor is controlled so that the drain-source voltages of the first transistor and the second transistor match.
Japanese Patent Application Laid-Open No. 2004-228867 discloses a current drive for supplying a current to a current generating element in order to solve the problem of uniforming the current supplied to a plurality of current generating elements and making the luminance of each current generating element uniform. There are a plurality of circuits in parallel, and each current drive circuit supplies a current at an arbitrary ratio between the drain-source voltage of one transistor element that flows a mirrored reference current from the current IREF flowing through the constant current generation circuit and the reference current. By having a differential amplifier circuit for making the drain-source voltage of the other transistor element to be supplied the same, a uniform current can be mirrored to a plurality of MOS transistors, and the brightness of the current generating element of each current driving circuit can be increased. All are uniform.

In Patent Document 3, when a plurality of LEDs are connected in parallel, it is necessary to connect a constant current circuit for each LED. Here, in order to make the light emission luminance of each LED uniform, a constant current to be supplied to each LED is required to have a very high accuracy of about 1% to several%. However, in order to solve the problem that it was difficult from the semiconductor manufacturing process to generate such a high-accuracy constant current from a plurality of constant current circuits, the reference current is converted into a voltage by a resistor, and the load A resistor is also added to the current side to convert it to a voltage, and the voltage between terminals of each resistor is referred to and fed back to the load circuit side by a differential amplifier circuit.
In Patent Document 4, in the cascode current mirror circuit, the channel terminal modulation effect is suppressed by feeding back the drain terminal of the transistor connected to the load to the input current side, and the constant current characteristic of the output current is reduced. It is possible to greatly improve the conventional basic current mirror circuit, and to make the output current rise time characteristic with respect to the change of the input current better than the cascode current mirror circuit and the low voltage cascode current mirror circuit. Can do. However, there is a problem that the input current and the output current are not completely equal.
JP 2005-173741 A JP 2006-237382 A JP 2006-318337 A JP 2004-180007 A

A current mirror circuit as shown in FIG. 27 is a well-known method when a current driving element such as an LED as a load is to be driven with high accuracy at a predetermined ratio with respect to a reference current. However, even if the reference current side transistor TR1 and the load current side transistor TR2 operate in a sufficiently saturated region, even if the drain-source voltage is slightly different, the current mirror circuit is affected by the channel length modulation effect. And the load current is not necessarily equal.
Furthermore, when the transistor TR2 constituting the current mirror circuit is operated linearly by the voltage between the terminals of the current driving element, the drain-source voltage and the load current are in a proportional relationship, and are saturated. Compared with the operation, the influence of the drain-source voltage fluctuation on the load current becomes very significant. Therefore, it is necessary to set the power supply voltage high in order to ensure a sufficient drain-source voltage for the saturation operation, which may increase power consumption.
Therefore, when using the current drive element as described above, if the resistance value of the transistor can be controlled so that the ratio of the reference current and the load current does not change even with respect to the power supply and ground voltage / current drive element terminal voltage fluctuations, A highly accurate load current can be generated at a predetermined ratio with respect to the reference current. That is, with such a configuration, the load current can be mirrored at a predetermined ratio even when the drain-source voltage of the transistor TR2 constituting the current mirror circuit is low (when operating in the linear region). This also means that the power supply voltage can be kept low, leading to a reduction in power consumption.

Therefore, in Patent Document 3, one end of two resistors through which a reference current and a load current flow is connected in common, and feedback control is performed so that the other end potentials of the resistors coincide with each other. Specifically, the reference current is mirrored with high accuracy by feeding back to the gate terminal of the transistor on the load current path.
However, in this configuration, there is no signal feedback to the reference current side, that is, control is performed to accurately follow the load current with a predetermined ratio with respect to a certain fixed reference current. The current-voltage characteristic on the drive element side is not considered at all, and only the current-voltage characteristic on the reference current side is referred to. For this reason, there is a possibility that the operation range of the current driving element is limited and a desired load current cannot be obtained.
Patent Document 2 improves this problem. In this prior art, feedback is performed to the common gate terminal of the transistors constituting the current mirror circuit, so that the gate and drain terminals of both transistors constituting the current mirror circuit are controlled by a control input (input to the gate terminal). The potential of fluctuates.
In particular, in this configuration, when the controller portion is removed, when the potential of the gate terminal of the transistor constituting the current mirror circuit is swept from the ground to the power supply voltage, the potential of both drain terminals decreases monotonously. On the other hand, the current flowing through the current source and the current driving element increases monotonously. When there is a potential at the gate terminal such that the potentials at both drain terminals of the transistors constituting the current mirror circuit have the same value, the biases of both transistors settle at that point (the ratio of both current values is the ratio of the respective transistor sizes). Will be equal). Further, even when the drain-source voltage of the transistors constituting the current mirror circuit is low (when operating in a linear region), the current can be mirrored at a predetermined ratio. This means that the power supply voltage can be kept low, leading to a reduction in power consumption.

However, in this configuration, no matter what type or value of transistor size, current source, or current drive element, when the potential of the gate terminal is set to the power supply voltage, the drain terminals of both transistors constituting the current mirror circuit The potential always takes a value of zero. Further, in some cases, there may be two points where the potential of the drain terminal takes the same value even at a point other than zero. That is, with this configuration, there is a possibility that a plurality of convergence points exist.
With regard to this point, in Patent Document 1, a portion where a signal is fed back is used as a gate terminal of a transistor connected in series to a current source. The connection point between the transistor and the current source is connected to the gate terminal of the transistor constituting the current mirror circuit. As in the case of Patent Document 2, when the controller unit is removed, when the gate terminal of the transistor connected in series with the current source, that is, the potential of the control input is swept from the ground to the power supply voltage, the drain of the transistor constituting the current mirror circuit The terminal potential decreases monotonously. However, unlike the case of Patent Document 2, it is possible to alternate the direction of change such that the current of the current source monotonously increases and the current of the load monotonously decreases. Therefore, if there is a potential at the gate terminal where the potentials of the drain terminals of both transistors constituting the current mirror circuit have the same value, that point can be unique.
However, even if the total bias potentials of the transistors are matched, if the individual variations such as V _th (threshold voltage) variations due to each transistor, power supply and ground variations occur, the ratio between the reference current and the load current will be different. It will be converged.
For example, when V _th (threshold voltage) variation occurs, the gate-source voltage apparently varies as shown in FIG. Assuming that the drain current value at the reference (no variation) is I0 and the variation range is ΔI, the variation rate can be expressed as ΔI / I0. Therefore, the effect becomes significant when a low drain current value is handled. In other words, the drain currents take different values even between transistors having the same bias.

In addition, the power supply and the ground potential applied to each transistor are not necessarily equal because of a voltage drop due to the resistance of the power supply and the ground wiring (power supply and ground variation). For this reason, the drain currents take different values even between transistors to which the same bias is applied.
The present invention has been made in view of the above problems, and in a driver circuit for driving a current driving element such as an LED, the influence of individual transistor variations, power supply and ground variations is eliminated, and the controller always operates properly. An object of the present invention is to provide a driver circuit that can obtain a load current at a predetermined ratio with respect to a reference current with high accuracy by making it function in a range.

  In order to solve this problem, the present invention provides a driver circuit for supplying a load with a predetermined ratio of a load current with respect to a reference current, the reference current generating means for generating the reference current, and Current driving means for supplying current to a load and the reference current generating means, respectively, and the current driving means includes a first resistor provided on a reference current path connected to the reference current generating means, A second resistor provided on a load current path connected to the load, and a voltage appearing at a terminal of the first resistor on the side of the reference current generating means are applied to the first input terminal, and the second resistor A differential amplifier in which a voltage appearing at the load side terminal is applied to a second input terminal, and a first terminal connected to the drain terminal by commonly connecting the other ends of the first resistor and the second resistor. A differential amplifier. By vessels of the output terminal is connected to the gate terminal of the first transistor, characterized in that so as to return the potential difference between the first input terminal and the second input terminal.

  According to a second aspect of the present invention, there is provided a driver circuit for supplying a load with a predetermined ratio of load current to a reference current, the reference current generating means for generating the reference current, and the load and the reference current generating means with currents respectively. Current driving means for supplying, on the path of a reference current connected to a first transistor having a drain terminal connected to the reference current generating means and a source terminal of the first transistor. The voltage appearing at the connection point between the first resistor provided, the second resistor provided on the path of the load current connected to the load, and the source terminal of the first resistor and the first transistor is first. And the other end of the first resistor and the second resistor in common with the differential amplifier in which the voltage appearing at the load-side terminal of the second resistor is applied to the second input terminal. Connect and dray A second transistor to which a fixed potential is applied, and the output terminal of the differential amplifier is connected to the gate terminal of the first transistor, so that the first input terminal A potential difference from the second input terminal is fed back.

  According to a third aspect of the present invention, there is provided a driver circuit for supplying a load current having a predetermined ratio with respect to a reference current to the load, the reference current generating means for generating the reference current, and currents for the load and the reference current generating means, respectively. Current driving means for supplying a first transistor having a drain terminal connected to the reference current generating means, and a reference current path connected to the source terminal of the first transistor. And a voltage appearing at a connection point between the first resistor and the source terminal of the first transistor is a first resistor provided on the first resistor, a second resistor provided on a load current path connected to the load, A differential amplifier applied to the input terminal of the first resistor and a voltage appearing on the load-side terminal of the second resistor applied to the second input terminal, and the other end of the first resistor and the second resistor shared Connected to A second transistor having a gate terminal connected to the drain terminal of the first transistor, and an output terminal of the differential amplifier connected to the gate terminal of the first transistor. A potential difference between the first input terminal and the second input terminal is fed back.

According to a fourth aspect of the present invention, the reference current and the load current are adjusted to a predetermined ratio by changing a ratio between the first resistor and the second resistor.
According to a fifth aspect of the present invention, the first resistor or the second resistor is constituted by a resistor circuit means in which a plurality of circuits each having a resistor having an arbitrary value and a switch connected in series with the resistor are connected in parallel. It is characterized in that each switch can be connected and disconnected independently.
According to a sixth aspect of the present invention, the switch is composed of an NMOS transistor.
According to a seventh aspect of the present invention, the switch includes a PMOS transistor.
The present invention is characterized in that the switch is a complementary switch using an NMOS transistor and a PMOS transistor.
A ninth aspect includes a light emitting diode as the load, and an anode of the light emitting diode is connected to the second resistor.

  A driver circuit for supplying a load with a predetermined ratio of a load current with respect to a reference current to a load, the current driving means for supplying a current to the load and a first current source for generating the reference current, and a reference A dummy circuit having a resistor, and the current driving means includes first and second variable resistors whose resistance values change according to voltage values, and the first current source and the load, one of which is connected to the ground. The first variable resistor connected to the other end of the first current source is provided on the path of the reference current, and the second variable resistor connected to the other end of the load is the load current. The potential appearing at the connection point between the first variable resistor and the first current source is applied to the first input terminal, and the potential appearing at the connection point between the second variable resistor and the load is First differential amplifier applied to second input terminal A first voltage controlled current source having one end connected to a power source and the other end connected to a terminal commonly connected to the other ends of the first variable resistor and the second variable resistor, and the dummy circuit Applies a potential appearing at a connection point between a second current source having one end connected to a reference resistor and the other end connected to the ground, and the first variable resistor and the first current source to the first input terminal. A second differential amplifier in which a potential appearing at a connection point between the reference resistor and the second current source is applied to a second input terminal, one end is connected to a power source, and the other end is the other end of the reference resistor A second voltage controlled current source connected to the first differential amplifier, and an output terminal of the first differential amplifier is connected to a control terminal of the first voltage controlled current source and the second voltage controlled current source. The first input terminal and the second input of the first differential amplifier The potential difference between the first and second variable amplifiers is fed back, and the output terminal of the second differential amplifier is connected to the control terminals of the first variable resistor and the second variable resistor. A potential difference between the input terminal and the second input terminal is fed back.

  A driver circuit for supplying a load with a predetermined ratio of load current to a reference current to a load, current driving means for supplying current to the load and a first current source for generating the reference current, and a reference A dummy circuit having a resistance, wherein the current driving means includes a first variable current whose first and second variable resistances change in accordance with a voltage value, a first MOS transistor, and one of the first currents connected to the ground. The first MOS transistor having a source and the load and having a drain terminal connected to the other end of the first current source is provided on the path of the reference current, and the source terminal of the first MOS transistor has the first MOS transistor 1 variable resistor is connected, and the second variable resistor connected to the load is provided on the path of the load current, and a connection point between the first variable resistor and the first MOS transistor A first differential amplifier in which a potential that appears is applied to the first input terminal, a potential that appears in a connection point between the second variable resistor and the load is applied to the second input terminal, one end is connected to a power source, and the like The first voltage control current source is connected to a terminal commonly connected to the other ends of the first variable resistor and the second variable resistor, and the dummy circuit has both terminals each having a drain of the second MOS transistor. A second current source connected to the terminal and the ground, the reference resistor connected to the source terminal of the second MOS transistor, and a potential appearing at a connection point between the first MOS transistor and the first current source. A second differential amplifier that is applied to one input terminal and a potential appearing at a connection point between the second MOS transistor and the second current source is applied to the second input terminal; A second voltage controlled current source connected to the other end of the reference resistor, and an arbitrary fixed potential is applied to a common control terminal of the first and second voltage controlled current sources, Since the output terminal of one differential amplifier is connected to the gate terminals of the first and second MOS transistors, the potential difference between the first input terminal and the second input terminal of the first differential amplifier is fed back. The output terminal of the second differential amplifier is connected to the control terminals of the first and second variable resistors, whereby the first input terminal and the second input terminal of the second differential amplifier. And the potential difference between the two is fed back.

A twelfth aspect is characterized in that the potential of the common control terminal of the first and second voltage controlled current sources is the same as that of the first input terminal of the second differential amplifier.
The resistance circuit means in which one or a plurality of circuits each having a variable resistor having a common control terminal and a switch each connected in series with the variable resistor are connected in parallel is the first variable resistor or the One or a plurality of circuits each having a voltage control current source having a common control terminal and a switch connected in series with each of the voltage control current sources and one of a plurality of second variable resistors are installed in parallel. The connected current source means is installed in place of the first voltage control current source, and the switches can be independently turned on and off.
14. The common control terminal according to claim 14, wherein one or a plurality of variable resistors having a common control terminal are connected in parallel, and the resistance circuit means is replaced with either the first variable resistor or the second variable resistor. A current source means in which one or a plurality of voltage controlled current sources having a parallel connection is installed in place of the first voltage controlled current source, and the variable resistor and the voltage controlled current source do not conduct current, It is realized by a signal input to each control terminal.

According to a fifteenth aspect of the present invention, a switch is connected in series to the control terminal of the variable resistor and the voltage controlled current source, and when the switch is OFF, the control terminal has a power supply or ground potential.
According to a sixteenth aspect of the present invention, the dynamic range of an inverter or a buffer that outputs a signal input to each control terminal of the variable resistor and the voltage control current source is connected to the control terminal of the variable resistor. In this case, it is determined by the voltage across the variable resistor, and when the inverter or buffer is connected to the control terminal of the voltage controlled current source, it is determined by the voltage across the voltage controlled current source. Features.
According to a seventeenth aspect of the present invention, the variable resistor or the voltage control current source is formed of a MOS transistor.
An eighteenth aspect is characterized in that the switch is constituted by a MOS transistor.

A nineteenth aspect includes a light emitting diode as the load, and an anode of the light emitting diode is connected to the second variable resistor.
In an electronic circuit device in which a plurality of driver circuits according to any one of claims 1 to 9 are arranged, the current source is configured by one MOS transistor, and the size and characteristics of the MOS transistors are equal. And connected by a common gate terminal.
A twenty-first aspect of the invention is an electronic circuit device in which a plurality of driver circuits according to any one of the tenth to thirteenth aspects are arranged, wherein each of the first current sources is a current mirror circuit, and the current mirror circuit has a MOS A driver circuit characterized in that transistors have the same size and characteristics.
Claim 22 is a current driving device for uniformly controlling the luminance of each semiconductor laser by making all currents supplied to each semiconductor laser uniform, and has the driver circuit according to claim 20 or 21. It is characterized by that.

According to the present invention, control is performed so that the potentials at both ends of two resistors having the same resistance value are equal to each other, and the current is directly controlled using a resistor rather than controlling the bias of the transistor. Therefore, the values of the reference current and the load current can be made equal without being affected by the individual variation of the current driving transistor, the power supply, and the ground variation. In addition, even when the drain-source voltage of the current driving transistor is low (when operating in the linear region), the current can be mirrored with high accuracy, which means that the power supply voltage can be kept low. It is effective for reducing power.
In addition, since the reference current and the load current change direction (increase or decrease) when the control input is input conflict, there is a convergence point (a point where the potentials at both ends of the resistors R1 and R2 become equal). For example, it can be limited to one.
Further, by changing the ratio of the two resistors, the ratio of the reference current and the load current can be adjusted to the ratio of the reciprocal of the resistance value. This means that when the same load current is applied to the load, the reference current can be lowered by setting the resistance value of one of the resistors high, and the efficiency in terms of power consumption can be improved.

In addition, a resistor circuit in which a plurality of circuits each having a resistor having an arbitrary resistance value and a switch connected in series with the resistor are connected in parallel is replaced with two resistors, and each switch is turned on and off independently. By doing so, it is possible to change two resistance values apparently. The more current circuits having a resistor and a switch connected in series with the resistor are connected in parallel, the finer current ratio can be realized.
In addition, when a light emitting diode is provided as a load, the voltage between the terminals increases depending on the desired luminance, so that the current driving transistor may operate in the linear region, but the voltage between the terminals of the two resistors is set to the same value. Thus, since the reference current and the drive current are controlled, it is possible to flow a load current having a predetermined ratio with respect to the reference current without being affected by fluctuations in the power supply, the ground voltage, and the voltage between the light emitting diode terminals.
In addition, control is performed so that the potentials at both ends of the two variable resistors are equal, and the current is directly controlled using the variable resistors, so that there is no influence of individual variation, power supply, and ground variation. The value of the reference current and the load current can be set to a predetermined ratio. Further, when the two voltage controlled current sources are MOS transistors, the current can be mirrored with high accuracy even when the drain-source voltage is low (when operating in the linear region). This also means that the power supply voltage can be kept low, which is effective in reducing power consumption. In addition, when MOS transistors are used as the two variable resistors, there is a possibility that individual variations will be affected, but by referring to the resistance value of the resistor connected to one voltage controlled current source That problem can be solved.

In addition, there is a convergence point (a point where the potentials at both ends of the variable resistors VR1 and VR2 are equal) because the directions of change (increase or decrease) of the reference current and the load current when the control input is input conflict. If so, it can be limited to only one.
Further, by changing the ratio of the two variable resistors, the ratio of the reference current and the load current can be adjusted to the ratio of the reciprocal of the resistance value. This means that, for example, when the same load current is supplied to the load, the reference current can be lowered by setting the resistance value of one of the variable resistors high, and the efficiency in terms of power consumption can be improved. . A resistance circuit in which a plurality of circuits each having a variable resistor having a common control terminal and a switch connected in series with the variable resistor are connected in parallel is replaced by two variable resistors, and each switch is independently input. Since it can be turned off, the resistance values of the two variable resistors can be changed apparently. As more circuits having a variable resistor and a switch connected in series with the variable resistor are connected in parallel, a finer current ratio can be realized. Also, by connecting multiple voltage controlled current sources that have a common control terminal with one of the voltage controlled current sources in parallel and providing a switch in series, it is possible to change the load current while suppressing fluctuations in the reference current, Providing a plurality of current sources also has an effect of avoiding a state where an excessive current flows through the voltage controlled current source and the circuit does not function.

Also, by removing the switch connected in series and providing a switch at the control terminal of the variable resistor and voltage controlled current source, the dynamic range of each potential on the circuit is wider than when connected in series on the current path. Therefore, the dynamic range of the current values of the load current and the reference current can be widened. Further, when the switch is turned off, the control terminal takes the power supply or the ground potential, so that the current of the voltage control current source and the variable resistor can be cut off without floating the control terminal.
In addition, by providing the control terminal potential when the switch connected to the control terminal is ON or OFF as the H or L potential supplied to the inverter, the number of transistors can be reduced and the chip area cost can be reduced. It becomes. In the driver circuit of the present invention, not only the voltage control current source and the variable resistor are turned ON / OFF, but also the H or L potential supplied to the inverter is the potential applied to both ends of the voltage control current source or the variable resistor. As a result, the output range of the inverter can be suppressed to be lower than that in the case of moving between the power source and the ground, and the power consumption of the inverter, and thus the power consumption of the entire chip can be reduced.

In addition, when a light emitting diode is used as a load, the voltage between the terminals increases depending on the desired luminance, so that the MOS transistor included in the current source or the variable resistor may operate in a linear region. Since the reference current and load current are controlled by setting the terminal voltage to the same value, the load current at a predetermined ratio with respect to the reference current is not affected by fluctuations in the voltage between the power supply, ground voltage, and LED terminals. Can flow.
Also, by arranging a plurality of driver circuits in parallel and making each current generator a general current mirror circuit, the reference current and the load current in each driver circuit can all be made equal. With such a configuration, a current light-emitting element such as a light-emitting diode can suppress variations in light emission luminance, and light emission without unevenness can be realized.
Further, by arranging a plurality of driver circuits in parallel and using the current generator as a current mirror circuit, all of the reference current and load current in each driver circuit can be made equal. In the current light emitting element such as a light emitting diode, variation in light emission luminance is suppressed, and light emission without unevenness can be realized.
In printers and copiers, etc., the current supplied to each semiconductor laser is made uniform by using the driver circuit of the present invention, so that the brightness of each semiconductor laser can be made uniform and the image density becomes uneven. The effect such as not being obtained.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .
FIG. 1 is a diagram showing a driver circuit according to the first embodiment of the present invention.
Two resistors R1 and R2 are connected to the drain terminal of the MOS transistor M3, and a current generator IREF and a load LOAD are connected to the other ends, respectively. Both resistance values are assumed to be the same value. A connection point between the drain terminal of the transistor M3 and both resistors is a connection point A.
This electronic circuit device has a connection point between the resistor R1 and the current generator IREF as a connection point B, and a connection point between the resistor R2 and the load LOAD as a connection point C, and is connected to the input terminal of the differential amplifier A1. . In the differential amplifier, an output terminal, that is, a control input terminal is connected to the gate terminal of the transistor M3. The connecting portion is defined as a connection point G. The differential amplifier functions as a circuit that feeds back the potential difference between the connection points B and C.

Here, a case where the feedback circuit is removed in the present embodiment will be considered. With this configuration, the potential at the connection point G is swept from the ground to the power supply voltage. A graph relating to the potentials of the connection points B and C at this time is shown in FIG. 2, and a graph relating to the currents (Ir1, Ir2) flowing through the current generator IREF and the load LOAD is shown in FIG.
It can be seen from FIG. 2 that the potentials at the connection points B and C, and from FIG. 3, all the currents flowing through the current generator IREF and the load LOAD are monotonically decreasing. Each graph has an intersection P1. The value of the connection point G at the intersection P1 is equal to Vg0. This is because when the connection point G takes Vg0, the potentials of the connection points B and C are equal, so that one terminal of the resistors R1 and R2 is connected in common at the connection point A. This is because the current Ir1 supplied by the current generator IREF is equal to the current Ir2 flowing through the load.
In addition, it can be seen from FIG. 2 that convergence can be achieved by connecting the connection point B to the non-inverting input terminal and the connection point C to the inverting input terminal (the potentials of the connection points B and C are equal). Here, the differential amplifier A1 functions sufficiently within the operation range of each terminal used in the description.

As described above, in the first embodiment of the driver circuit according to the present invention, one terminal of the resistors R1 and R2 connected to the current generator side and the load side is made common, and the other terminal is connected to the differential amplifier A1. The current flowing through both resistors is made equal by performing control so as to take the same value by a feedback circuit including With this configuration, there is no influence of individual variation due to the transistor M3, and since only one transistor is connected to the power supply, it is possible to prevent the occurrence of power supply variation. That is, since the current is directly controlled rather than controlling the bias of the transistor, both current values can be equalized with high accuracy.
Even when the drain-source voltage of the transistor M3 is low (when operating in the linear region), the current can be mirrored at a predetermined ratio. This also means that the power supply voltage can be kept low, which is effective in reducing power consumption.
However, as can be seen from FIGS. 2 and 3, in the present embodiment, when the potential at the connection point G takes the power supply voltage, the intersection point P2 always exists (a plurality of convergence points exist). Further, since both the voltage in FIG. 2 and the current in FIG. 3 are monotonously decreasing, there is a possibility of having an intersection other than the intersections P1 and P2. In the second and subsequent embodiments, this problem is solved.

FIG. 4 is a diagram showing a driver circuit according to the second embodiment of the present invention.
Two resistors R1 and R2 are connected to the drain terminal of the MOS transistor M3, and a load LOAD is connected to the other end of the resistor R2. Both resistance values are assumed to be the same value. A connection point between the drain terminal of the transistor M3 and both resistors is a connection point A.
Further, a transistor M4 is inserted between the resistor R1 and the current generator IREF. The transistor M4 has a source terminal connected to the resistor R1, and a drain terminal connected to the current generator IREF.
In this electronic circuit device, a connection point between the resistor R1 and the source terminal of the transistor M4 is a connection point B, a connection point between the resistor R2 and the load LOAD is a connection point C, and a connection point between the drain terminal of the transistor M4 and the current generator IREF. Is the connection point D, and connection points B and C are connected to the input terminal of the differential amplifier A1. It is assumed that the gate terminal of the transistor M3 is fixed to a predetermined potential by a current mirror circuit or the like. In the differential amplifier A1, an output terminal, that is, a control input terminal is connected to the gate terminal of the transistor M4. The connecting portion is defined as a connection point G. The differential amplifier functions as a circuit that feeds back the potential difference between the connection points B and C.

Here, a case where the feedback circuit is removed in the present embodiment will be considered. With this configuration, the potential at the connection point G is swept from the ground to the power supply voltage. A graph relating to the potentials of the connection points B and C at this time is shown in FIG. 5, and a graph relating to the currents (Ir1, Ir2) flowing through the current generator IREF and the load LOAD is shown in FIG.
When looking at FIG. 5, the potential at the connection points B and C increases monotonically, while when looking at FIG. 6, the current Ir1 supplied by the current generator IREF decreases monotonously and the current Ir2 flowing through the load LOAD increases monotonously. I understand that.
Further, an intersection P3 exists in each graph. The value of the connection point G at the intersection P3 is equal to Vg0. This is because when the connection point G takes Vg0, the potentials of the connection points B and C are equal, so that one terminal of the resistors R1 and R2 is connected in common at the connection point A. This is because the current Ir1 supplied by the current generator IREF is equal to the current Ir2 flowing through the load.
In addition, it can be seen from FIG. 5 that convergence can be achieved by connecting the connection point B to the inverting input terminal and the connection point C to the non-inverting input terminal (the potentials of the connection points B and C are equal). Here, the differential amplifier A1 functions sufficiently within the operation range of each terminal used in the description.

As described above, in the second embodiment of the driver circuit according to the present invention, one terminal of the resistors R1 and R2 connected to the current generator side and the load side is made common, and the other terminal is used as the differential amplifier A1. The current flowing through both resistors is made equal by performing control so as to take the same value by a feedback circuit including With this configuration, there is no influence of individual variation due to the transistor M3, and since only one transistor is connected to the power supply, it is possible to prevent the occurrence of power supply variation. That is, since the current is directly controlled rather than controlling the bias of the transistor, both current values can be made equal with high accuracy.
Further, when the value of the control input terminal G is changed, in the first embodiment, the intersection point P2 is always generated in addition to the intersection point P1, but in this embodiment, the current value Ir1 supplied by the current generator IREF and the load are applied. Since the direction of change (increase or decrease) of the flowing current Ir2 is contradictory, if there exists Vg0 in which the potentials of the connection points B and C have the same value, it is limited to only one (only the intersection point P3).
Even when the drain-source voltage of the transistor M3 is low (when operating in the linear region), the current can be mirrored at a predetermined ratio. This also means that the power supply voltage can be kept low, which is effective in reducing power consumption.

FIG. 7 is a diagram showing a driver circuit according to the third embodiment of the present invention.
Two resistors R1 and R2 are connected to the drain terminal of the MOS transistor M3, and a load LOAD is connected to the other end of the resistor R2. Both resistance values are assumed to be the same value. A connection point between the drain terminal of the transistor M3 and both resistors is a connection point A.
Further, a transistor M4 is inserted between the resistor R1 and the current generator IREF. The transistor M4 has a source terminal connected to the resistor R1, and a drain terminal connected to the current generator IREF.
In this electronic circuit device, a connection point between the resistor R1 and the source terminal of the transistor M4 is a connection point B, a connection point between the resistor R2 and the load LOAD is a connection point C, and a connection point between the drain terminal of the transistor M4 and the current generator IREF. Is the connection point D, the connection point D is connected to the gate terminal of the transistor M3, and the connection points B and C are connected to the input terminal of the differential amplifier A1. In the differential amplifier A1, an output terminal, that is, a control input terminal is connected to the gate terminal of the transistor M4. The connecting portion is defined as a connection point G. The differential amplifier functions as a circuit that feeds back the potential difference between the connection points B and C.

Here, a case where the feedback circuit is removed in the present embodiment will be considered. With this configuration, the potential at the connection point G is swept from the ground to the power supply voltage. A graph relating to the potentials of the connection points B and C at this time is omitted from FIG. 5, and a graph relating to the currents (Ir1, Ir2) flowing through the current generator IREF and the load LOAD is similar to that shown in FIG.
When looking at FIG. 5, the potential at the connection points B and C increases monotonically, while when looking at FIG. 6, the current Ir1 supplied by the current generator IREF decreases monotonously and the current Ir2 flowing through the load LOAD increases monotonously. I understand that.
Further, an intersection P3 exists in each graph. The value of the connection point G at the intersection P3 is equal to Vg0. This is because when the connection point G takes Vg0, the potentials of the connection points B and C are equal, so that one terminal of the resistors R1 and R2 is connected in common at the connection point A. This is because the current Ir1 supplied by the current generator IREF is equal to the current Ir2 flowing through the load.
In addition, it can be seen from FIG. 5 that convergence can be achieved by connecting the connection point B to the inverting input terminal and the connection point C to the non-inverting input terminal (the potentials of the connection points B and C are equal). Here, the differential amplifier A1 functions sufficiently within the operation range of each terminal used in the description.

As described above, in the third embodiment of the driver circuit according to the present invention, one terminal of the resistors R1 and R2 connected to the current generator side and the load side is made common, and the other terminal is used as the differential amplifier A1. The current flowing through both resistors is made equal by performing control so as to take the same value by a feedback circuit including With this configuration, there is no influence of individual variation due to the transistor M3, and since only one transistor is connected to the power supply, it is possible to prevent the occurrence of power supply variation. That is, since the current is directly controlled rather than controlling the bias of the transistor, both current values can be made equal with high accuracy.
Further, when the value of the control input terminal G is changed, in the first embodiment, the intersection point P2 is always generated in addition to the intersection point P1, but in this embodiment, the current value Ir1 supplied by the current generator IREF and the load are applied. Since the direction of change (increase or decrease) of the flowing current Ir2 is contradictory, if there is Vg0 in which the potentials of the connection points B and C have the same value, it is limited to only one (only the intersection point P3).
Even when the drain-source voltage of the transistor M3 is low (when operating in the linear region), the current can be mirrored at a predetermined ratio. This also means that the power supply voltage can be kept low, leading to a reduction in power consumption.

Next, as a fourth embodiment of the present invention, there is provided a driver circuit that changes the ratio of the resistance values of the resistors R1 and R2 in the driver circuits of the first to third embodiments to make the reference current and the load current have a predetermined ratio. Show.
The driver circuits of Embodiments 1 to 3 are all devices that control the potentials of the connection points B and C to be equal. Here, when the resistance values of the two resistors are different, if the voltage between the terminals takes the same value, it can be seen that the reference current and the load current flow at a ratio of the reciprocal of the resistance value according to Ohm's law.
As described above, according to the fourth embodiment of the driver circuit of the present invention, the reference values are obtained by setting the resistance values of both resistors R1 and R2 connected to the current generator side and the load side to a predetermined ratio. The value of the current and the load current can be made a ratio of the reciprocal of the resistance value. This means that when the same load current is supplied to the load, the reference current can be lowered by increasing the resistance value of the resistor R1, and the efficiency in terms of current consumption can be improved.

Next, as a fifth embodiment of the present invention, the driver circuit according to the first to fourth embodiments includes a resistor having an arbitrary resistance value and a switch connected in series with the resistor R1 or R2. A driver circuit in which a plurality of circuits are connected in parallel is shown.
FIG. 8 is a diagram showing a circuit representing the resistor R1 or R2 of the first to fourth embodiments according to the fifth embodiment of the present invention. In this driver circuit, the resistance value corresponding to the resistor R1 or R2 in the first to fourth embodiments is variable by switches S1 to Sn (n is a positive integer) connected in series to resistors Rp1 to Rpn (n is a positive integer). It is something to try. In this embodiment, as shown in FIG. 8, instead of the resistor R1 or R2, a circuit of a resistor and a switch connected in series to the resistor is connected in parallel. This shows that the more switches that are turned on, the lower the resistance value corresponding to the resistor R1 or R2. This switch can also be realized by a PMOS and NMOS transistor, or a complementary transistor using them.
As described above, according to the fifth embodiment of the driver circuit of the present invention, the resistor R1 or R2 is replaced with a circuit in which a circuit of a resistor and a switch connected in series to the resistor is connected in parallel. Thus, the resistance value corresponding to the resistor R1 or R2 can be easily varied by turning the switch ON / OFF.

Next, as a sixth embodiment of the present invention, the driver circuit according to any of the first to fifth embodiments includes a light emitting diode as a load, and an anode of the light emitting diode is connected to a resistor R2. The circuit is shown.
The current-voltage characteristics and current-luminance characteristics of the light-emitting diodes differ depending on each diode element, but the luminance is determined by the current value, so that a predetermined voltage is required to obtain a desired luminance. For this reason, in a configuration using a normal current mirror circuit (FIG. 27), a case where a transistor connected to the light emitting diode cannot perform a saturation operation (operates in a linear region) occurs. When the linear operation is performed, it is important that the ratio of the reference current and the load current does not change even when the power supply, the ground voltage, and the voltage between the light emitting diode terminals change.
In the first to fifth embodiments, there is no designation for the operation region of the transistors M3 and M4. For this reason, if the load does not require a terminal voltage higher than the power supply voltage, the reference current and the load current can be realized by the ratio of the reciprocal of the resistance value by setting the resistors R1 and R2 to a predetermined ratio.
As described above, according to the sixth embodiment of the driver circuit of the present invention, when a desired luminance is required in a current light-emitting element such as a light-emitting diode, the transistor M3 or M4 is activated depending on the voltage between the terminals. Although it may operate in the linear region, the reference current and the load current are controlled by setting the voltage between the terminals of the resistors R1 and R2 to the same value. Can be ignored. In addition, the operation region of the transistor M3 or M4 may be a linear region as described above, and therefore the power supply voltage can be set low, so that power consumption can be reduced compared to a normal current mirror circuit.

FIG. 9 is a diagram showing a driver circuit according to the seventh embodiment of the present invention.
In FIG. 9, two driver circuits described in the first embodiment are arranged. Each element constituting these two circuits is assumed to have the same kind and characteristic, and a symbol (') is attached to one of them. Further, the current generator IREF in the driver circuit described in the first embodiment is replaced with transistors M5 and M5 ′.
Referring to FIG. 9, the gate potentials of the transistors M5 and M5 ′ are generated by the current source I and the transistor M6. Since the gate terminals of the transistors M5 and M5 ′ are common, the same voltage is applied. As described above, since the elements constituting the two driver circuits in FIG. 9 are of the same type and characteristics, the currents flowing through the loads LOAD and LOAD ′ can take the same value. The ratio between the reference current (Ir1, Ir1 ′) and the load current (Ir2, Ir2 ′) is the ratio of the reciprocal of the resistance values of the resistors R1 (or R1 ′) and R2 (or R2 ′).
Incidentally, although two driver circuits described in the first embodiment are arranged in FIG. 9, the driver circuit according to any one of the first to sixth embodiments is replaced by only replacing the current generator IREF with one MOS transistor. The same argument can be made no matter how many are arranged.
As described above, according to the seventh embodiment of the driver circuit of the present invention, the load currents can all be made equal by arranging a plurality of driver circuits according to any one of the first to sixth embodiments in parallel. In a current light emitting element such as a diode, variation in light emission luminance is suppressed, and light emission without unevenness can be realized.

Next, as an eighth embodiment of the present invention, there is a printer or copying machine having the driver circuit of the seventh embodiment that drives the current supplied to the semiconductor laser.
In laser printers and laser copiers, the image density is determined by the brightness of the laser that irradiates the photosensitive band. In a laser printer or laser copying machine having such characteristics, when there are a plurality of semiconductor lasers driven by the driver circuit of the seventh embodiment, when the resistance values of the resistors corresponding to the resistors R1 and R2 are all equal, All semiconductor lasers can emit light with the same brightness. At that time, the ratio between the reference current and the load current is determined by the ratio between the resistors R1 and R2.

FIG. 10 is a diagram showing a basic configuration of a driver circuit according to the ninth embodiment of the present invention.
The purpose of this driver circuit is to control the current I2 flowing through the load to a desired value based on the current I1 flowing through the current source IREF. Since the variable resistors VR1 and VR2 have a common connection point A, the current values of the currents I1 and I2 are determined by the resistance values of the variable resistors VR1 and VR2 and the potentials of the connection points B and C. Further, if the potentials of the connection points B and C are the same value, the current values of the currents I1 and I2 can be determined only by the resistance values of the variable resistors VR1 and VR2. The resistance values of these variable resistors are determined based on the resistance value of the resistor R.
The controller A1 gives a control input G1 based on the potential difference between the connection points B and C. The control input G1 is connected to the control terminal of the voltage controlled current source IVCCS1, and the current flowing through the voltage controlled current source IVCCS1 is adjusted to control the potentials at the connection points B and C to be the same value.
The controller A2 gives a control input G2 based on the potential difference between the connection points B and D. The control input G2 is connected to the control terminals of the variable resistors VR1 and VR2, and the current flowing through the variable resistors VR1 and VR2 is adjusted to control the potentials at the connection points B and D to be the same value. The relationship between the resistance values of the resistor R and the variable resistors VR1 and VR2 is determined by the size of the current sources IREF and IMIR, the voltage control current sources IVCCS1 and IVCCS2, the resistor R and the variable resistors VR1 and VR2 in the configuration of FIG. The

FIG. 11 is a diagram showing a specific example 1 according to the ninth embodiment of the present invention.
In this specific example, the current source and variable resistor in FIG. 10 are replaced with MOS transistors. The current sources IREF and IMIR and the variable resistor are NMOS transistors, and the voltage controlled current source is a PMOS transistor. The gate terminals of the transistors M1 and M2 are connected in common, and the transistors M1 and M2, M3 and M4, and M5 and M6 have the same size.
In this electronic circuit device, a connection point between the drain terminal of the transistor M6 and the drain terminals of the transistors M3 and M4 is a connection point A, a connection point between the source terminal of the transistor M3 and the drain terminal of the transistor M1 is a connection point B, and a transistor M4. A connection point between the source terminal and the load LOAD is a connection point C, a connection point between the resistor R and the drain terminal of the transistor M2 is a connection point D, and a connection point between the drain terminal of the transistor M5 and the resistor R is a connection point E. . The connection points B and C are each connected to the input terminal of the differential amplifier A1, and the connection points B and D are each connected to the input terminal of the differential amplifier A2. In the differential amplifier A1, an output terminal, that is, a control input terminal is connected to the gate terminals of the transistors M5 and M6. In the differential amplifier A2, an output terminal, that is, a control input terminal is connected to the gate terminals of the transistors M3 and M4. It is characterized by being. These control input terminals are designated as connection points G1 and G2, respectively. Each differential amplifier functions as a circuit that feeds back a potential difference between the connection points B and C or the connection points B and D.

Here, consider a case where the feedback circuit is removed in the present embodiment. With this configuration, the potential at the connection point G1 or G2 is swept from the ground to the power supply voltage. When the potential of the connection point G1 or G2 is swept, it is assumed that the potential of the connection point that is not swept is fixed to an arbitrary potential. FIG. 12 is a graph regarding the potentials of the connection points B and C at this time (when the connection point G1 is swept), and FIG. 13 is a graph regarding the currents I1 and I2 flowing through the transistor M1 and the load LOAD (when the connection point G1 is swept). FIG. 14 shows a graph regarding the potentials of the connection points B and D (when the connection point G2 is swept), and FIG. 15 shows a graph regarding the currents I1 and I3 flowing through the transistors M1 and M2 (when the connection point G2 is swept).
From FIG. 12, it can be seen that the potentials at the connection points B and C, and from FIG.
Further, an intersection P1 exists in FIGS. The value of the connection point G1 at the intersection P1 is equal to Vg1. This is because when the connection point G1 takes Vg1, the potentials of the connection points B and C are equal, so that the drain terminals of the transistors M3 and M4 are connected in common at the connection point A, and the gate terminals are connected in common at the connection point G2. This is because the bias voltages of both transistors become equal, and the current I1 supplied from the transistor M1 and the current I2 flowing through the load LOAD have the same value.
In addition, it can be seen from FIG. 12 that convergence can be achieved by connecting the connection point B to the non-inverting input terminal and the connection point C to the inverting input terminal (the potentials of the connection points B and C are equal). Here, the differential amplifier A1 functions sufficiently within the operation range of each terminal used in the description.

On the other hand, FIG. 14 shows that the potential at the connection point B monotonously increases, whereas the potential at the connection point D always maintains a constant value. This is because the sweep was performed in a state where the potentials of the gate terminals of the transistors M2 and M5 having the function of changing the potential of the connection point D were kept constant.
FIG. 15 shows a waveform similar to that in FIG. 14 except that the gates and source terminals of the transistors M1 and M2 are connected in common, so that the current flowing through each transistor is the potential of the drain terminal. Because it depends on.
The description of the principle that the currents flowing in the transistors M1 and M2 are equal is the same as the principle that the currents flowing in the transistor M1 and the load LOAD are equal, and thus the description thereof is omitted.
From FIG. 14, it can be seen that convergence can be achieved by connecting the connection point B to the inverting input terminal and the connection point D to the non-inverting input terminal (the potentials of the connection points B and D are equal). Here, the differential amplifier A2 functions sufficiently within the operation range of each terminal used in the description.

As described above, in the first specific example according to the first embodiment of the driver circuit according to the present invention, the drain terminals of the transistors M3 and M4 connected to the transistor M1 side and the load LOAD side are made common, and the source terminals are different. By controlling so as to take the same value by a feedback circuit including the dynamic amplifier A1, the currents flowing in both transistors are made equal. The principle of equalizing the currents flowing through the transistors M1 and M2 is also the same.
In this configuration, since the number of transistors M6 connected to the power source is one in the first place, the occurrence of power source variations can be eliminated. That is, since the current is directly controlled rather than controlling the bias of the transistor, both current values can be made equal with high accuracy. Even when the drain-source voltage of the transistor M6 is low (when operating in the linear region), the current can be mirrored at a predetermined ratio. This also means that the power supply voltage can be kept low, which is effective in reducing power consumption.

On the other hand, since the transistors M3 and M4 are handled as variable resistors, the influence of the individual variation is likely to appear. For example, only the size of the transistor M2 is doubled that of the transistor M1 with this configuration (the current flowing through the transistor M2). To be twice the current flowing through M1), the current flowing through the resistor R and the transistors M2, M5, and M6 can be matched. Further, since the potentials of the connection points A and E and the potentials of the connection points B and D are equal, the resistance value of the resistor R and the transistors M3 and M4 can be matched. That is, the resistance value of the transistors M3 and M4 can be determined by referring to the resistance value of the resistor R, so that the influence of individual variation can be canceled.
In addition, by using a variable resistor, the voltage applied to the variable resistor can be adjusted even when the current value is large (actually, the resistor R is adjusted), and the voltage fluctuation within a range where the differential amplifier or the like functions sufficiently is suppressed. It is also possible.
However, as can be seen from FIGS. 12 and 13, in this specific example, when the potential at the connection point G1 takes the power supply voltage, the intersection point P2 always exists (a plurality of convergence points exist). In addition, since both the voltage in FIG. 12 and the current in FIG. 13 are monotonously decreasing, there is a possibility of having an intersection other than the intersections P1 and P2. This problem is solved in the tenth and subsequent embodiments.

Next, as a specific example 2 of the ninth embodiment of the present invention, a variable resistance VR2 is replaced by a variable voltage control current source having a common bias and a variable control terminal having a common control terminal connected to the voltage control current source. A driver circuit is shown in which a plurality of circuits each having a resistor and a switch connected in series to the voltage controlled current source and the variable resistor are connected in parallel.
FIG. 16 is a diagram showing a circuit representing the variable resistance VR2 portion of specific example 2 according to the ninth embodiment of the present invention.
The driver circuit includes variable resistors VRp1 to VRpn (n is a positive integer) and switches S1 to Sn connected in series to voltage controlled current sources IVCCSp1 to IVCCSpn (n is a positive integer, and switches having the same name perform the same operation). Therefore, the current flowing through the load is varied.
In this specific example, as shown in FIG. 16, a circuit corresponding to the voltage controlled current source IVCCS1 and the variable resistor VR1 is connected in series instead of the variable resistor VR2. When the potentials of the connection points B and C are the same value by the differential amplifier A1, all the voltage control current sources and variable resistors included in the circuits connected in parallel include the voltage control current source IVCCS1 and The same bias voltage as that of the variable resistor VR1 is applied.
With this configuration, the ratio between the load current and the reference current can be easily varied by turning the switch on and off. Further, by adding the voltage controlled current sources IVCCSp1 to IVCCSpn, as shown in FIG. 8, the resistors corresponding to the variable resistor VR2 are arranged in parallel, and each of them has a switch. Since the change in VR2 is small, it is possible to suppress a change in the bias point of the entire circuit. Furthermore, when there is one current source corresponding to the voltage controlled current source IVCCS1, it may be impossible to realize depending on the size of the reference current and the load current. In order to increase the degree, the configuration of this example is useful. This switch can also be realized by PMOS and NMOS transistors, or complementary transistors using them.

Next, as specific example 3 of the ninth embodiment of the present invention, in the driver circuit of specific example 2 according to the ninth embodiment, there is no switch directly connected to the voltage control current source and the variable resistor, and voltage control is performed. The driver circuit which tries to give the function equivalent to the specific example 2 by providing a switch in the control terminal of a current source and a variable resistor is shown. Further, when the switch is OFF so that the control terminal does not float by the switch, a predetermined bias is applied to the control terminal so that no current flows through each element.
FIG. 17 is a diagram illustrating a circuit representing the variable resistor VR2 portion of specific example 3 according to the ninth embodiment of the invention.
In the specific example 2, this driver circuit uses a transistor M7 as a voltage-controlled current source and a transistor M8 as a variable resistor. The two switches connected in series with the voltage-controlled current source and the variable resistor are removed, and complementary switches are provided at the control terminals (gate terminals of the transistors M7 and M8) of each element (so that the EN1 and EN2 signals are Complementary signal). A configuration in which the circuit shown in FIG. 17 is connected in parallel is a form of this example. However, it is assumed that the EN1 and EN2 signals are independent.

When a current is passed through the transistors M7 and M8 shown in FIG. 17, EN1 is set to H (V _dd ) and EN2 is set to L (V _ss ), so that the gate terminals of the transistors M7 and M8 are connected to the differential amplifiers A1 and A2. To the control input (connection points G1 and G2). On the other hand, by setting EN1 to L and EN2 to H, the drains and sources of the transistors M9 and M10 become conductive, and H is added to the gate terminal of the transistor M7 and L is added to the gate terminal of the transistor M8. The current flowing through the transistors M7 and M8 can be turned off. At the same time, the control inputs of the differential amplifiers A1 and A2 are turned off. By doing so, the gate terminals of the transistors M7 and M8 can be turned off without floating.
In addition, the dynamic range of the potentials of the connection points A and C is wider and the dynamic range of the current values of the load current and the reference current is wider than when a switch is installed on the path of the load current as shown in FIG. Can do.

Next, as specific example 4 of the ninth embodiment of the present invention, when the current flowing through the transistors M7 and M8 is turned off in the driver circuit of specific example 3 according to the ninth embodiment, the gate terminal of the transistor A driver circuit in which H is set to H (power supply, V _dd ) or L (ground, V _ss ) between V _dd and connection point G1 or between connection point G2 and connection point C is shown.
FIG. 18 is a diagram illustrating a circuit representing the variable resistor VR2 portion of specific example 4 according to the ninth embodiment of the invention.
In this specific example, the transistor M9 and the switch SW1 (or the transistor M10 and the switch SW2) in the configuration of the specific example 3 are replaced with the buffer B1 (or the buffer B2).
A characteristic of the buffer is that its output becomes a potential of H or L connected to the buffer. In this specific example, this characteristic is used, and the output of the buffer is connected to the gate terminals of the transistors M7 and M8. It deals with a given control input or a potential at which the current is turned off. Further, in order to turn off the current flowing through the transistors M7 and M8, it is sufficient that the gate-source voltage of the transistor is zero. Therefore, the current can be sufficiently turned off even with the configuration shown in FIG.
The signals EN1, EN2, EN1 ′, and EN2 ′ are intensified by the buffer. The EN1 and EN2 signals have voltage fluctuations between the power supply (V _dd ) and the ground (V _ss ), but the EN1 ′ and EN2 ′ signals are between the power supply (V _dd ) and the connection point G1 or between the connection point G2 and the connection point C. Therefore, the power consumption generated in the buffer can be reduced as compared with the case where the EN1 and EN2 signals are handled.

FIG. 19 is a diagram showing a basic configuration of a driver circuit according to the tenth embodiment of the present invention.
The purpose of this driver circuit is to control the current I2 to a desired value based on the current I1 flowing through the current source IREF. Since the variable resistors VR1 and VR2 have a common connection point A, the current values of the currents I1 and I2 are determined by the resistance values of the variable resistors VR1 and VR2 and the potentials of the connection points B and C. Further, if the potentials of the connection points B and C are the same value, the current values of the currents I1 and I2 can be determined only by the resistance values of the variable resistors VR1 and VR2. The resistance values of these variable resistors are determined based on the resistance value of the resistor R.
The controller A1 gives a control input G1 based on the potential difference between the connection points B and C. The control input G1 is connected to the gate terminals of the MOS transistors MR1 and MR2, and the current flowing through the MOS transistor MR1 is adjusted to control the potentials at the connection points B and C to be the same value.
The controller A2 gives a control input G2 based on the potential difference between the connection points D and E. The control input G2 is connected to the control terminals of the variable resistors VR1 and VR2, and the current flowing through the variable resistors VR1 and VR2 is adjusted to control the potentials of the connection points D and E to be the same value. In the configuration of FIG. 19, the relationship between the resistance value of the resistor R and the variable resistors VR1 and VR2 is as follows: current sources IREF and IMIR, voltage controlled current sources IVCCS1 and IVCCS2, resistor R and variable resistors VR1 and VR2, MOS transistors MR1 and MR2. It is determined by the size of
Further, an arbitrary fixed potential is applied to the control terminals of the voltage controlled current sources IVCCS1 and IVCCS2.

FIG. 20 shows a specific example 1 according to the tenth embodiment of the present invention.
In this specific example, the current source and variable resistor in FIG. 19 are replaced with MOS transistors. The current sources IREF and IMIR and the variable resistors VR1 and VR2 are NMOS transistors, and the voltage control current source is a PMOS transistor. The gate terminals of the transistors M1 and M2 are connected in common, and the transistors M1 and M2, M3 and M4, and M5 and M6 have the same size.
In this electronic circuit device, a connection point between the drain terminal of the transistor M8 and the drain terminals of the transistors M3 and M4 is a connection point A, a connection point between the source terminal of the transistor M3 and the source terminal of the transistor M5 is a connection point B, and the transistor M4. A connection portion between the source terminal of the transistor LOAD and the load LOAD is a connection point C, a connection portion between the drain terminal of the transistor M5 and the drain terminal of the transistor M1 is a connection point D, and a connection portion between the drain terminal of the transistor M6 and the drain terminal of the transistor M2. Is a connection point E, a connection point between the resistor R and the source terminal of the transistor M6 is a connection point F, and a connection point between the drain terminal of the transistor M7 and the resistor R is a connection point G. The connection points B and C are each connected to the input terminal of the differential amplifier A1, and the connection points D and E are respectively connected to the input terminal of the differential amplifier A2. It is assumed that the gate terminals of the transistors M7 and M8 are fixed to a predetermined potential by a current mirror circuit or the like. In the differential amplifier A1, an output terminal, that is, a control input terminal is connected to the gate terminals of the transistors M5 and M6. In the differential amplifier A2, an output terminal, that is, a control input terminal is connected to the gate terminals of the transistors M3 and M4. It is characterized by that. Let these connection points be connection points G1 and G2, respectively. Each differential amplifier functions as a circuit that feeds back a potential difference between the connection points B and C or the connection points D and E.

Here, consider a case where the feedback circuit is removed in the present embodiment. With this configuration, the potential at the connection point G1 or G2 is swept from the ground to the power supply voltage. When the potential of the connection point G1 or G2 is swept, it is assumed that the potential of the connection point that is not swept is fixed to an arbitrary potential. FIG. 21 is a graph regarding the potentials of the connection points B and C at this time (when the connection point G1 is swept), and FIG. 22 is a graph regarding the currents I1 and I2 flowing through the transistor M1 and the load LOAD (when the connection point G1 is swept). FIG. 23 shows a graph regarding the potentials of the connection points D and E (when sweeping the connection point G2), and FIG. 24 shows a graph regarding the currents I1 and I3 flowing through the transistors M1 and M2 (when sweeping the connection point G2).
When looking at FIG. 21, the potentials of the connection points B and C increase monotonically, while when looking at FIG. 22, the current I1 flowing through the transistor M1 decreases monotonously and the current I2 flowing through the load LOAD increases monotonously. I understand.

Further, in FIG. 21 and FIG. 22, there is an intersection point P4. The value of the connection point G1 at the intersection P4 is equal to Vg4. This is because when the connection point G1 takes Vg4, the potentials of the connection points B and C are equal, so the drain terminals of the transistors M3 and M4 are connected in common at the connection point A, and the gate terminals are connected in common at the connection point G2. This is because the bias voltages of both transistors become equal, and the current I1 supplied from the transistor M1 and the current I2 flowing through the load LOAD have the same value.
In addition, it can be seen from FIG. 21 that convergence can be achieved by connecting the connection point B to the inverting input terminal and the connection point C to the non-inverting input terminal (the potentials of the connection points B and C are equal). Here, the differential amplifier A1 functions sufficiently within the operation range of each terminal used in the description.

On the other hand, FIG. 23 shows that the potential at the connection point D monotonously increases, whereas the potential at the connection point E always maintains a constant value. This is because the sweep was performed while the potentials of the gate terminals of the transistors M2, M6, and M7 having the function of changing the potential of the connection point E were kept constant.
FIG. 24 shows a waveform similar to that in FIG. 23. This is because the gates and source terminals of the transistors M1 and M2 are connected in common, so that the current flowing through each transistor is the potential of the drain terminal. Because it depends on.
The description of the principle that the currents flowing in the transistors M1 and M2 are equal is the same as the principle that the currents flowing in the transistor M1 and the load LOAD are equal, and thus the description is omitted.
It can be seen from FIG. 23 that convergence can be achieved by connecting the connection point D to the inverting input terminal and the connection point E to the non-inverting input terminal (the potentials of the connection points D and E are equal). Here, the differential amplifier A2 functions sufficiently within the operation range of each terminal used in the description.

As described above, in the first specific example according to the tenth embodiment of the driver circuit according to the present invention, the drain terminals of the transistors M3 and M4 connected to the transistor M1 side and the load LOAD side are shared, and the source terminals are different. By controlling so as to take the same value by a feedback circuit including the dynamic amplifier A1, the currents flowing in both transistors are made equal. The principle of equalizing the currents flowing through the transistors M1 and M2 is also the same.
In this configuration, since the number of transistors M8 connected to the power source is one in the first place, the occurrence of power source variations can be eliminated. That is, since the current is directly controlled rather than controlling the bias of the transistor, both current values can be made equal with high accuracy. Further, even when the drain-source voltage of the transistor M8 is low (when operating in the linear region), the current can be mirrored at a predetermined ratio. This also means that the power supply voltage can be kept low, which is effective in reducing power consumption.

On the other hand, since the transistors M3 and M4 are handled as variable resistors, the influence of the individual variation is likely to appear. For example, only the size of the transistor M2 is doubled that of the transistor M1 with this configuration (the current flowing through the transistor M2). To be twice the current flowing through M1), the current flowing through the resistor R and the transistors M2, M6, M7, and M8 can be matched. Further, since the potentials of the connection points A and G and the potentials of the connection points B and F are equal, the resistance values of the resistor R and the transistor M3 can be matched. That is, the resistance value of the transistors M3 and M4 can be determined by referring to the resistance value of the resistor R, so that the influence of individual variation can be canceled.
In addition, by using a variable resistor, the voltage applied to the variable resistor can be adjusted even when the current value is large (actually, the resistor R is adjusted), and the voltage fluctuation within a range where the differential amplifier or the like functions sufficiently is suppressed. It is also possible.
Furthermore, when the value of the control input terminal G1 is changed, in the ninth embodiment, the intersection point P2 always occurs in addition to the intersection point P1, but in this embodiment, the current value I1 supplied by the transistor M1 and the load Since the direction of change (increase or decrease) of the flowing current value I2 is contradictory, if there is Vg4 in which the potentials of the connection points B and C have the same value, it can be limited to only one (only the intersection point P4).
In this embodiment, the same configurations as those of the specific examples 2 to 4 of the ninth embodiment are possible. However, the same effect and principle can be obtained, and a description thereof will be omitted.

FIG. 25 is a diagram showing a basic configuration of a driver circuit according to the eleventh embodiment of the present invention. The purpose of this driver circuit is to control the current I2 to a desired value based on the current I1 flowing through the current source IREF.
Since the variable resistors VR1 and VR2 have a common connection point A, the current values of the currents I1 and I2 are determined by the resistance values of the variable resistors VR1 and VR2 and the potentials of the connection points B and C. Further, if the potentials of the connection points B and C are the same value, the current values of the currents I1 and I2 can be determined only by the resistance values of the variable resistors VR1 and VR2. The resistance values of these variable resistors are determined based on the resistance value of the resistor R.
The controller A1 gives a control input G1 based on the potential difference between the connection points B and C. The control input G1 is connected to the gate terminals of the MOS transistors MR1 and MR2, and the current flowing through the MOS transistor MR1 is adjusted to control the potentials at the connection points B and C to be the same value.
The controller A2 gives a control input G2 based on the potential difference between the connection points D and E. The control input G2 is connected to the control terminals of the variable resistors VR1 and VR2, and the current flowing through the variable resistors VR1 and VR2 is adjusted to control the potentials of the connection points D and E to be the same value. In the configuration of FIG. 25, the relationship between the resistance value of the resistor R and the variable resistors VR1 and VR2 is as follows: current sources IREF and IMIR, voltage controlled current sources IVCCS1 and IVCCS2, resistor R and variable resistors VR1 and VR2, MOS transistors MR1 and MR2. It is determined by the size of
The control terminals of the voltage controlled current sources IVCCS1 and IVCCS2 are connected to a connection point between the MOS transistor MR1 and the current source IREF.

FIG. 26 is a diagram showing a specific example 1 according to the eleventh embodiment of the present invention.
In this embodiment, the same configurations as those of the first to fourth specific examples of the tenth embodiment are possible, but the effects and the principles thereof are the same, and the description thereof is omitted.
Next, as a twelfth embodiment of the present invention, the driver circuits of Embodiments 9 to 11 include a light emitting diode as a load, and an anode of the light emitting diode is connected to a variable resistor VR2. A driver circuit is shown.
The current-voltage characteristics and current-luminance characteristics of the light-emitting diodes differ depending on each diode element, but the luminance is determined by the current value, so that a predetermined voltage is required to obtain a desired luminance. For this reason, in a configuration using a normal current mirror circuit (FIG. 27), a case where a transistor connected to the light emitting diode cannot perform a saturation operation (operates in a linear region) occurs. When the linear operation is performed, it is important that the ratio of the reference current and the load current does not change even with respect to power supply, ground voltage, and voltage variation between light emitting diode terminals.

In the specific examples of the ninth to eleventh embodiments, the operation region of all the transistors is not specified. For this reason, if the load does not require a terminal voltage higher than the power supply voltage, the current values of the reference current and the load current can be realized by the ratio of the reciprocal of the resistance value by setting the variable resistors VR1 and VR2 to a predetermined ratio. .
As described above, according to the fourth embodiment of the driver circuit of the present invention, when a desired luminance is required in a current light emitting element such as a light emitting diode, the transistor is in a linear region depending on the voltage between the terminals. Although it may operate, the reference current and the load current are controlled by setting the voltage between the terminals of the variable resistors VR1 and VR2 to the same value, so that the influence due to the voltage variation between the light emitting diode terminals can be ignored. Further, the influence of the power supply and ground voltage fluctuations on the variable resistors VR1 and VR2 is also canceled by referring to the resistor R and determining the resistance value of the variable resistor.
As described above, the operation region of the transistor may be a linear region, so that the power supply voltage can be set low, so that power consumption can be reduced as compared with a normal current mirror circuit.

Next, a driver circuit according to a thirteenth embodiment of the present invention will be described.
It is assumed that a plurality of driver circuits described in the twelfth embodiment are arranged, and each element constituting these circuits is of the same type and characteristics. In addition, it is assumed that the gate potential of the transistor TR1 is generated by a current mirror circuit (in the case of being configured by an NMOS transistor) as shown in FIG. 27, and the gate terminal is connected to Vin of each circuit.
As described above, since each element constituting each driver circuit is composed of the same type and characteristics, the current flowing through each load LOAD can take the same value. The ratio between the reference current I1 and the load current I2 is a ratio of the reciprocal of the resistance values of the variable resistors VR1 and VR2.
As described above, according to the thirteenth embodiment of the driver circuit according to the present invention, the load currents can all be made equal by arranging a plurality of driver circuits described in the twelfth embodiment in parallel. In the light emitting element, variation in light emission luminance is suppressed, and light emission without unevenness can be realized.

Next, as a fourteenth embodiment of the present invention, there is a printer or copying machine having the driver circuit of the thirteenth embodiment that drives a current supplied to a semiconductor laser.
In laser printers and laser copiers, the image density is determined by the brightness of the laser that irradiates the photosensitive band. When a laser printer or laser copying machine having such characteristics has a plurality of semiconductor lasers driven by the driver circuit of the thirteenth embodiment, when the resistance values of the variable resistors VR1 and VR2 are all equal, All can emit light with the same brightness. At that time, the ratio between the reference current and the load current can be determined by the ratio between the variable resistors VR1 and VR2.

1 is a diagram illustrating a driver circuit according to a first embodiment of the present invention. It is a figure which shows the graph regarding the electric potential of the connection points B and C. FIG. It is a figure which shows the graph regarding the electric current (Ir1, Ir2) which flows into the electric current generator IREF and load LOAD. It is a figure which shows the driver circuit which concerns on the 2nd Embodiment of this invention. It is a figure which shows the graph regarding the electric potential of the connection points B and C. FIG. It is a figure which shows the graph regarding the electric current (Ir1, Ir2) which flows into the electric current generator IREF and load LOAD. It is a figure which shows the driver circuit which concerns on the 3rd Embodiment of this invention. It is a figure which shows the circuit showing resistance R1 or R2 of Embodiment 1 thru | or 4 which concerns on the 5th Embodiment of this invention. It is a figure which shows the driver circuit which concerns on the 7th Embodiment of this invention. It is a figure which shows the basic composition of the driver circuit based on the 9th Embodiment of this invention. It is a figure which shows the specific example 1 which concerns on the 9th Embodiment of this invention. It is a figure which shows the graph regarding the electric potential of the connection points B and C. FIG. It is a figure which shows the graph regarding the electric currents I1 and I2 which flow into the transistor M1 and load LOAD. It is a figure which shows the graph regarding the electric potential of the connection points B and D. FIG. It is a figure which shows the graph regarding the electric currents I1 and I3 which flow into the transistors M1 and M2. It is a figure which shows the circuit showing the variable resistance VR2 part of the specific example 2 which concerns on the 9th Embodiment of this invention. It is a figure which shows the circuit showing the variable resistance VR2 part of the specific example 3 which concerns on the 9th Embodiment of this invention. It is a figure which shows the circuit showing the variable resistance VR2 part of the specific example 4 which concerns on the 9th Embodiment of this invention. It is a figure which shows the basic composition of the driver circuit based on the 10th Embodiment of this invention. It is a figure which shows the specific example 1 which concerns on the 10th Embodiment of this invention. It is a figure which shows the graph regarding the electric potential of the connection points B and C. FIG. It is a figure which shows the graph regarding the electric currents I1 and I2 which flow into the transistor M1 and load LOAD. It is a figure which shows the graph regarding the electric potential of the connection points D and E. FIG. It is a figure which shows the graph regarding the electric currents I1 and I3 which flow into the transistors M1 and M2. It is a figure which shows the basic composition of the driver circuit based on the 11th Embodiment of this invention. It is a figure which shows the specific example 1 which concerns on the 11th Embodiment of this invention. It is a figure of a general current mirror circuit. It is a figure showing the relationship between drain current and the gate-source voltage.

Explanation of symbols

  R1, R2 resistance, IREF current generator, LOAD load, M3 transistor, A connection point, A1 differential amplifier

Claims (22)

A driver circuit for supplying a load with a predetermined ratio of load current to a reference current;
Reference current generating means for generating the reference current;
Current driving means for supplying current to the load and the reference current generating means, respectively,
The current driving means includes a first resistor provided on a reference current path connected to the reference current generating means;
A second resistor provided on a path of a load current connected to the load;
The difference between the voltage appearing at the reference current generating means side terminal of the first resistor applied to the first input terminal and the voltage appearing at the load side terminal of the second resistor applied to the second input terminal A dynamic amplifier;
A first transistor connected in common to the other ends of the first resistor and the second resistor and connected to a drain terminal;
A driver characterized in that an output terminal of the differential amplifier is connected to a gate terminal of the first transistor to feed back a potential difference between the first input terminal and the second input terminal. circuit. A driver circuit for supplying a load with a predetermined ratio of load current to a reference current;
Reference current generating means for generating the reference current;
Current driving means for supplying a current to a load and the reference current generating means, respectively,
The current driving means includes a first transistor having a drain terminal connected to the reference current generating means;
A first resistor provided on a reference current path connected to a source terminal of the first transistor;
A second resistor provided on a path of a load current connected to the load;
A voltage appearing at a connection point between the first resistor and the source terminal of the first transistor is applied to the first input terminal, and a voltage appearing at the load side terminal of the second resistor is applied to the second input terminal. A differential amplifier,
The other end of the first resistor and the second resistor are connected in common and connected to the drain terminal, and the gate terminal includes a second transistor to which a fixed potential is applied,
A driver circuit characterized in that the potential difference between the first input terminal and the second input terminal is fed back by connecting the output terminal of the differential amplifier to the gate terminal of the first transistor. . A driver circuit for supplying a load with a predetermined ratio of load current to a reference current;
Reference current generating means for generating the reference current;
Current driving means for supplying current to the load and the reference current generating means, respectively,
The current driving means includes
A first transistor having a drain terminal connected to the reference current generating means;
A first resistor provided on a reference current path connected to a source terminal of the first transistor;
A second resistor provided on a path of a load current connected to the load;
A voltage appearing at a connection point between the first resistor and the source terminal of the first transistor is applied to the first input terminal, and a voltage appearing at the load side terminal of the second resistor is applied to the second input terminal. A differential amplifier,
A second transistor having the other end of the first resistor and the second resistor connected in common and connected to a drain terminal, and a gate terminal connected to the drain terminal of the first transistor;
A driver characterized in that a potential difference between the first input terminal and the second input terminal is fed back by connecting an output terminal of the differential amplifier to a gate terminal of the first transistor. circuit.   4. The driver circuit according to claim 1, wherein the reference current and the load current are adjusted to a predetermined ratio by changing a ratio between the first resistor and the second resistor. 5. . The first resistor or the second resistor is constituted by a resistor circuit means in which a plurality of circuits each having a resistor having an arbitrary value and a switch connected in series with the resistor are connected in parallel.
The driver circuit according to claim 1, wherein each of the switches can be connected and disconnected independently.   6. The driver circuit according to claim 5, wherein the switch includes an NMOS transistor.   6. The driver circuit according to claim 5, wherein the switch includes a PMOS transistor.   6. The driver circuit according to claim 5, wherein the switch is a complementary switch using an NMOS transistor and a PMOS transistor.   The driver circuit according to claim 1, wherein the load includes a light emitting diode, and an anode of the light emitting diode is connected to the second resistor. A driver circuit for supplying a load with a predetermined ratio of load current to a reference current;
Current driving means for supplying current to a first current source for generating the load and a reference current;
A dummy circuit having a reference resistance,
The current driving means includes
First and second variable resistors whose resistance values change according to voltage values;
The first current source and the load, one of which is connected to ground,
The first variable resistor connected to the other end of the first current source is provided on a path of the reference current;
The second variable resistor connected to the other end of the load is provided on a path of the load current;
A potential appearing at a connection point between the first variable resistor and the first current source is applied to a first input terminal, and a potential appearing at a connection point between the second variable resistor and the load is applied to a second input terminal. A first differential amplifier;
A first voltage controlled current source connected at one end to a power source and connected at the other end to a terminal commonly connected to the other ends of the first variable resistor and the second variable resistor;
A second current source having one end connected to a reference resistor and the other end connected to ground;
A potential appearing at the connection point between the first variable resistor and the first current source is applied to the first input terminal, and a potential appearing at the connection point between the reference resistor and the second current source is applied to the second input terminal. A second differential amplifier,
A second voltage controlled current source having one end connected to the power source and the other end connected to the other end of the reference resistor;
The output terminal of the first differential amplifier is connected to the control terminals of the first voltage controlled current source and the second voltage controlled current source, so that the first input terminal of the first differential amplifier and the first differential amplifier The potential difference from the second input terminal is fed back,
The output terminal of the second differential amplifier is connected to the control terminal of the first variable resistor and the second variable resistor, whereby the first input terminal and the second input of the second differential amplifier. A driver circuit in which a potential difference from a terminal is fed back. A driver circuit for supplying a load with a predetermined ratio of load current to a reference current;
Current driving means for supplying current to a first current source for generating the load and a reference current;
A dummy circuit having a reference resistance,
The current driving means includes
First and second variable resistors whose resistance values change according to voltage values;
A first MOS transistor;
The first current source and the load, one of which is connected to ground,
The first MOS transistor having a drain terminal connected to the other end of the first current source is provided on a path of the reference current;
The first variable resistor is connected to a source terminal of the first MOS transistor, and the second variable resistor connected to the load is provided on a path of the load current,
A potential appearing at a connection point between the first variable resistor and the first MOS transistor is applied to a first input terminal, and a potential appearing at a connection point between the second variable resistor and the load is applied to a second input terminal. A first differential amplifier;
One end is connected to a power source, and the other end is composed of a first voltage controlled current source connected to a terminal commonly connected to the other ends of the first variable resistor and the second variable resistor,
The dummy circuit is
A second current source having both terminals connected to the drain terminal of the second MOS transistor and ground;
The reference resistor connected to the source terminal of the second MOS transistor;
A potential appearing at the connection point between the first MOS transistor and the first current source is applied to the first input terminal, and a potential appearing at the connection point between the second MOS transistor and the second current source is applied to the second input terminal. A second differential amplifier,
A second voltage controlled current source having one end connected to a power source and the other end connected to the other end of the reference resistor;
An arbitrary fixed potential is applied to a common control terminal of the first and second voltage controlled current sources,
By connecting the output terminal of the first differential amplifier to the gate terminals of the first and second MOS transistors, the potential difference between the first input terminal and the second input terminal of the first differential amplifier. Is returned,
The output terminal of the second differential amplifier is connected to the control terminals of the first and second variable resistors, so that the first input terminal and the second input terminal of the second differential amplifier are connected to each other. A driver circuit in which a potential difference is fed back.   12. The driver circuit according to claim 11, wherein the potential of the common control terminal of the first and second voltage controlled current sources is the same as that of the first input terminal of the second differential amplifier. A variable resistor with a common control terminal;
Resistor circuit means in which one or a plurality of circuits each having a variable resistor and a switch connected in series are connected in parallel is replaced with either the first variable resistor or the second variable resistor, respectively. ,
A voltage controlled current source having a common control terminal;
Current source means in which one or a plurality of circuits each having a switch connected in series with the voltage controlled current source are connected in parallel is installed in place of the first voltage controlled current source,
The driver circuit according to claim 10, wherein each of the switches can be turned on and off independently. Resistor circuit means in which one or a plurality of variable resistors having a common control terminal are connected in parallel is installed by replacing either or each of the first or second variable resistors,
Current source means in which one or a plurality of voltage controlled current sources having a common control terminal are connected in parallel is installed in place of the first voltage controlled current source,
The driver circuit according to any one of claims 10 to 12, wherein the state in which the variable resistor and the voltage-controlled current source do not conduct current is realized by a signal input to each control terminal.   15. The driver circuit according to claim 14, wherein a switch is connected in series to the control terminal of the variable resistor and the voltage controlled current source, and the control terminal has a power supply or ground potential when the switch is OFF. . When the dynamic range of the inverter or buffer that outputs a signal input to each control terminal of the variable resistance and voltage controlled current source is connected to the control terminal of the variable resistance, the inverter or buffer Determined by the voltage across the variable resistor,
15. The driver circuit according to claim 14, wherein when the inverter or the buffer is connected to a control terminal of the voltage controlled current source, it is determined by a voltage across the voltage controlled current source.   The driver circuit according to any one of claims 10 to 16, wherein the variable resistor or the voltage controlled current source is configured by a MOS transistor.   The driver circuit according to claim 10, wherein the switch is configured by a MOS transistor.   The driver circuit according to claim 10, further comprising: a light emitting diode as the load, wherein an anode of the light emitting diode is connected to the second variable resistor. An electronic circuit device in which a plurality of driver circuits according to any one of claims 1 to 9 are arranged.
A driver circuit, wherein the current source is composed of one MOS transistor, the MOS transistors have the same size and characteristics, and are connected by a common gate terminal. An electronic circuit device in which a plurality of driver circuits according to any one of claims 10 to 19 are arranged.
A driver circuit, wherein each of the first current sources includes a current mirror circuit, and the size and characteristics of MOS transistors included in the current mirror circuit are equal.   22. A current driving device for uniformly controlling the luminance of each semiconductor laser by making all currents supplied to each semiconductor laser uniform, comprising the driver circuit according to claim 20 or 21. Electronic circuit device.

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