JP2010067876A - Chip type solid electrolytic capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip type solid electrolytic capacitor capable of reducing cost, and having high reliability in relation to connection of a negative electrode without causing deterioration of a lead frame terminal even by a reflow process. <P>SOLUTION: The chip type solid electrolytic capacitor includes a solid electrolytic capacitive element 1 comprising: a positive electrode body with a positive electrode lead 20 led out therefrom; an oxide film on a surface thereof; a solid electrolyte layer formed on top of it; and a negative electrode extraction layer located on top of it and comprising a graphite layer and a silver paste layer. In the chip type solid electrolytic capacitor, a plate-like lead frame terminal 34 is connected to the negative electrode extraction layer by a conductive adhesive 3, base plated layers are formed on both surfaces of the lead frame terminal 34, a second plated layer 5 formed of a noble metal is formed only on a surface in contact with the conductive adhesive 3 on top of it, and, on other parts identical to that surface and almost over the whole of the back surface thereof, a tin-plated layer 6 is formed on the base plated layer so as not to contact the second plated layer 5 across a region 10 therefrom. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a chip-type solid electrolytic capacitor using a valve action metal such as tantalum or niobium, and more particularly to an electrode terminal thereof.

  In the chip type solid electrolytic capacitor, an oxide film is formed on the surface of an anode body made of a valve metal from which an anode lead is drawn, a solid electrolyte layer is formed on the oxide film, a graphite layer and a solid electrolyte layer are formed on the solid electrolyte layer. A cathode lead layer made of a silver paste layer is formed to produce a solid electrolytic capacitor element, plate-like lead frame terminals are connected to the anode lead and cathode lead layer, and the whole is molded with an exterior resin.

  For example, in a solid electrolytic capacitor using tantalum, an anode body is used in which a tantalum wire is embedded in a porous body obtained by molding and sintering tantalum powder for the purpose of anode extraction. A tantalum oxide film is formed on the surface of the anode body by an anodic oxidation method (chemical conversion method), and this oxide film becomes a dielectric layer of the electrolytic capacitor. A solid electrolyte layer made of, for example, manganese dioxide or a conductive polymer is formed thereon, and a cathode layer is formed by further forming a graphite layer or a silver paste layer thereon to obtain a solid electrolytic capacitor element.

  FIG. 7 is a cross-sectional view showing an example of the conventional chip-type solid electrolytic capacitor. In the solid electrolytic capacitor element 1, the anode lead 20 is connected to the anode side lead frame terminal 4 by welding in order to obtain electrical connection with the outside, and the cathode lead layer is connected to the cathode side lead frame terminal by the conductive adhesive 3. 4 and finally molded by the exterior resin 2.

  FIG. 8 is an enlarged cross-sectional view of a conventional lead frame terminal 4. Conventionally, as shown in FIG. 8, in the lead frame terminal 4, a nickel plating layer is formed on both surfaces of the base material 41 as a base plating layer 42 for preventing corrosion and preventing diffusion of the tin plating layer into the base material. On top of that, a material having a tin plating layer 6 which is a low melting point metal having a melting point of 232 ° C. is widely used. However, since the tin plating layer 6 is melted by the reflow process at the time of soldering at 260 ° C. or higher, a gap may be formed at the interface between the conductive adhesive 3 and the lead frame terminal 4.

  In order to solve this problem, in recent years, instead of a tin plating layer, a gold plating layer (melting point 1064 ° C.) which is a high melting point metal or a plating layer made of palladium (melting point 1555 ° C.)-Gold is formed on the underlying plating layer. The forming technique is known.

  Patent Document 1 discloses a technique for forming a gold plating layer only on one side of a lead frame terminal in order to reduce a plating layer formation region using a refractory metal.

JP 2003-124074 A

  As described above, in the conventional technology using a tin plating layer for the lead frame terminal, a gap is generated at the interface between the conductive adhesive and the lead frame, and if moisture enters the gap, corrosion may occur at the interface. There is a problem that it is difficult to obtain high reliability with respect to the connection of the cathode electrode.

  In addition, when a plating layer made of gold or palladium-gold is formed in place of the tin plating layer, the above problem can be solved, but the conductive adhesive does not affect the reliability of the connection portion. Since a plating layer made of these metals is formed in a region other than the region in contact with the agent, the lead frame terminal is expensive. Further, even when a plating layer such as gold is formed only on one side of the lead frame terminal as in Patent Document 1, the cost reduction effect is not sufficient.

  In order to improve this, it is conceivable to form a plating layer made of gold or palladium-gold only in the region where the conductive adhesive is in contact, and to form a tin plating layer in the other region. When tin is melted by the treatment, there is a problem that tin and gold are alloyed and the portion becomes a brittle metal.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a chip-type solid electrolytic capacitor that can be reduced in cost, has high reliability with respect to connection of a cathode electrode, and does not deteriorate lead frame terminals even by reflow processing.

  In order to solve the above problems, a chip-type solid electrolytic capacitor according to the present invention includes an anode body made of a valve metal from which an anode lead is drawn, an oxide film formed on the surface of the anode body, and an oxide film on the oxide film. It has a solid electrolytic capacitor element composed of a formed solid electrolyte layer and a cathode lead layer composed of a graphite layer and a silver paste layer formed on the solid electrolyte layer, and the plate-like lead frame terminal is conductive In a chip-type solid electrolytic capacitor connected to the cathode lead layer by an adhesive, a first plating layer serving as a base is formed on the entire surface of both surfaces of the lead frame terminal, and the conductivity on the first plating layer A second plating layer made of a noble metal is formed only on the surface in contact with the adhesive.

  Further, tin is formed on the first plating layer only on at least a part of a portion of the lead frame where the second plating layer is not formed on the same surface as the second plating layer is formed. A plating layer may be formed.

  In addition, at least a part of a portion of the lead frame on which the second plating layer is formed and the second plating layer of the lead frame are not formed. A tin plating layer may be formed on the first plating layer on at least a part of the back surface of the formed surface.

  In the above case, it is desirable that the region where the second plating layer is formed and the region where the tin plating layer is formed are not in contact with each other.

  Moreover, it has exterior resin which covers the said solid electrolytic capacitor element, and the area | region where neither said 2nd plating layer nor said tin plating layer is formed may exist only in the inside of said exterior resin.

  In addition, as the noble metal constituting the second plating layer, generally, eight kinds of metals such as gold, silver, platinum, palladium, rhodium, iridium, ruthenium, and osmium are used, but are practically suitable for the present invention. Among these, metals other than iridium, ruthenium and osmium and alloys thereof are included. In addition, the first plating layer serving as the base is formed for preventing corrosion and preventing diffusion of the second plating layer to the base material.

  According to the present invention, in the lead frame terminal of the chip-type solid electrolytic capacitor, in order to form the noble metal plating layer only in the region in contact with the conductive adhesive used for the connection of the cathode electrode with the solid electrolytic capacitor element, It is possible to achieve both the effect of increasing the reliability of the connection of the cathode electrode and the effect of being able to be manufactured at a low cost. Furthermore, when the tin plating layer is formed outside the region where the noble metal plating layer is formed, the noble metal plating layer and the tin plating layer are not in contact with each other, and the underlying plating layer is exposed between the two plating regions. By providing such a region, tin melted by the reflow process does not penetrate into the region of the gold plating layer, so that there is an effect of preventing tin and gold from alloying and leading to weakening of the lead frame terminal.

  According to the present invention, it is possible to obtain a chip-type solid electrolytic capacitor that can be reduced in cost, has high reliability with respect to the connection of the cathode electrode, and does not deteriorate lead frame terminals even by reflow processing.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a first embodiment of a chip-type solid electrolytic capacitor according to the present invention. In FIG. 1, as in the prior art, an anode body made of a valve metal from which an anode lead 20 is drawn, an oxide film formed on the surface of the anode body, and a solid electrolyte layer formed on the oxide film, , Having a solid electrolytic capacitor element 1 composed of a graphite lead layer formed of a graphite layer and a silver paste layer formed on the solid electrolyte layer, and a plate-like lead frame terminal 14 is drawn into the cathode by a conductive adhesive. Connected to the layer. The conductive adhesive 3 used for connecting the exterior resin 2, the lead frame terminal 14 and the cathode electrode is the same as the conventional one. FIG. 2 is an enlarged cross-sectional view of the lead frame terminal 14, and a base plating layer 42 is formed as a first plating layer on a base material 41 on both surfaces of the lead frame terminal 14 as in the prior art.

  However, in the present embodiment, the second plating layer 5 made of a gold plating layer or palladium-gold is formed on the base plating layer 42 in a region in contact with the conductive adhesive. The base plating layer 42 is exposed on the surface of the other lead frame terminals 4.

  FIG. 3 is a cross-sectional view showing a second embodiment of the chip-type solid electrolytic capacitor according to the present invention. 3, the solid electrolytic capacitor element 1 is the same as that of the first embodiment shown in FIG. 1, and a plate-like lead frame terminal 24 is connected to the cathode lead layer by the conductive adhesive 3. It has exterior resin 2. FIG. 4 is an enlarged cross-sectional view of the lead frame terminal 24. A base plating layer 42 is formed as a first plating layer on the base material 41 on both surfaces of the lead frame terminal 24 as in the conventional case.

  However, in the present embodiment, the second plating layer 5 made of a gold plating layer or palladium-gold is formed on the base plating layer 42 in the region in contact with the conductive adhesive, and the second plating layer 5 The tin plating layer 6 is formed on the base plating layer 42 only on a part of the same surface as the surface where the second plating layer 5 is not formed, and on the opposite side of the lead frame terminal 24. The surface plating layer 42 is exposed on this surface.

  Further, the region where the second plating layer 5 is formed and the region where the tin plating layer 6 is formed are not in contact with each other, and the underlying plating layer 42 is exposed between the two regions 11.

  FIG. 5 is a cross-sectional view showing a third embodiment of the chip-type solid electrolytic capacitor according to the present invention. 5, the solid electrolytic capacitor element 1 is the same as that of the first embodiment shown in FIG. 1, and a plate-like lead frame terminal 34 is connected to the cathode lead layer by the conductive adhesive 3. It has exterior resin 2. FIG. 6 is an enlarged cross-sectional view of the lead frame terminal 34, and a base plating layer 42 is formed as a first plating layer on the base material 41 on both surfaces of the lead frame terminal 34 as in the prior art.

  However, in the present embodiment, the second plating layer 5 made of a gold plating layer or palladium-gold is formed on the base plating layer 42 in the region in contact with the conductive adhesive, and the second plating layer 5 A portion of the same surface as the surface on which the second plating layer 5 is not formed and a part of the back surface of the surface on which the second plating layer 5 of the lead frame terminal 24 is formed are substantially the base. A tin plating layer 6 is formed on the plating layer 42.

  Further, the region where the second plating layer 5 is formed and the region where the tin plating layer 6 is formed are not in contact with each other, and the underlying plating layer 42 is exposed between the two regions.

  Further, in the present embodiment, the region 10 where the base plating layer 42 in which neither the second plating layer 5 nor the tin plating layer 6 is formed is covered with the exterior resin 2 and exists only in the interior thereof. ing.

  Next, a specific example of the chip-type solid electrolytic capacitor of the third embodiment will be described. An anode body in which a tantalum wire is embedded in a porous body obtained by molding and sintering tantalum powder is used. A tantalum oxide film is formed on the surface of the anode body by anodic oxidation. A solid electrolyte layer made of a conductive polymer is formed thereon, and a cathode lead layer made of a graphite layer and a silver paste layer is further formed thereon to obtain the solid electrolytic capacitor element 1.

  An iron-nickel alloy is used for the base material 41 of the lead frame terminal 34, and a nickel plating layer of 0.5 μm is formed as the base plating layer 42. Thereafter, a mask is applied to a region other than the region in contact with the conductive adhesive when the chip-type solid electrolytic capacitor is molded, and a gold plating layer is formed to a thickness of 0.1 μm. Next, a mask is applied to the gold-plated region to form a tin plating layer 6 having a thickness of 3 μm. At this time, the region 10 where the base plating layer 42 is exposed is obtained by masking the gold plating layer region and the tin plating layer region with a gap of 0.5 mm or more.

  The anode lead 20 is connected to the lead frame terminal on the anode side by resistance welding, and the cathode lead layer is connected to the portion of the lead frame terminal on which the gold plating layer is formed by the conductive adhesive 3, and is molded by the exterior resin 2 to be a chip type. A solid electrolytic capacitor is completed.

  The chip-type solid electrolytic capacitor manufactured by the above embodiment and the conventional chip-type solid electrolytic capacitor manufactured by the conventional structure shown in FIG. 7 are allowed to stand for 1000 hours at a temperature of 65 ° C. and a humidity of 95%, respectively. Tests were performed to compare ESR (equivalent series resistance). The results are shown in Table 1.

  As shown in Table 1, an increase in the ESR value after the moisture resistance test is suppressed in the example as compared with the conventional example. This is considered to be because the reliability of the cathode connection was improved because the lead frame terminal in contact with the conductive adhesive was provided with a gold plating layer that hardly corrodes.

  As described above, in the present invention, it is possible to reduce the cost by limiting the region where the noble metal such as gold is plated to only the portion related to the reliability of the cathode connection, and it has high reliability. By preventing this alloying, a chip-type solid electrolytic capacitor in which the lead frame terminal is not deteriorated can be obtained.

  In the above embodiment, each of the first, second, and third implementations according to the necessity of the tin plating layer of the lead frame terminal due to the size, mountability, and appearance needs of the chip-type solid electrolytic capacitor Can be selected.

  Needless to say, the present invention is not limited to the above-described embodiments and examples, and the materials and thicknesses of the first and second plating layers according to the purpose, application, required performance, and the like. It is possible to change the design such as the material and structure of the lead frame terminal and the structure and shape of the capacitor element.

Sectional drawing which shows 1st embodiment of the chip-type solid electrolytic capacitor by this invention. The expanded sectional view of the lead frame terminal of a first embodiment. Sectional drawing which shows 2nd embodiment of the chip-type solid electrolytic capacitor by this invention. The expanded sectional view of the lead frame terminal of a 2nd embodiment. Sectional drawing which shows 3rd embodiment of the chip-type solid electrolytic capacitor by this invention. The expanded sectional view of the lead frame terminal of a third embodiment. Sectional drawing which shows an example of the conventional chip-type solid electrolytic capacitor. The expanded sectional view of the conventional lead frame terminal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid electrolytic capacitor element 2 Exterior resin 3 Conductive adhesive 4, 14, 24, 34 Lead frame terminal 41 Base material 42 Base plating layer 5 Second plating layer 6 Tin plating layer 10, 11 Area 20 Anode lead

Claims (5)

  An anode body made of a valve metal from which an anode lead was drawn, an oxide film formed on the surface of the anode body, a solid electrolyte layer formed on the oxide film, and formed on the solid electrolyte layer In a chip type solid electrolytic capacitor having a solid electrolytic capacitor element composed of a graphite layer and a cathode lead layer made of a silver paste layer, and having a plate-like lead frame terminal connected to the cathode lead layer by a conductive adhesive The first plating layer as a base is formed on the entire surface of both surfaces of the lead frame terminal, and the second plating layer made of a noble metal is formed only on the surface in contact with the conductive adhesive on the first plating layer. A chip-type solid electrolytic capacitor characterized in that   A tin plating layer on the first plating layer only on at least a part of a portion of the lead frame on which the second plating layer is not formed on the same surface as the second plating layer is formed. The chip-type solid electrolytic capacitor according to claim 1, wherein: is formed.   At least a part of a portion of the lead frame on which the second plating layer is formed and the second plating layer of the lead frame and the second plating layer of the lead frame are formed. 2. The chip-type solid electrolytic capacitor according to claim 1, wherein a tin plating layer is formed on the first plating layer on at least a part of the back surface of the first surface.   4. The chip-type solid electrolytic capacitor according to claim 2, wherein a region where the second plating layer is formed and a region where the tin plating layer is formed are not in contact with each other.   3. An exterior resin covering the solid electrolytic capacitor element is provided, and a region where neither the second plating layer nor the tin plating layer is formed exists only inside the exterior resin. The chip type solid electrolytic capacitor of any one of -4.

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