JP2010062229A5 - Semiconductor device and method of manufacturing semiconductor device - Google Patents
Semiconductor device and method of manufacturing semiconductor device Download PDFInfo
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- JP2010062229A5 JP2010062229A5 JP2008224178A JP2008224178A JP2010062229A5 JP 2010062229 A5 JP2010062229 A5 JP 2010062229A5 JP 2008224178 A JP2008224178 A JP 2008224178A JP 2008224178 A JP2008224178 A JP 2008224178A JP 2010062229 A5 JP2010062229 A5 JP 2010062229A5
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前記ゲート絶縁層上のチャネル形成領域が形成される第1の酸化物半導体層と、
前記第1の酸化物半導体層上の一対のソース領域及びドレイン領域が形成される第2の酸化物半導体層と、
前記第2の酸化物半導体層のソース電極層及びドレイン電極層と、を有し、
前記第1の酸化物半導体層の前記ゲート絶縁層とは反対側の面であって前記ソース領域と前記ドレイン領域に挟まれた領域と、該領域に近接する前記第2の酸化物半導体層の側端部とは、酸素濃度の高い高抵抗領域であることを特徴とする半導体装置。 A gate insulating layer over the gate electrode,
A first oxide semiconductor layer in which a channel formation region over the gate insulating layer is formed ;
A second oxide semiconductor layer in which a pair of source and drain regions is formed over the first oxide semiconductor layer;
Anda source and drain electrode layers of the second oxide semiconductor layer,
Said first and said gate insulating layer of the oxide semiconductor layer interposed between the surface and a by pre SL source region opposite to the drain region region, the second oxide semiconductor layer proximate to the area the side end portions, wherein a high oxygen concentration is high resistance region.
前記第1の酸化物半導体層は、前記第2の酸化物半導体層よりも酸素濃度が高いことを特徴とする半導体装置。 In claim 1,
The semiconductor device characterized in that the first oxide semiconductor layer has an oxygen concentration higher than that of the second oxide semiconductor layer.
前記第1の酸化物半導体層は非晶質構造を有し、
前記第2の酸化物半導体層は非晶質構造の中に微結晶粒を含むことを特徴とする半導体装置。 In claim 1,
The first oxide semiconductor layer has an amorphous structure,
The semiconductor device characterized in that the second oxide semiconductor layer contains microcrystalline grains in an amorphous structure.
前記第1の酸化物半導体層及び前記第2の酸化物半導体層は、インジウム、ガリウム、及び亜鉛を含むことを特徴とする半導体装置。 In any one of claims 1 to 3,
The first oxide semiconductor layer and the second oxide semiconductor layer is a semiconductor device which comprises indium arm, Gallium, and zinc.
前記ゲート絶縁層上に第1の酸化物半導体層と第2の酸化物半導体層とを順次形成し、
前記第2の酸化物半導体層上に、一対のソース電極層及びドレイン電極層を形成し、
前記ソース電極層及びドレイン電極層をマスクとして、前記第2の酸化物半導体層及び前記第1の酸化物半導体層の一部をエッチングし、
前記エッチングにより露出した第2の酸化物半導体層及び前記第1の酸化物半導体層の表面を酸素プラズマ処理により高抵抗化することを特徴とする半導体装置の作製方法。 Forming a gate insulating layer on the gate electrode;
A first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed on the gate insulating layer,
A pair of source and drain electrode layers is formed over the second oxide semiconductor layer,
As masking the source and drain electrode layers, etching a portion of the second oxide semiconductor layer and the first oxide semiconductor layer,
30. A method for manufacturing a semiconductor device , comprising increasing the resistance of a surface of the second oxide semiconductor layer exposed by the etching and the surface of the first oxide semiconductor layer by oxygen plasma treatment.
前記酸素プラズマ処理は、酸素ガス又は酸素ガスと希ガスの混合ガスによるグロー放電プ
ラズマで行うことを特徴とする半導体装置の作製方法。 In claim 5,
The method for manufacturing a semiconductor device , wherein the oxygen plasma treatment is performed by glow discharge plasma using oxygen gas or a mixed gas of oxygen gas and a rare gas.
前記ゲート絶縁層、前記第1の酸化物半導体層、前記第2の酸化物半導体層、前記ソース電極層及び前記ドレイン電極層をスパッタリング法で形成することを特徴とする半導体装置の作製方法。 In claim 5,
The gate insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, a method for manufacturing a semiconductor device characterized by forming the source electrode layer and the drain electrode layer by a sputtering method.
前記ゲート絶縁層、前記第1の酸化物半導体層、前記第2の酸化物半導体層、前記ソース電極層及び前記ドレイン電極層の各層をスパッタリング法で大気に触れさせることなく連続して形成することを特徴とする半導体装置の作製方法。 In claim 5,
The gate insulating layer, the first oxide semiconductor layer, the second oxide semiconductor layer, be formed successively without being exposed to the atmosphere each layer of the source electrode layer and the drain electrode layer by a sputtering method And a method of manufacturing a semiconductor device characterized by
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JP2008224178A JP5537787B2 (en) | 2008-09-01 | 2008-09-01 | Method for manufacturing semiconductor device |
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JP2010062229A5 true JP2010062229A5 (en) | 2011-09-29 |
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