JP6259575B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP6259575B2
JP6259575B2 JP2013032112A JP2013032112A JP6259575B2 JP 6259575 B2 JP6259575 B2 JP 6259575B2 JP 2013032112 A JP2013032112 A JP 2013032112A JP 2013032112 A JP2013032112 A JP 2013032112A JP 6259575 B2 JP6259575 B2 JP 6259575B2
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oxide semiconductor
layer
film
oxygen
oxide
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JP2013201429A5 (en
JP2013201429A (en
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山崎 舜平
舜平 山崎
正美 神長
正美 神長
輝正 池山
輝正 池山
純一 肥塚
純一 肥塚
岡崎 健一
健一 岡崎
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株式会社半導体エネルギー研究所
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Description

The disclosed invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to semiconductor electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, a technique for manufacturing a transistor using zinc oxide or an In—Ga—Zn-based oxide as an oxide semiconductor is disclosed (see Patent Documents 1 and 2).

By the way, it has been pointed out that in an oxide semiconductor, when hydrogen is contained, a donor is generated in a shallow level from the conduction band and the resistance is reduced (n-type). Therefore, it is required to take measures so that hydrogen is not mixed during formation of the oxide semiconductor.

JP 2007-123861 A JP 2007-96055 A

In addition, in the oxide semiconductor, the supply source of carriers includes oxygen vacancies in the oxide semiconductor in addition to hydrogen. Oxygen vacancies in the oxide semiconductor serve as donors and generate electrons that are carriers in the oxide semiconductor. If there are many oxygen vacancies in the oxide semiconductor including the channel formation region of the transistor, electrons are generated in the channel formation region, which causes the threshold voltage of the transistor to fluctuate in the negative direction.

In view of the above problems, in one embodiment of the present invention, a method for manufacturing a semiconductor device using an oxide semiconductor, which can provide stable electrical characteristics and high reliability can be obtained. One purpose is to provide.

According to one embodiment of the present invention, after a source electrode and a drain electrode are formed in an oxide semiconductor layer overlapping with a gate electrode, an oxygen-excess region is provided in at least the oxide semiconductor layer exposed between the source electrode and the drain electrode. This is a method for manufacturing a semiconductor device, in which heat treatment is performed at a temperature at which hydrogen or a hydrogen compound is released from a physical semiconductor layer or higher.

Part of hydrogen in the oxide semiconductor layer is bonded to oxygen included in the oxide semiconductor to be an OH group, so that an oxygen vacancy is formed in the oxide semiconductor. In an oxide semiconductor, oxygen vacancies cause generation of electrons as carriers in the oxide semiconductor. Therefore, if there are many oxygen vacancies in an oxide semiconductor including a channel formation region of a transistor, electrons are generated in the channel formation region. As a result, the threshold voltage of the transistor fluctuates in the negative direction. Therefore, in order to achieve improvement in the reliability of the transistor, it is important to reduce hydrogen and a hydrogen compound in the oxide semiconductor layer as much as possible.

In the method for manufacturing a semiconductor device of one embodiment of the present invention, hydrogen and a hydrogen compound that cause variation in electrical characteristics by performing heat treatment at a temperature at which hydrogen or a hydrogen compound is released from the oxide semiconductor layer or higher than that temperature And the like can be separated from the oxide semiconductor layer.

In addition, part of hydrogen or a hydrogen compound released from the oxide semiconductor layer by the above heat treatment reacts with oxygen (for example, oxygen having an In—O bond) bonded to a metal element in the oxide semiconductor, so that a hydrogen compound (for example, , OH and water). Thus, oxygen vacancies are formed in the oxide semiconductor layer where oxygen is taken. However, according to the method for manufacturing a semiconductor device of one embodiment of the present invention, after an oxygen-excess region is provided in the oxide semiconductor layer exposed between the source electrode and the drain electrode, hydrogen or hydrogen is removed from the oxide semiconductor layer. Oxygen formed in the oxide semiconductor layer or bonded to oxygen containing excessive hydrogen or a hydrogen compound to be removed for heat treatment (hereinafter also referred to as dehydrogenation treatment) for the purpose of detachment of the compound By immediately filling defects with oxygen contained excessively, generation of oxygen defects in the oxide semiconductor layer after heat treatment can be suppressed.

According to another embodiment of the present invention, after a source electrode and a drain electrode are formed in an oxide semiconductor layer overlapping with a gate electrode, an oxygen-excess region is formed in the oxide semiconductor layer exposed at least between the source electrode and the drain electrode. And forming an insulating layer covering the oxygen-excess region, and in a state where the insulating layer is in contact with the oxide semiconductor layer, heat treatment is performed at a temperature at which hydrogen or a hydrogen compound is released from the oxide semiconductor layer, or at a temperature higher than that temperature. This is a method for manufacturing a semiconductor device.

In the above method for manufacturing a semiconductor device, the insulating layer covering the oxygen-excess region is preferably formed at a temperature lower than the temperature at which oxygen is released from the oxygen-excess region.

In the above method for manufacturing a semiconductor device, the oxygen-excess region may be formed by performing oxygen doping treatment on the oxide semiconductor layer.

According to one embodiment of the present invention, a semiconductor device including an oxide semiconductor that can provide stable electrical characteristics and high reliability can be provided.

4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. FIG. 10 is a plan view illustrating one embodiment of a semiconductor device. 4A and 4B are a plan view and cross-sectional views illustrating one embodiment of a semiconductor device. FIG. 14 is a cross-sectional view illustrating one embodiment of a semiconductor device. 6A and 6B are a circuit diagram and a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 9 illustrates an electronic device. FIG. 9 illustrates an electronic device. The figure which shows the model used for calculation of the movement of hydrogen. The graph which shows the calculation result of the model shown in FIG. The figure which shows the model used for calculation of the movement of excess oxygen. The graph which shows the calculation result of the model shown in FIG. The figure which shows the model used for calculation of the movement of oxygen deficiency. The graph which shows the calculation result of the model shown in FIG.

Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the drawings. However, the invention disclosed in this specification is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed. Further, the invention disclosed in this specification is not construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, when referring to a portion having a similar function, the hatch pattern may not be particularly labeled.

In the present specification, ordinal numbers such as “first” and “second” are used for avoiding confusion between components, and are not limited numerically.

(Embodiment 1)
In this embodiment, one embodiment of a method for manufacturing a semiconductor device will be described with reference to FIGS. In this embodiment, a transistor including an oxide semiconductor layer is described as an example of a semiconductor device.

FIG. 1 illustrates a configuration example of the transistor 420. 1A is a plan view of the transistor 420, FIG. 1B is a cross-sectional view taken along line X1-Y1 of FIG. 1A, and FIG. 1C is a cross-sectional view of FIG. It is sectional drawing in V1-W1.

1 includes a gate electrode 401 provided over a substrate 400, an island-shaped oxide semiconductor layer 403 overlapping with the gate electrode 401, and a source electrode 405a electrically connected to the oxide semiconductor layer 403. And a drain electrode 405b.

In addition, the transistor 420 illustrated in FIG. 1 includes the gate insulating layer 402 in which a gate insulating layer 402a and a gate insulating layer 402b are stacked between the gate electrode 401 and the oxide semiconductor layer 403. An insulating layer 408 is provided over the source electrode 405a and the drain electrode 405b.

For example, the oxide semiconductor layer 403 included in the transistor 420 may include a non-single crystal. The non-single crystal includes, for example, CAAC (C Axis Aligned Crystal), polycrystal, microcrystal, and amorphous part. The amorphous part has a higher density of defect states than microcrystals and CAAC. In addition, microcrystals have a higher density of defect states than CAAC. Note that an oxide semiconductor including CAAC is referred to as a CAAC-OS (C Axis Crystallized Oxide Semiconductor).

For example, the oxide semiconductor layer 403 may include a CAAC-OS. For example, the CAAC-OS is c-axis oriented, and the a-axis and / or the b-axis are not aligned macroscopically.

For example, the oxide semiconductor layer 403 may include microcrystal. Note that an oxide semiconductor including microcrystal is referred to as a microcrystalline oxide semiconductor. The microcrystalline oxide semiconductor layer includes microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example.

For example, the oxide semiconductor layer 403 may include an amorphous part. Note that an oxide semiconductor having an amorphous part is referred to as an amorphous oxide semiconductor. The amorphous oxide semiconductor layer has, for example, disordered atomic arrangement and no crystal component. Alternatively, the amorphous oxide semiconductor layer is, for example, completely amorphous and does not have a crystal part.

Note that the oxide semiconductor layer 403 may be a mixed film of a CAAC-OS, a microcrystalline oxide semiconductor, and an amorphous oxide semiconductor. For example, the mixed film includes an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region. The mixed film may have a stacked structure of an amorphous oxide semiconductor region, a microcrystalline oxide semiconductor region, and a CAAC-OS region, for example.

Note that the oxide semiconductor layer 403 may include a single crystal, for example.

The oxide semiconductor layer 403 preferably includes a plurality of crystal parts, and the c-axis of the crystal parts is aligned in a direction parallel to the normal vector of the formation surface or the normal vector of the surface. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. An example of such an oxide semiconductor film is a CAAC-OS film.

Hereinafter, an example of a method for manufacturing the transistor 420 illustrated in FIGS.

First, after the gate electrode 401 is formed over the substrate 400 having an insulating surface, the gate insulating layer 402 is formed by sequentially stacking the gate insulating layer 402a and the gate insulating layer 402b over the gate electrode 401.

There is no particular limitation on a substrate that can be used as the substrate 400 having an insulating surface as long as it has heat resistance enough to withstand heat treatment performed later. For example, various glass substrates used in the electronic industry such as glass substrates such as barium borosilicate glass and alumino borosilicate glass can be used. The substrate has a thermal expansion coefficient of 25 × 10 −7 / ° C. or higher and 50 × 10 −7 / ° C. or lower (preferably 30 × 10 −7 / ° C. or higher and 40 × 10 −7 / ° C. or lower). A substrate having a strain point of 650 ° C. or higher and 750 ° C. or lower (preferably 700 ° C. or higher and 740 ° C. or lower) is preferably used.

5th generation (1000 mm × 1200 mm or 1300 mm × 1500 mm), 6th generation (1500 mm × 1800 mm), 7th generation (1870 mm × 2200 mm), 8th generation (2200 mm × 2500 mm), 9th generation (2400 mm × 2800 mm), 1st When a large glass substrate of 10 generations (2880 × 3130 mm) or the like is used, fine processing may be difficult due to shrinkage of the substrate caused by heat treatment in a manufacturing process of a semiconductor device. Therefore, when a large glass substrate as described above is used as the substrate, it is preferable to use a substrate with less shrinkage. For example, a large glass substrate having a shrinkage amount of 20 ppm or less, more preferably 10 ppm or less, more preferably 5 ppm or less after heat treatment at 450 ° C., preferably 500 ° C. for 1 hour, is used as the substrate. That's fine.

Alternatively, as the substrate 400, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. Alternatively, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be used. A substrate provided with a semiconductor element may be used.

Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 400. Note that in order to manufacture a flexible semiconductor device, the transistor 420 including the oxide semiconductor layer 403 may be directly formed over a flexible substrate, or the oxide semiconductor layer 403 may be formed over another manufacturing substrate. The transistor 420 including the transistor 420 may be manufactured, and then peeled and transferred to the flexible substrate. Note that in order to separate the transistor from the manufacturing substrate and transfer it to the flexible substrate, a separation layer may be provided between the manufacturing substrate and the transistor 420 including the oxide semiconductor layer.

A base insulating layer may be provided over the substrate 400. As the base insulating layer, an oxide insulating film such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, gallium oxide, silicon nitride, silicon nitride oxide, aluminum nitride is formed by a plasma CVD method or a sputtering method. Alternatively, a nitride insulating film such as aluminum nitride oxide, or a mixed material thereof can be used.

The material of the gate electrode 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing any of these materials as its main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used as the gate electrode 401. The gate electrode 401 may have a single-layer structure or a stacked structure.

The material of the gate electrode 401 is indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium oxide. A conductive material such as zinc oxide or indium tin oxide to which silicon oxide is added can also be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

As the gate electrode 401, a metal oxide containing nitrogen, specifically, an In—Ga—Zn—O film containing nitrogen, an In—Sn—O film containing nitrogen, or an In—Ga— film containing nitrogen is used. An O film, an In—Zn—O film containing nitrogen, an Sn—O film containing nitrogen, an In—O film containing nitrogen, or a metal nitride film (InN, SnN, or the like) can be used. These films have a work function of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more, and when used as a gate electrode, the threshold voltage of the electrical characteristics of the transistor can be made positive. In other words, a so-called normally-off switching element can be realized.

As the gate insulating layer 402a, a nitride insulating layer formed by a plasma CVD method, a sputtering method, or the like with a thickness of 10 nm to 100 nm, typically, a thickness of 20 nm to 50 nm can be preferably used. For example, a silicon nitride film, a silicon nitride oxide film, or the like can be given. By applying a nitride insulating layer as the gate insulating layer 402 a in contact with the gate electrode 401 and the substrate 400, an effect of preventing impurity diffusion from the gate electrode 401 or the substrate 400 is achieved.

Alternatively, as the gate insulating layer 402a, aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), tantalum (Ta), lanthanum (La), zirconium (Zr), nickel ( Ni), magnesium (Mg), or metal oxide insulating film containing one or more selected from barium (Ba) metal elements (for example, aluminum oxide film, aluminum oxynitride film, hafnium oxide film, magnesium oxide) A film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film), or a metal nitride insulating film (aluminum nitride film, aluminum nitride oxide film) can be used. For the gate insulating layer 402a, a gallium oxide film, an In—Zr—Zn-based oxide film, an In—Fe—Zn-based oxide film, an In—Ce—Zn-based oxide film, or the like can be used.

As a material of the gate insulating layer 402b, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film can be used. The thickness of the gate insulating layer 402b can be greater than or equal to 100 nm and less than or equal to 350 nm, for example.

As materials for the gate insulating layer 402b, hafnium oxide, yttrium oxide, hafnium silicate (HfSi x O y (x> 0, y> 0)), hafnium silicate to which nitrogen is added (HfSiO x N y (x> 0, The gate leakage current can be reduced by using a high-k material such as y> 0)), hafnium aluminate (HfAl x O y (x> 0, y> 0)), or lanthanum oxide.

The gate insulating layer 402 described in this embodiment has a structure in which a gate insulating layer 402a and a gate insulating layer 402b are stacked in this order from the gate electrode 401 side. However, the embodiment of the present invention is not limited to this, and the gate insulating layer may have a single-layer structure or a stacked structure of three or more layers.

Next, an oxide semiconductor layer is formed over the gate insulating layer 402, and part of the oxide semiconductor layer is selectively etched using a photolithography step, so that the island-shaped oxide semiconductor layer 403 is formed. .

The oxide semiconductor layer 403 may have a single-layer structure or a stacked structure.

As a method for forming the oxide semiconductor layer, a sputtering method, an MBE (Molecular Beam Epitaxy) method, a CVD method, a pulse laser deposition method, an ALD (Atomic Layer Deposition) method, or the like can be used as appropriate.

An oxide semiconductor used for the oxide semiconductor layer 403 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain both In and Zn. In addition, it is preferable that gallium (Ga) be included in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide semiconductor. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer. Moreover, it is preferable to have a zirconium (Zr) as a stabilizer.

As other stabilizers, lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb) , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

For example, as an oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide Oxide, Sn—Mg oxide, In—Mg oxide, In—Ga oxide, In—Ga—Zn oxide, In—Al—Zn oxide which is an oxide of a ternary metal In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La- Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, quaternary metal In—Sn—Ga—Zn-based oxide, In—Hf—Ga—Zn-based oxide, In—Al—Ga—Zn-based oxide, In—Sn—Al—Zn-based oxide, In— Sn-Hf-Zn-based oxides and In-Hf-Al-Zn-based oxides can be used.

Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO 3 (ZnO) m (m> 0 is satisfied, and m is not an integer) may be used as the oxide semiconductor. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In 2 SnO 5 (ZnO) n (n> 0 is satisfied, and n is an integer) may be used as the oxide semiconductor.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1) / 5), or an In—Ga—Zn-based oxide having an atomic ratio of In: Ga: Zn = 3: 1: 2 (= 1/2: 1/6: 1/3) and oxidation in the vicinity of the composition. Can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1) / 2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio In—Sn—Zn-based oxide or oxide in the vicinity of the composition Should be used.

However, the composition is not limited thereto, and a material having an appropriate composition may be used depending on required semiconductor characteristics (mobility, threshold value, variation, etc.). In order to obtain the required semiconductor characteristics, it is preferable that the carrier concentration, the impurity concentration, the defect density, the atomic ratio between the metal element and oxygen, the interatomic distance, the density, and the like are appropriate.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

Note that for example, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: B: C (A + B + C = 1) is in the vicinity of the oxide composition, a, b, c are (a−A) 2 + (b−B) 2 + (c−C) 2 ≦ r 2 Satisfying. For example, r may be 0.05. The same applies to other oxides.

Next, a conductive film to be a source electrode and a drain electrode (including a wiring formed using the same layer) is formed over the gate electrode 401, the gate insulating layer 402, and the oxide semiconductor layer 403, and selectively etched. Then, a source electrode 405a and a drain electrode 405b are formed (see FIG. 2A). The film thickness of the conductive film can be, for example, 20 nm or more and 50 nm or less.

The conductive film can be a single layer or a stacked structure using a material that can withstand heat treatment performed later. As the conductive film used for the source electrode and the drain electrode, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film containing the above-described element as a component ( A titanium nitride film, a molybdenum nitride film, a tungsten nitride film, or the like can be used. Further, a refractory metal film such as Ti, Mo, W or the like or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is provided on one or both of the lower side or the upper side of a metal film such as Al or Cu. It is good also as a structure which laminated | stacked. Further, the conductive film used for the source electrode and the drain electrode may be formed using a conductive metal oxide. As the conductive metal oxide, indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), indium tin oxide (In 2 O 3 —SnO 2 , abbreviated as ITO), oxidation Indium zinc oxide (In 2 O 3 —ZnO) or a metal oxide material containing silicon oxide can be used.

After the source electrode 405a and the drain electrode 405b are formed, heat treatment for reducing or removing (dehydrogenating) excess hydrogen or a hydrogen compound contained in the oxide semiconductor layer 403 may be performed. The heat treatment may be performed under reduced pressure, and the temperature of the heat treatment is set to a temperature at which hydrogen or a hydrogen compound is released from the oxide semiconductor layer 403 or higher. For example, when the heat treatment temperature is 100 ° C. or higher, the hydrogen content in the oxide semiconductor layer 403 can be reduced, and this heat treatment is preferably performed at 300 ° C. to 400 ° C. Needless to say, the effect of reducing the hydrogen content of the oxide semiconductor layer 403 can be obtained even when heat treatment is performed at a higher temperature.

For example, the substrate 400 is introduced into an electric furnace which is one of heat treatment apparatuses, and the oxide semiconductor layer 403 is heat-treated at 350 ° C. under reduced pressure.

Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, a rapid thermal annealing (RTA) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used.

Note that when the gate insulating layer 402 in contact with the oxide semiconductor layer 403 contains hydrogen, the hydrogen may enter the oxide semiconductor layer 403 or the hydrogen may extract oxygen from the oxide semiconductor layer 403. is there. Therefore, the gate insulating layer 402 is preferably free of impurities such as water and a hydrogen compound as much as possible. Here, when heat treatment is performed on the island-shaped oxide semiconductor layer 403 at a temperature at which hydrogen or a hydrogen compound is released or higher, the gate insulating layer 402 in a region exposed from the oxide semiconductor layer 403 is exposed. Is also preferable because hydrogen and hydrogen compounds can be effectively released.

In the heat treatment, it is preferable that water or hydrogen is not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably Is preferably 0.1 ppm or less).

Next, oxygen 421 is introduced into the oxide semiconductor layer 403, and at least the oxide semiconductor layer 403 exposed between the source electrode 405a and the drain electrode 405b includes a region containing oxygen in excess of the stoichiometric composition (oxygen) An excess region is provided (see FIG. 2B).

The introduction of oxygen 421 can be performed by, for example, oxygen doping treatment.

In this specification and the like, “oxygen doping” means oxygen (including at least one of oxygen radicals, oxygen atoms, oxygen molecules, ozone, oxygen ions (oxygen molecular ions), and / or oxygen cluster ions). Is added to the bulk. The term “bulk” is used for the purpose of clarifying that oxygen is added not only to the surface of the thin film but also to the inside of the thin film. Further, “oxygen doping” includes “oxygen plasma doping” in which oxygen in plasma form is added to a bulk.

As the oxygen supply gas, a gas containing O may be used. For example, O 2 gas, N 2 O gas, CO 2 gas, CO gas, NO 2 gas, or the like may be used. Note that a rare gas (eg, Ar) may be added to the oxygen supply gas.

For example, when oxygen is introduced by an ion implantation method, the oxygen dose is preferably 1 × 10 13 ions / cm 2 or more and 5 × 10 16 ions / cm 2 or less. It is preferable that the oxygen content in the physical semiconductor layer 403 be higher than the stoichiometric composition of the oxide semiconductor layer 403 in at least a region exposed between the source electrode 405a and the drain electrode 405b. Note that the depth of oxygen implantation may be appropriately controlled depending on the implantation conditions.

Note that oxygen is one of main component materials in an oxide semiconductor. Therefore, it is difficult to accurately estimate the oxygen concentration in the oxide semiconductor layer 403 by using a method such as SIMS (Secondary Ion Mass Spectrometry). That is, it can be difficult to determine whether oxygen is intentionally added to the oxide semiconductor layer 403.

By the way, it is known that oxygen has isotopes such as 17 O and 18 O, and their abundance ratios in the natural world are about 0.038% and 0.2% of the whole oxygen atom, respectively. In other words, the concentration of these isotopes in the oxide semiconductor layer 403 can be estimated by a method such as SIMS. Therefore, by measuring these concentrations, the oxygen concentration in the oxide semiconductor layer 403 can be further increased. It may be possible to estimate accurately. Therefore, it may be determined whether oxygen is intentionally added to the oxide semiconductor layer 403 by measuring these concentrations.

Note that the top surfaces of the source electrode 405a and the drain electrode 405b may be oxidized depending on the condition of the oxygen doping treatment.

Next, heat treatment is performed at or above a temperature at which hydrogen or a hydrogen compound is released from the oxide semiconductor layer 403 including the oxygen-excess region. By this heat treatment, hydrogen which is an impurity imparting n-type conductivity can be removed from the oxide semiconductor more preferably.

Note that part of hydrogen or a hydrogen compound released from the oxide semiconductor layer 403 by this heat treatment reacts with oxygen (for example, oxygen having an In—O bond) bonded to a metal element in the oxide semiconductor, so that a hydrogen compound (for example, , OH and water). However, according to the manufacturing method of this embodiment, the oxide semiconductor layer 403 exposed between the source electrode 405a and the drain electrode 405b is provided with an oxygen-excess region, and then dehydrogenation is performed. An oxide semiconductor layer after dehydrogenation treatment is formed by combining hydrogen or hydrogen compound with oxygen excessively contained or by immediately filling oxygen deficiency formed in the oxide semiconductor layer 403 with oxygen excessively contained. It is possible to suppress the generation of oxygen vacancies.

Through the above steps, the transistor 420 including the oxide semiconductor layer 403 from which hydrogen is removed and reduced by dehydrogenation treatment is manufactured. By using the oxide semiconductor layer 403 as a film which does not contain hydrogen as much as possible, a change in characteristics of the transistor 420 can be suppressed and a highly reliable semiconductor device can be obtained.

An insulating layer 408 in contact with part of the oxide semiconductor layer 403 (including an oxygen-excess region) may be formed over the source electrode 405a and the drain electrode 405b (see FIG. 2C). The insulating layer 408 can be a single layer or a stacked structure using a material similar to that of the gate insulating layer 402. For example, the insulating layer 408 can be formed using silicon oxide, silicon oxynitride, or the like by a sputtering method or a CVD method.

The insulating layer 408 is preferably formed as a dense film by supplying high power under low pressure vacuum. By forming the insulating layer 408 into a dense film, oxygen can be prevented from being separated from the oxide semiconductor layer 403 and the insulating layer 408 in contact therewith, and mixing of hydrogen and a hydrogen compound into the oxide semiconductor layer 403 can be prevented. Can do.

Further, heat treatment may be performed after the insulating layer 408 is formed. The temperature of the heat treatment may be higher than or equal to the temperature at which hydrogen or a hydrogen compound is released from the oxide semiconductor layer 403 including the oxygen-excess region. Note that in the case where the thickness of the insulating layer 408 is large (for example, when the thickness of the insulating layer 408 is 200 nm or more), the temperature of heat treatment for releasing hydrogen or a hydrogen compound from the oxide semiconductor layer 403 is 200. It is preferable to set it as ° C or more.

The heat treatment at or above the temperature at which hydrogen or a hydrogen compound is released from the oxide semiconductor layer may be performed at least once after the oxygen-excess region is formed in the oxide semiconductor layer 403. That is, in the case where the heat treatment is performed after the insulating layer 408 is formed, the dehydrogenation treatment after the introduction of the oxygen 421 described above can be omitted. In addition, in the case where the deposition temperature of the insulating layer 408 is set to a temperature at which hydrogen or a hydrogen compound is released from the oxide semiconductor layer or higher, the formation of the insulating layer 408 and the dehydrogenation treatment may be performed. it can.

Further, a planarization insulating layer may be formed over the transistor 420. As the planarization insulating layer, a heat-resistant organic material such as polyimide, acrylic, polyimide amide, ginzocyclobutene, polyamide, or epoxy can be used. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphorus glass), BPSG (phosphorus glass), or the like can be used. Note that the planarization insulating layer may be formed by stacking a plurality of insulating layers formed using these materials.

In the method for manufacturing the semiconductor device described in this embodiment, the oxide semiconductor layer 403 including the oxygen-excess region is subjected to heat treatment substantially once at a temperature at which hydrogen or a hydrogen compound is released or higher. Thus, impurities such as hydrogen and a hydrogen compound, which cause variation in electrical characteristics, can be separated from the oxide semiconductor layer 403 while suppressing generation of oxygen vacancies. Therefore, the reliability of the semiconductor device to which the oxide semiconductor layer 403 subjected to the heat treatment is applied can be improved.

Note that a region containing oxygen in excess of the stoichiometric composition (oxygen-excess region) in the oxide semiconductor layer 403 is in contact with the oxide semiconductor layer 403 and the oxide semiconductor layer 403 in stoichiometry. The oxide semiconductor layer including oxygen in excess of the theoretical composition may be provided by deposition.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, a semiconductor device using a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film as the oxide semiconductor layer 403 in the semiconductor device described in Embodiment 1 will be described.

The CAAC-OS film used for the oxide semiconductor layer 403 is an oxide semiconductor film having a crystal part. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in the observation image obtained by a transmission electron microscope (TEM), the boundary between the crystal part and the crystal part included in the CAAC-OS film is not clear. In addition, a clear grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, reduction in electron mobility due to grain boundaries is suppressed.

The crystal part included in the CAAC-OS film is aligned so that, for example, the c-axis is in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and is perpendicular to the ab plane. When viewed from the direction, the metal atoms are arranged in a triangular shape or a hexagonal shape, and when viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in layers, or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, the term “perpendicular” includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. In addition, a simple term “parallel” includes a range of −10 ° to 10 °, preferably −5 ° to 5 °.

Note that the distribution of crystal parts in the CAAC-OS film is not necessarily uniform. For example, in the formation process of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the ratio of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher in the vicinity of the surface. Further, when an impurity is added to the CAAC-OS film, the crystallinity of a crystal part in the impurity-added region may be decreased.

Since the c-axis of the crystal part included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, the shape of the CAAC-OS film (formation surface) Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface). The crystal part is formed when a film is formed or when a crystallization process such as a heat treatment is performed after the film formation. Therefore, the c-axes of the crystal parts are aligned in a direction parallel to the normal vector of the surface where the CAAC-OS film is formed or the normal vector of the surface.

In a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

Further, in an oxide semiconductor having a crystal part such as a CAAC-OS, defects in a bulk can be further reduced, and mobility higher than that of an oxide semiconductor in an amorphous state can be obtained by increasing surface flatness. . In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on the flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Is preferably formed on a surface of 0.1 nm or less.

Ra is a three-dimensional extension of the centerline average roughness defined in JIS B0601 so that it can be applied to a surface. “A value obtained by averaging the absolute values of deviations from a reference surface to a specified surface” "And is defined by the following equation.

In the above, S 0 is surrounded by four points represented by the measurement plane (coordinates (x 1 , y 1 ) (x 1 , y 2 ) (x 2 , y 1 ) (x 2 , y 2 )). (Rectangular region) indicates the area, and Z 0 indicates the average height of the measurement surface. Ra can be evaluated with an atomic force microscope (AFM).

As a method for obtaining the CAAC-OS film as described above, for example, the oxide semiconductor layer is formed by heating the substrate (for example, the substrate temperature is set to 170 ° C.), and the c-axis alignment is performed substantially perpendicular to the surface. There is a way.

Note that the oxide semiconductor layer 403 may have a structure in which a plurality of oxide semiconductor layers are stacked. The first oxide semiconductor layer and the second oxide semiconductor layer each have a crystalline oxide structure different from that of the CAAC-OS. A physical semiconductor may be applied. In other words, the CAAC-OS and a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, or an amorphous oxide semiconductor may be combined as appropriate. However, an amorphous oxide semiconductor easily absorbs an impurity serving as a donor such as hydrogen, and oxygen vacancies easily occur, so that the amorphous oxide semiconductor is easily n-type. Therefore, an oxide semiconductor having crystallinity such as CAAC-OS is preferably used for the oxide semiconductor layer on the channel side.

Alternatively, the oxide semiconductor layer 403 may have a stacked structure of three or more layers and a structure including a plurality of crystalline oxide semiconductor layers or amorphous oxide semiconductor layers. Alternatively, a structure in which an oxide semiconductor layer having crystallinity and an amorphous oxide semiconductor layer are alternately stacked may be employed. The above structures in the case where the oxide semiconductor layer 403 has a stacked structure of a plurality of layers can be used in appropriate combination.

As described above, by using the CAAC-OS film as the oxide semiconductor layer 403, hydrogen can be easily released from the top surface of the CAAC-OS film in the heat treatment (dehydrogenation treatment) described in Embodiment 1. it can. Further, in the heat treatment, it is possible to selectively release a large amount of hydrogen by reducing the separation of oxygen.

Here, the heat treatment (dehydrogenation treatment) described in Embodiment 1 indicates that hydrogen is relatively easily released from the upper surface of the CAAC-OS film, and the results of calculation using a model are described with reference to FIGS. explain.

In this calculation, as an example of the CAAC-OS, a crystal structure oriented in the c-axis direction of an In—Ga—Zn-based oxide that is a ternary metal oxide is used. A model in which hydrogen atoms were introduced as impurities (hereinafter referred to as model A) was produced, and whether or not hydrogen easily diffuses in the c-axis direction in the model was verified using computer simulation. In addition, as a comparative example, a model in which excess oxygen (oxygen atoms existing beyond the stoichiometric ratio) is introduced as an impurity in an In—Ga—Zn-based oxide (hereinafter referred to as model B), and In—Ga -Models in which oxygen vacancies are introduced as impurities in Zn-based oxides (hereinafter referred to as model C) are manufactured, and whether or not excess oxygen or oxygen vacancies easily diffuse in the c-axis direction in these models is verified using computer simulation did.

First, the structure of model A is shown in FIG. In the model A shown in FIG. 9, hydrogen atoms are introduced so as to be bonded to oxygen atoms in an In—Ga—Zn-based oxide having an atomic ratio of In: Ga: Zn = 1: 1: 1. The number of atoms in Model A is 85 atoms. Here, the large black sphere in FIG. 9 is an indium atom, the large white sphere is a gallium atom, the white medium sphere is a zinc atom, the small black sphere is an oxygen atom to which no hydrogen atom is bonded, gray. The small sphere represents an oxygen atom to which a hydrogen atom is bonded, and the white small sphere represents a hydrogen atom. Further, an arrow in FIG. 9 represents the c-axis direction of the In—Ga—Zn-based oxide crystal.

The sites 1 to 8 shown in FIG. 9 indicate binding sites of oxygen atoms that can be bonded to hydrogen atoms. In model A, as shown in FIG. 9, in the initial state, a hydrogen atom is bonded to oxygen at the first site, and the hydrogen atom moves to the second site through an intermediate structure along the minimum energy path. It is assumed that the user moves to the 8th site through the 3rd to 7th sites.

In this calculation, the diffusion frequency Γ per unit time was used as an index for evaluating hydrogen atoms diffusing in the c-axis direction in the CAAC-OS film. The diffusion frequency Γ (/ s) at a certain temperature T (K) is expressed by the following equation (1) using the frequency Γ O (/ s) of the impurity atom at the stable position.

In equation (1), Eb max is the maximum value of energy Eb (eV) in the movement of hydrogen atoms between the sites, and corresponds to the activation energy associated with the movement of hydrogen atoms between the sites. K is a Boltzmann constant. In the formula (1), Γ O = 1.0 × 10 13 (/ s). Further, T = 623 K (350 ° C.) is used in correspondence with the temperature of the heat treatment shown in Embodiment Mode 1.

Thus, the diffusion frequency Γ of hydrogen atoms can be evaluated by calculating the activation energy Eb max required when the hydrogen atoms move between the sites. That is, if the activation energy Eb max is high, hydrogen atoms are difficult to move between sites, and if the activation energy Eb max is low, hydrogen atoms are likely to move between sites.

Here, in order to obtain Eb max in the movement of the 8th site from the 1st site of the hydrogen atom, the energy for the intermediate structure along the minimum energy path is calculated between each site using the NEB (Nudged Elastic Band) method. Each was calculated. Note that the model A shown in FIG. 9 is structurally optimized in advance, and the NEB method is used for the structurally optimized model A.

For calculation of the NEB method, VASP (Vienna Ab-initio Simulation Package), which is a program package using the density functional method, was used. A plane wave basis function was used as the basis function, and a GGA / PBE (Generalized-Gradient-Approximation / Perdew-Burke-Ernzerhof) using a PAW (Projector Augmented Wave) method was used as the functional. Further, a cutoff energy of 400 eV was used, and a 2 × 2 × 1 grid was used for sampling k points.

FIG. 10 shows the result of calculation for the model A using the NEB method. In FIG. 10, the vertical axis indicates the energy Eb (eV) required for the movement of hydrogen atoms, and the horizontal axis indicates the hydrogen movement path (arbitrary unit), and the above sites 1 to 8 correspond to the hydrogen movement path. It has been described.

From FIG. 10, it can be seen that, in the movement of the hydrogen atom from the first site to the eighth site, the highest energy Eb is from the seventh site to the eighth site. Here, the activation energy Eb max with the energy minimum point of the entire hydrogen transfer path as the origin is 1.50 eV. From the above formula (1), the diffusion frequency Γ of hydrogen atoms at a temperature of 350 ° C. is 7.3 / s.

Here, the 7th site and the 8th site are provided so as to sandwich the indium atom, so that the movement of the hydrogen atom described above causes the hydrogen atom to diffuse across the layer of indium atom in the c-axis direction. Corresponding to Therefore, the activation energy Eb max and the diffusion frequency Γ correspond to the activation energy and the diffusion frequency when hydrogen atoms diffuse in the c-axis direction beyond the layer of indium atoms.

Next, the structure of model B is shown in FIGS. 11 (A) and 11 (B). In the model B shown in FIGS. 11A and 11B, in an In—Ga—Zn-based oxide with an atomic ratio of In: Ga: Zn = 3: 1: 2, it is bonded to an indium atom. Excess oxygen is introduced. The number of atoms in Model B is 85 atoms. Here, black large spheres in FIGS. 11A and 11B represent indium atoms, white large spheres represent gallium atoms, gray medium sized spheres represent zinc atoms, and black small spheres represent Represents an oxygen atom. Note that the first to third oxygen atoms illustrated in FIGS. 11A and 11B are oxygen atoms in the vicinity of indium atoms to which excess oxygen is bonded. In addition, an arrow in FIGS. 11A and 11B represents the c-axis direction of the crystal of the In—Ga—Zn-based oxide.

Here, FIGS. 11A and 11B show the initial state and the final state of model B in which excess oxygen moves in the c-axis direction beyond the layer of indium atoms. Therefore, from FIG. 11A to FIG. 11B, the first oxygen atom moves in the direction of pushing out the third oxygen atom. At this time, the second oxygen atom is also moving.

In the model B as well, the excess oxygen diffusing in the c-axis direction in the CAAC-OS film is evaluated using the diffusion frequency Γ similarly to the model A. Eb max in the movement of excess oxygen from the initial state to the final state of Model B was also calculated using the NEB method. Note that the model B shown in FIGS. 11A and 11B is structurally optimized in advance, and the NEB method is used for the model B that has been structurally optimized.

For the calculation of the NEB method, OpenMX, which is a program package using a density functional method, was used. Localized basis functions (pseudo-atomic orbit functions) were used as the basis functions, and GGA / PBE (Generalized-Gradient-Approximation / Perdew-Burke-Ernzerhof) using norm-conserving pseudopotentials was used as the functional. The cut-off energy was 2721.16 eV, and the sampling k point was a 5 × 5 × 3 grid.

FIG. 12 shows the result of calculation for the model B using the NEB method. In FIG. 12, the vertical axis represents energy Eb (eV) required for the movement of excess oxygen, and the horizontal axis represents the path length (angstrom) of the movement of excess oxygen.

From FIG. 12, the activation energy Eb max when excess oxygen diffuses in the c-axis direction beyond the layer of indium atoms is 2.38 eV. From the above formula (1), the diffusion frequency Γ of excess oxygen at a temperature of 350 ° C. is 5.6 × 10 −7 / s.

Next, the structure of the model C is shown in FIGS. 13 (A) and 13 (B). In Model C shown in FIGS. 13A and 13B, an oxygen atom bonded to an indium atom in an In—Ga—Zn-based oxide with an atomic ratio of In: Ga: Zn = 3: 1: 2 is used. One deficiency is introduced to introduce oxygen deficiency. The number of atoms in model C is 83 atoms. Here, black large spheres in FIGS. 13A and 13B represent indium atoms, white large spheres represent gallium atoms, gray medium sized spheres represent zinc atoms, and black small spheres represent Represents an oxygen atom. 13A and 13B indicate the c-axis direction of the In—Ga—Zn-based oxide crystal. Note that a sphere indicated by a dotted line in FIGS. 13A and 13B represents oxygen deficiency.

Here, FIGS. 13A and 13B show an initial state and an end state of model C in which oxygen vacancies move in the c-axis direction beyond the layer of indium atoms. In the model C as well, the oxygen vacancies diffused in the c-axis direction in the CAAC-OS film are evaluated using the diffusion frequency Γ as in the models A and B. Eb max in the movement of oxygen deficiency from the initial state to the final state of model C was also calculated using the NEB method. Various conditions of calculation using the NEB method for model C were the same as those for model B. Note that the model C shown in FIGS. 13A and 13B is structurally optimized in advance, and the NEB method is used for the structurally optimized model C.

FIG. 14 shows the result of calculation for model C using the NEB method. In FIG. 14, the vertical axis represents energy Eb (eV) required for the movement of oxygen deficiency, and the horizontal axis represents the path length (angstrom) of the movement of oxygen deficiency.

From FIG. 14, the activation energy Eb max when the oxygen vacancy diffuses in the c-axis direction beyond the layer of indium atoms is 4.10 eV. From the above formula (1), the diffusion frequency Γ of oxygen vacancies at a temperature of 350 ° C. is 6.8 × 10 −21 .

As described above, the activation energy Eb max obtained when hydrogen atoms, excess oxygen, or oxygen vacancies diffuse from the indium atom layer in the c-axis direction and the diffusion at 350 ° C. obtained from FIG. 10, FIG. 12, and FIG. The frequency Γ is shown in Table 1.

From Table 1, it can be seen that model A has a larger activation energy Eb max than model B and model C. That is, it can be said that hydrogen atoms are more likely to diffuse in the c-axis direction across the layer of indium atoms compared to excess oxygen or oxygen deficiency. In particular, the diffusion frequency Γ of model A at 350 ° C. is extremely large as compared with model B and model C. Therefore, by performing heat treatment as described in Embodiment 1, hydrogen atoms in the CAAC-OS film are more likely to diffuse in the c-axis direction across the layer of indium atoms than in excess oxygen or oxygen vacancies. Can do.

Note that in the above description, the case where hydrogen atoms, excess oxygen, or oxygen vacancies diffuses in the c-axis direction across the layer of indium atoms is described, but the same applies to metal atoms other than indium included in the CAAC-OS film. It is possible.

Therefore, by using the CAAC-OS film as the oxide semiconductor layer 403 described in the above embodiment and performing the dehydrogenation treatment described in Embodiment 1, hydrogen atoms in the CAAC-OS film are aligned in the c-axis direction. It can be diffused and separated from the upper surface of the CAAC-OS film. At this time, since the diffusion frequency of hydrogen is extremely large as compared with excess oxygen or oxygen deficiency, a large amount of hydrogen can be selectively released.

In addition, as described in Embodiment 1, the formation of an oxygen-excess region in the oxide semiconductor layer 403 can suppress extraction of oxygen from the CAAC-OS film when hydrogen is released.

In this manner, by using the CAAC-OS film as the oxide semiconductor layer, impurities such as hydrogen and a hydrogen compound that cause variation in electric characteristics of the transistor can be separated from the oxide semiconductor layer. Reliability can be improved.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
A semiconductor device having a display function (also referred to as a display device) can be manufactured using the transistor described in Embodiment 1. In addition, part or the whole of a driver circuit including a transistor can be formed over the same substrate as the pixel portion to form a system-on-panel.

In FIG. 3A, a sealant 4005 is provided so as to surround a pixel portion 4002 provided over a substrate 4001 and sealed with the substrate 4006. 3A, a single crystal semiconductor film or a polycrystalline semiconductor film is formed over an IC chip or a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the substrate 4001. A scanning line driver circuit 4004 and a signal line driver circuit 4003 are mounted. In addition, a variety of signals and potentials are supplied to a separately formed signal line driver circuit 4003, the scan line driver circuit 4004, and the pixel portion 4002 from FPCs (Flexible Printed Circuits) 4018a and 4018b.

3B and 3C, a sealant 4005 is provided so as to surround the pixel portion 4002 provided over the substrate 4001 and the scan line driver circuit 4004. A substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the display element by the substrate 4001, the sealant 4005, and the substrate 4006. 3B and 3C, a single crystal semiconductor film or a polycrystalline semiconductor is formed over an IC chip or a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the substrate 4001. A signal line driver circuit 4003 formed of a film is mounted. 3B and 3C, a signal line driver circuit 4003 which is formed separately, and various signals and potentials which are supplied to the scan line driver circuit 4004 or the pixel portion 4002 are supplied from an FPC 4018.

3B and 3C illustrate an example in which the signal line driver circuit 4003 is separately formed and mounted on the substrate 4001, the invention is not limited to this structure. The scan line driver circuit may be separately formed and mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and mounted.

Note that a connection method of a driver circuit which is separately formed is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, a TAB (Tape Automated Bonding) method, or the like can be used. 3A illustrates an example in which the signal line driver circuit 4003 and the scanning line driver circuit 4004 are mounted by a COG method, and FIG. 3B illustrates an example in which the signal line driver circuit 4003 is mounted by a COG method. FIG. 3C illustrates an example in which the signal line driver circuit 4003 is mounted by a TAB method.

The display device includes a panel in which the display element is sealed, and a module in which an IC including a controller is mounted on the panel.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). In addition, a connector, for example, a module to which an FPC or TCP is attached, a module in which a printed wiring board is provided at the end of TCP, or a module in which an IC (integrated circuit) is directly mounted on a display element by a COG method is also included in the display device Shall be included.

In addition, the pixel portion and the scan line driver circuit provided over the substrate include a plurality of transistors, and the transistor described in Embodiment 1 can be used.

As a display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, and the like. In addition, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

One embodiment of a semiconductor device will be described with reference to FIGS. FIG. 5 corresponds to a cross-sectional view taken along line MN in FIG.

As shown in FIGS. 3 and 5, the semiconductor device includes a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are anisotropically conductive with terminals of the FPC 4018 (4018a and 4018b). Electrical connection is established through the layer 4019.

The connection terminal electrode 4015 is formed using the same conductive layer as the first electrode layer 4034, and the terminal electrode 4016 is formed using the same conductive layer as the source and drain electrodes of the transistors 4040 and 4011.

The pixel portion 4002 and the scan line driver circuit 4004 provided over the substrate 4001 include a plurality of transistors. In FIGS. 3 and 5, the transistor 4040 included in the pixel portion 4002 and the scan line driver circuit 4004 are included. The transistor 4011 included in FIG. In FIG. 5A, insulating layers 4030 and 4032 are provided over the transistors 4040 and 4011. In FIG. 5B, an insulating layer 4021 is further provided.

As the transistors 4010 and 4011, the transistor described in Embodiment 1 can be used. The transistors 4010 and 4011 are bottom-gate transistors.

In the manufacturing process of the transistors 4010 and 4011, heat treatment is performed on the oxide semiconductor layer including the oxygen-excess region at a temperature at which hydrogen or a hydrogen compound is released or higher. Thus, the oxide semiconductor layer included in the transistors 4010 and 4011 is an oxide semiconductor layer in which oxygen vacancies are suppressed and impurities such as hydrogen and a hydrogen compound that cause variation in electrical characteristics are reduced. In 4011, fluctuations in electrical characteristics are suppressed.

Therefore, a highly reliable semiconductor device can be provided as a semiconductor device including the transistors 4010 and 4011 having stable electric characteristics using the oxide semiconductor layer of this embodiment illustrated in FIGS.

Further, a conductive layer may be provided in a position overlapping with a channel formation region of the oxide semiconductor layer of the transistor 4011 for the driver circuit. By providing the conductive layer so as to overlap with the channel formation region of the oxide semiconductor layer, the amount of change in the threshold voltage of the transistor 4011 before and after the bias-thermal stress test (BT test) can be further reduced. In addition, the potential of the conductive layer may be the same as or different from that of the gate electrode of the transistor 4011, and the conductive layer can function as a second gate electrode. Further, the potential of the conductive layer may be in a floating state, for example.

The conductive layer also has a function of shielding an external electric field, that is, preventing the external electric field from acting on the inside (a circuit portion including a transistor) (particularly, an electrostatic shielding function against static electricity). With the shielding function of the conductive layer, the electrical characteristics of the transistor can be prevented from changing due to the influence of an external electric field such as static electricity.

A transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element to form a display panel. The display element is not particularly limited as long as display can be performed, and various display elements can be used.

FIG. 5A illustrates an example of a liquid crystal display device using a liquid crystal element as a display element. In FIG. 5A, a liquid crystal element 4013 which is a display element includes a first electrode layer 4034, a second electrode layer 4031, and a liquid crystal layer 4008. Note that insulating layers 4038 and 4033 functioning as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the substrate 4006 side, and the first electrode layer 4034 and the second electrode layer 4031 are stacked with the liquid crystal layer 4008 interposed therebetween.

The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided for controlling the film thickness (cell gap) of the liquid crystal layer 4008. A spherical spacer may be used.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials (liquid crystal compositions) exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

Alternatively, a liquid crystal composition exhibiting a blue phase for which an alignment film is unnecessary may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008 is in contact with the first electrode layer 4034 and the second electrode layer 4031. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. The blue phase can be expressed using a liquid crystal composition in which a liquid crystal and a chiral agent are mixed. In addition, in order to widen the temperature range in which the blue phase develops, a liquid crystal layer is formed by adding a polymerizable monomer, a polymerization initiator, or the like to the liquid crystal composition that develops the blue phase, and performing a polymer stabilization treatment. You can also. A liquid crystal composition that develops a blue phase has a short response speed and is optically isotropic, so alignment treatment is unnecessary and viewing angle dependency is small. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. . Therefore, the productivity of the liquid crystal display device can be improved. In a transistor using an oxide semiconductor layer, the electrical characteristics of the transistor may fluctuate significantly due to the influence of static electricity and deviate from the design range. Therefore, it is more effective to use a liquid crystal composition exhibiting a blue phase for a liquid crystal display device including a transistor including an oxide semiconductor layer.

The specific resistance of the liquid crystal material is 1 × 10 9 Ω · cm or more, preferably 1 × 10 11 Ω · cm or more, and more preferably 1 × 10 12 Ω · cm or more. In addition, the value of the specific resistance in this specification shall be the value measured at 20 degreeC.

The size of the storage capacitor provided in the liquid crystal display device is set so that charges can be held for a predetermined period in consideration of a leakage current of a transistor arranged in the pixel portion. The size of the storage capacitor may be set in consideration of the off-state current of the transistor. By using a transistor including an oxide semiconductor layer disclosed in this specification, a storage capacitor having a capacitance of 1/3 or less, preferably 1/5 or less of the liquid crystal capacitance of each pixel is provided. It is enough.

In a transistor including an oxide semiconductor layer disclosed in this specification, a current value in an off state (off-state current value) can be controlled low. Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

In addition, a transistor including the oxide semiconductor layer disclosed in this specification can have a relatively high field-effect mobility, and thus can be driven at high speed. For example, by using such a transistor capable of high-speed driving for a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. In the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

The liquid crystal display device includes TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetrical Micro-cell) mode, OCB mode (OCB). An FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti Ferroelectric Liquid Crystal) mode, or the like can be used.

Alternatively, a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, and the like can be used. The present invention can also be applied to a VA liquid crystal display device. A VA liquid crystal display device is a type of a method for controlling the alignment of liquid crystal molecules of a liquid crystal display panel. The VA liquid crystal display device is a method in which liquid crystal molecules face a vertical direction with respect to a panel surface when no voltage is applied. Further, a method called multi-domain or multi-domain design in which pixels (pixels) are divided into several regions (sub-pixels) and molecules are tilted in different directions can be used.

In the display device, a black matrix (light shielding layer), a polarizing member, a retardation member, an optical member (an optical substrate) such as an antireflection member, and the like are provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

As a display method in the pixel portion, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, there is RGBW (W represents white) or RGB in which one or more colors of yellow, cyan, magenta, etc. are added. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

In addition, as a display element included in the display device, a light-emitting element utilizing electroluminescence can be used. A light-emitting element using electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from the pair of electrodes into the layer containing the light emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element. In this embodiment, an example in which an organic EL element is used as a light-emitting element is described.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes may be light-transmitting. Then, a transistor and a light emitting element are formed over the substrate, and a top emission that extracts light from a surface opposite to the substrate, a bottom emission that extracts light from a surface on the substrate side, and a surface opposite to the substrate side and the substrate. There is a light-emitting element having a dual emission structure in which light emission is extracted from the light-emitting element, and any light-emitting element having an emission structure can be applied.

4A and 4B illustrate an example of a light-emitting device using a light-emitting element as a display element.

4A is a plan view of the light-emitting device, and a cross section taken along dashed-dotted lines S1-T1, S2-T2, and S3-T3 in FIG. 4A corresponds to FIG. Note that the electroluminescent layer 542 and the second electrode layer 543 are not illustrated in the plan view of FIG.

The light-emitting device illustrated in FIG. 4 includes a transistor 510, a capacitor 520, and a wiring layer intersection 530 over a substrate 500. The transistor 510 is electrically connected to the light-emitting element 540. 4 illustrates a light emitting device having a bottom emission structure in which light from the light emitting element 540 is extracted through the substrate 500. FIG.

As the transistor 510, the transistor described in Embodiment 1 can be used. In this embodiment, an example in which a transistor having a structure similar to that of the transistor 420 described in Embodiment 1 is applied is described. The transistor 510 is a bottom-gate transistor.

The transistor 510 includes gate electrodes 511a and 511b, a gate insulating layer 502, an oxide semiconductor layer 512, and conductive layers 513a and 513b functioning as a source electrode or a drain electrode.

In the manufacturing process of the transistor 510, heat treatment is performed on the oxide semiconductor layer 512 including the oxygen-excess region at a temperature at which hydrogen or a hydrogen compound is released or higher. Therefore, the oxide semiconductor layer 512 is an oxide semiconductor layer in which oxygen vacancies are suppressed and impurities such as hydrogen and a hydrogen compound that are factors of variation in electrical characteristics are reduced.

Therefore, a highly reliable semiconductor device can be provided as a semiconductor device including the transistor 510 having stable electric characteristics using the oxide semiconductor layer 512 of this embodiment illustrated in FIG. Further, such a highly reliable semiconductor device can be manufactured with high yield and high productivity can be achieved.

The capacitor 520 includes conductive layers 521a and 521b, a gate insulating layer 502, an oxide semiconductor layer 522, and a conductive layer 523. The conductive layers 521a and 521b and the conductive layer 523 include the gate insulating layer 502 and the oxide semiconductor layer 522. Capacitance is formed by adopting a structure that sandwiches.

The wiring layer intersection 530 is an intersection between the gate electrodes 511a and 511b and the conductive layer 533, and the gate electrodes 511a and 511b and the conductive layer 533 intersect with each other with the gate insulating layer 502 interposed therebetween.

In this embodiment, a titanium film with a thickness of 30 nm is used as the gate electrode 511a and the conductive layer 521a, and a copper thin film with a thickness of 200 nm is used as the gate electrode 511b and the conductive layer 521b. Therefore, the gate electrode has a laminated structure of a titanium film and a copper thin film.

As the oxide semiconductor layers 512 and 522, an In—Ga—Zn-based oxide film with a thickness of 25 nm is used.

An interlayer insulating layer 504 is formed over the transistor 510, the capacitor 520, and the wiring layer intersection 530, and a color filter layer 505 is provided in a region overlapping with the light-emitting element 540 on the interlayer insulating layer 504. An insulating layer 506 functioning as a planarization insulating layer is provided over the interlayer insulating layer 504 and the color filter layer 505.

A light-emitting element 540 including a stacked structure in which a first electrode layer 541, an electroluminescent layer 542, and a second electrode layer 543 are stacked in this order is provided over the insulating layer 506. The light-emitting element 540 and the transistor 510 are electrically connected to each other when the first electrode layer 541 and the conductive layer 513a are in contact with each other in an opening formed in the insulating layer 506 and the interlayer insulating layer 504 reaching the conductive layer 513a. . Note that a partition 507 is provided so as to cover part of the first electrode layer 541 and the opening.

A photosensitive acrylic film with a thickness of 1500 nm can be used for the insulating layer 506, and a photosensitive polyimide film with a thickness of 1500 nm can be used for the partition 507.

As the color filter layer 505, for example, a chromatic translucent resin can be used. As the chromatic translucent resin, a photosensitive or non-photosensitive organic resin can be used. However, the use of a photosensitive organic resin layer can reduce the number of resist masks, thereby simplifying the process. preferable.

A chromatic color is a color excluding achromatic colors such as black, gray, and white, and the color filter layer is formed of a material that transmits only colored chromatic light. As the chromatic color, red, green, blue, or the like can be used. Further, cyan, magenta, yellow (yellow), or the like may be used. To transmit only colored chromatic light means that the transmitted light in the color filter layer has a peak at the wavelength of the chromatic light. In the color filter layer, the optimum film thickness may be appropriately controlled in consideration of the relationship between the concentration of the coloring material to be included and the light transmittance. For example, the thickness of the color filter layer 505 may be 1500 nm or more and 2000 nm or less.

In the light-emitting device illustrated in FIG. 5B, the light-emitting element 4513 which is a display element is electrically connected to a transistor 4010 provided in the pixel portion 4002. Note that although the structure of the light-emitting element 4513 is a stacked structure of the first electrode layer 4034, the electroluminescent layer 4511, and the second electrode layer 4031, it is not limited to the structure shown. The structure of the light-emitting element 4513 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4513, or the like.

The partition walls 4510 and 507 are formed using an organic insulating material or an inorganic insulating material. In particular, a photosensitive resin material is used, and openings are formed on the first electrode layers 4034 and 541 so that the side walls of the openings are inclined surfaces formed with continuous curvature. preferable.

The electroluminescent layers 4511 and 542 may be composed of a single layer or a plurality of layers stacked.

A protective film may be formed over the second electrode layers 4031 and 543 and the partition walls 4510 and 507 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting elements 4513 and 540. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

Alternatively, a layer containing an organic compound that covers the light-emitting element 4513 may be formed by an evaporation method so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting elements 4513 and 540.

A space sealed by the substrate 4001, the substrate 4006, and the sealant 4005 is provided with a filler 4514 and sealed. Thus, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material that has high air tightness and little degassing so as not to be exposed to the outside air.

In addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used as the filler 4514. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl) Butyl) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the light emitting element exit surface. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

In addition, as a display device, electronic paper that drives electronic ink can be provided. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the same readability as paper, low power consumption compared to other display devices, and the advantage that it can be made thin and light. ing.

The electrophoretic display device may have various forms, and a plurality of microcapsules including first particles having a positive charge and second particles having a negative charge are dispersed in a solvent or a solute. By applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to display only the color of the particles assembled on one side. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. In addition, the color of the first particles and the color of the second particles are different (including colorless).

As described above, the electrophoretic display device is a display using a so-called dielectrophoretic effect in which a substance having a high dielectric constant moves to a high electric field region.

A solution in which the above microcapsules are dispersed in a solvent is referred to as electronic ink. This electronic ink can be printed on a surface of glass, plastic, cloth, paper, or the like. Color display is also possible by using particles having color filters or pigments.

Note that the first particle and the second particle in the microcapsule are a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, or a magnetophoresis. A kind of material selected from the materials or a composite material thereof may be used.

In addition, a display device using a twisting ball display system can be used as the electronic paper. The twist ball display method is a method in which spherical particles separately painted in white and black are arranged between a first electrode layer and a second electrode layer which are electrode layers used for a display element, and the first electrode layer and In this method, a potential difference is generated in the second electrode layer to control the orientation of spherical particles.

3 to 5, as the substrates 4001, 500 and 4006, a flexible substrate can be used in addition to a glass substrate, for example, a light-transmitting plastic substrate can be used. . As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. In addition, a metal substrate (metal film) such as aluminum or stainless steel may be used if translucency is not necessary. For example, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or polyester films can be used.

The insulating layers 4021 and 506 functioning as planarization insulating layers can be formed using a heat-resistant organic material such as acrylic, polyimide, benzocyclobutene-based resin, polyamide, or epoxy. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used. Note that the insulating layer may be formed by stacking a plurality of insulating layers formed using these materials.

The formation method of the insulating layers 4021 and 506 is not particularly limited, and according to the material, sputtering method, spin coating, dip, spray coating, droplet discharge method (inkjet method), screen printing, offset printing, doctor knife, A roll coater, curtain coater, knife coater, or the like can be used.

The display device performs display by transmitting light from a light source or a display element. Therefore, thin films such as a substrate, an insulating layer, and a conductive layer provided in the pixel portion where light is transmitted have a light-transmitting property with respect to light in the visible wavelength region.

In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, or the like) that applies a voltage to the display element, the direction of light to be extracted, the place where the electrode layer is provided, and What is necessary is just to select translucency and reflectivity by the pattern structure of an electrode layer.

The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium tin containing titanium oxide. A light-transmitting conductive material such as oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or graphene can be used.

The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), Metals such as tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or the like One or a plurality of types of alloys or metal nitrides thereof can be used.

In this embodiment mode, the light-emitting device illustrated in FIG. 4 is a bottom emission type; thus, the first electrode layer 541 has a light-transmitting property and the second electrode layer 543 has a reflecting property. Therefore, when a metal film is used for the first electrode layer 541, the film thickness is thin enough to maintain translucency, and when a conductive layer having a light-transmitting property is used for the second electrode layer 543, a conductive material having a reflective property is used. Layers may be stacked.

The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

In addition, since the transistor is easily broken by static electricity or the like, it is preferable to provide a protective circuit for protecting the driving circuit. The protection circuit is preferably configured using a non-linear element.

As described above, by using the transistor described in Embodiment 1, a semiconductor device having various functions can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
With the use of the transistor described in Embodiment 1, a semiconductor device having an image sensor function of reading information on an object can be manufactured.

FIG. 6A illustrates an example of a semiconductor device having an image sensor function. FIG. 6A is an equivalent circuit of the photosensor, and FIG. 6B is a cross-sectional view illustrating part of the photosensor.

In the photodiode 602, one electrode is electrically connected to the photodiode reset signal line 658 and the other electrode is electrically connected to the gate of the transistor 640. In the transistor 640, one of a source and a drain is electrically connected to the photosensor reference signal line 672, and the other of the source and the drain is electrically connected to one of the source and the drain of the transistor 656. The transistor 656 has a gate electrically connected to the gate signal line 659 and the other of the source and the drain electrically connected to the photosensor output signal line 671.

Note that in a circuit diagram in this specification, a symbol of a transistor using an oxide semiconductor layer is described as “OS” so that the transistor can be clearly identified as a transistor using an oxide semiconductor layer. 6A, the transistor described in Embodiment 1 can be applied to the transistor 640 and the transistor 656, which are transistors each using an oxide semiconductor layer. In this embodiment, an example in which a transistor having a structure similar to that of the transistor 420 described in Embodiment 1 is applied is described. The transistor 640 is a bottom-gate transistor.

6B is a cross-sectional view of the photodiode 602 and the transistor 640 in the photosensor. The photodiode 602 and the transistor 640 functioning as a sensor are provided over a substrate 601 (an element substrate) having an insulating surface. Yes. A substrate 613 is provided over the photodiode 602 and the transistor 640 by using an adhesive layer 608.

An insulating layer 631, an interlayer insulating layer 633, and an interlayer insulating layer 634 are provided over the transistor 640. The photodiode 602 includes an electrode layer 641b formed over the interlayer insulating layer 633, a first semiconductor film 606a, a second semiconductor film 606b, and a third semiconductor film 606c sequentially stacked over the electrode layer 641b, and an interlayer insulating layer. An electrode layer 642 provided over the layer 634 and electrically connected to the electrode layer 641b through the first to third semiconductor films, and provided in the same layer as the electrode layer 641b and electrically connected to the electrode layer 642 An electrode layer 641a.

The electrode layer 641b is electrically connected to the conductive layer 643 formed in the interlayer insulating layer 634, and the electrode layer 642 is electrically connected to the conductive layer 645 through the electrode layer 641a. The conductive layer 645 is electrically connected to the gate electrode of the transistor 640, and the photodiode 602 is electrically connected to the transistor 640.

Here, a semiconductor film having a p-type conductivity type as the first semiconductor film 606a, a high-resistance semiconductor film (i-type semiconductor film) as the second semiconductor film 606b, and an n-type conductivity type as the third semiconductor film 606c. A pin type photodiode in which a semiconductor film having the same is stacked is illustrated.

The first semiconductor film 606a is a p-type semiconductor film and can be formed using an amorphous silicon film containing an impurity element imparting p-type conductivity. The first semiconductor film 606a is formed by a plasma CVD method using a semiconductor material gas containing a Group 13 impurity element (eg, boron (B)). Silane (SiH 4 ) may be used as the semiconductor material gas. Alternatively, Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , SiF 4, or the like may be used. Alternatively, after an amorphous silicon film not containing an impurity element is formed, the impurity element may be introduced into the amorphous silicon film by a diffusion method or an ion implantation method. It is preferable to diffuse the impurity element by introducing an impurity element by an ion implantation method or the like and then performing heating or the like. In this case, as a method for forming the amorphous silicon film, an LPCVD method, a vapor phase growth method, a sputtering method, or the like may be used. The first semiconductor film 606a is preferably formed to have a thickness greater than or equal to 10 nm and less than or equal to 50 nm.

The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film) and is formed of an amorphous silicon film. For the formation of the second semiconductor film 606b, an amorphous silicon film is formed by a plasma CVD method using a semiconductor material gas. Silane (SiH 4 ) may be used as the semiconductor material gas. Alternatively, Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , SiF 4, or the like may be used. The second semiconductor film 606b may be formed by an LPCVD method, a vapor deposition method, a sputtering method, or the like. The second semiconductor film 606b is preferably formed to have a thickness greater than or equal to 200 nm and less than or equal to 1000 nm.

The third semiconductor film 606c is an n-type semiconductor film and is formed using an amorphous silicon film containing an impurity element imparting n-type conductivity. The third semiconductor film 606c is formed by a plasma CVD method using a semiconductor material gas containing a Group 15 impurity element (eg, phosphorus (P)). Silane (SiH 4 ) may be used as the semiconductor material gas. Alternatively, Si 2 H 6 , SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , SiF 4, or the like may be used. Alternatively, after an amorphous silicon film not containing an impurity element is formed, the impurity element may be introduced into the amorphous silicon film by a diffusion method or an ion implantation method. It is preferable to diffuse the impurity element by introducing an impurity element by an ion implantation method or the like and then performing heating or the like. In this case, as a method for forming the amorphous silicon film, an LPCVD method, a vapor phase growth method, a sputtering method, or the like may be used. The third semiconductor film 606c is preferably formed to have a thickness greater than or equal to 20 nm and less than or equal to 200 nm.

In addition, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c may be formed using a polycrystalline semiconductor instead of an amorphous semiconductor, or may be formed using a microcrystalline (Semi Amorphous Semiconductor: SAS)) may be formed using a semiconductor.

Further, since the mobility of holes generated by the photoelectric effect is smaller than the mobility of electrons, the pin type photodiode exhibits better characteristics when the p type semiconductor film side is the light receiving surface. Here, an example is shown in which light received by the photodiode 602 from the surface of the substrate 601 on which the pin-type photodiode is formed is converted into an electrical signal. In addition, since light from the semiconductor film side having a conductivity type opposite to that of the semiconductor film as the light receiving surface becomes disturbance light, a conductive layer having a light shielding property is preferably used as the electrode layer. The n-type semiconductor film side can also be used as the light receiving surface.

As the insulating layer 631, the interlayer insulating layer 633, and the interlayer insulating layer 634, an insulating material is used, and a sputtering method, a plasma CVD method, spin coating, dipping, spray coating, a droplet discharge method (inkjet) is used depending on the material. Method), screen printing, offset printing, and the like.

As the insulating layer 631, for example, a single layer or a stacked layer such as a silicon oxynitride layer or a silicon oxynitride layer can be used as the inorganic insulating material.

As the interlayer insulating layers 633 and 634, an insulating layer functioning as a planarization insulating layer is preferable in order to reduce surface unevenness. As the interlayer insulating layers 633 and 634, a heat-resistant organic insulating material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used. In addition to the organic insulating material, a single layer or a stacked layer such as a low dielectric constant material (low-k material), a siloxane-based resin, PSG (phosphorus glass), or BPSG (phosphorus boron glass) can be used.

By detecting light incident on the photodiode 602, information on the object to be detected can be read. Note that a light source such as a backlight can be used when reading information on the object to be detected.

In the manufacturing process, the transistor 640 performs heat treatment on the oxide semiconductor layer including the oxygen-excess region at a temperature at which hydrogen or a hydrogen compound is released or higher. Therefore, the oxide semiconductor layer included in the transistor 640 is an oxide semiconductor layer in which oxygen vacancies are suppressed and impurities such as hydrogen and a hydrogen compound which are factors of variation in electrical characteristics are reduced. Characteristic fluctuation is suppressed.

Therefore, a highly reliable semiconductor device including the transistor 640 having stable electric characteristics using the oxide semiconductor layer of this embodiment can be provided. In addition, a highly reliable semiconductor device can be manufactured with high yield and high productivity can be achieved.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 5)
The semiconductor device disclosed in this specification can be applied to a variety of electronic devices (including game machines). As electronic devices, television devices (also referred to as televisions or television receivers), monitors for computers, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound Examples include a playback device, a gaming machine (such as a pachinko machine or a slot machine), and a game housing. Specific examples of these electronic devices are shown in FIGS.

FIG. 7A illustrates a table 9000 having a display portion. In the table 9000, a display portion 9003 is incorporated in a housing 9001, and an image can be displayed on the display portion 9003. Note that a structure in which the housing 9001 is supported by four legs 9002 is shown. In addition, the housing 9001 has a power cord 9005 for supplying power.

The semiconductor device described in any of the above embodiments can be used for the display portion 9003 and can impart high reliability to the electronic device.

The display portion 9003 has a touch input function. By touching a display button 9004 displayed on the display portion 9003 of the table 9000 with a finger or the like, screen operation or information can be input. It is good also as a control apparatus which controls other household appliances by screen operation by enabling communication with household appliances or enabling control. For example, when the semiconductor device having the image sensor function described in Embodiment 3 is used, the display portion 9003 can have a touch input function.

Further, the hinge of the housing 9001 can be used to stand the screen of the display portion 9003 perpendicular to the floor, which can be used as a television device. In a small room, if a television apparatus with a large screen is installed, the free space becomes narrow. However, if the display portion is built in the table, the room space can be used effectively.

FIG. 7B illustrates a television device 9100. In the television device 9100, a display portion 9103 is incorporated in a housing 9101 and an image can be displayed on the display portion 9103. Note that here, a structure in which the housing 9101 is supported by a stand 9105 is illustrated.

The television device 9100 can be operated with an operation switch included in the housing 9101 or a separate remote controller 9110. Channels and volume can be operated with an operation key 9109 provided in the remote controller 9110, and an image displayed on the display portion 9103 can be operated. The remote controller 9110 may be provided with a display portion 9107 for displaying information output from the remote controller 9110.

A television set 9100 illustrated in FIG. 7B includes a receiver, a modem, and the like. The television apparatus 9100 can receive a general television broadcast by a receiver, and is connected to a wired or wireless communication network via a modem so that it can be unidirectional (sender to receiver) or bidirectional. It is also possible to perform information communication (between the sender and the receiver or between the receivers).

The semiconductor device described in any of the above embodiments can be used for the display portions 9103 and 9107, and can provide high reliability to the television device and the remote controller.

FIG. 7C illustrates a computer, which includes a main body 9201, a housing 9202, a display portion 9203, a keyboard 9204, an external connection port 9205, a pointing device 9206, and the like.

The semiconductor device described in any of the above embodiments can be used for the display portion 9203 and can give high reliability to the computer.

8A and 8B illustrate a tablet terminal that can be folded. FIG. 8A illustrates an open state in which the tablet terminal includes a housing 9630, a display portion 9631a, a display portion 9631b, a display mode switching switch 9034, a power switch 9035, a power saving mode switching switch 9036, and a fastener 9033. And an operation switch 9038.

The semiconductor device described in any of the above embodiments can be used for the display portion 9631a and the display portion 9631b, so that a highly reliable tablet terminal can be provided.

Part of the display portion 9631 a can be a touch panel region 9632 a and data can be input when a displayed operation key 9638 is touched. Note that in the display portion 9631a, for example, a structure in which half of the regions have a display-only function and a structure in which the other half has a touch panel function is shown, but the structure is not limited thereto. The entire region of the display portion 9631a may have a touch panel function. For example, the entire surface of the display portion 9631a can display keyboard buttons to serve as a touch panel, and the display portion 9631b can be used as a display screen.

Further, in the display portion 9631b, as in the display portion 9631a, part of the display portion 9631b can be a touch panel region 9632b. Further, a keyboard button can be displayed on the display portion 9631b by touching a position where the keyboard display switching button 9539 on the touch panel is displayed with a finger or a stylus.

Touch input can be performed simultaneously on the touch panel region 9632a and the touch panel region 9632b.

A display mode switching switch 9034 can switch the display direction such as vertical display or horizontal display, and can select switching between monochrome display and color display. The power saving mode change-over switch 9036 can optimize the display luminance in accordance with the amount of external light during use detected by an optical sensor built in the tablet terminal. The tablet terminal may include not only an optical sensor but also other detection devices such as a gyroscope, an acceleration sensor, and other sensors that detect inclination.

FIG. 8A illustrates an example in which the display areas of the display portion 9631b and the display portion 9631a are the same; however, there is no particular limitation, and one size may differ from the other size, and the display quality may also be high. May be different. For example, one display panel may be capable of displaying images with higher definition than the other.

FIG. 8B illustrates a closed state, in which the tablet terminal includes a housing 9630, a solar cell 9633, and a charge / discharge control circuit 9634. Note that FIG. 8B illustrates a structure including a battery 9635 and a DCDC converter 9636 as an example of the charge / discharge control circuit 9634.

Note that since the tablet terminal can be folded in two, the housing 9630 can be closed when not in use. Accordingly, since the display portion 9631a and the display portion 9631b can be protected, a tablet terminal with excellent durability and high reliability can be provided from the viewpoint of long-term use.

In addition, the tablet terminal shown in FIGS. 8A and 8B has a function for displaying various information (still images, moving images, text images, etc.), a calendar, a date, or a time. A function for displaying on the display unit, a touch input function for performing touch input operation or editing of information displayed on the display unit, a function for controlling processing by various software (programs), and the like can be provided.

Electric power can be supplied to the touch panel, the display unit, the video signal processing unit, or the like by the solar battery 9633 mounted on the surface of the tablet terminal. Note that the solar cell 9633 is preferable because it can efficiently charge the battery 9635 on one or two surfaces of the housing 9630. Note that as the battery 9635, when a lithium ion battery is used, there is an advantage that reduction in size can be achieved.

Further, the structure and operation of the charge and discharge control circuit 9634 illustrated in FIG. 8B will be described with reference to a block diagram in FIG. FIG. 8C illustrates the solar battery 9633, the battery 9635, the DCDC converter 9636, the converter 9637, the switches SW1 to SW3, and the display portion 9631. The battery 9635, the DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 are illustrated. This corresponds to the charge / discharge control circuit 9634 shown in FIG.

First, an example of operation in the case where power is generated by the solar battery 9633 using external light is described. The power generated by the solar battery is boosted or lowered by the DCDC converter 9636 so as to be a voltage for charging the battery 9635. When power from the solar cell 9633 is used for the operation of the display portion 9631, the switch SW1 is turned on, and the converter 9637 increases or decreases the voltage required for the display portion 9631. In the case where display on the display portion 9631 is not performed, the battery 9635 may be charged by turning off SW1 and turning on SW2.

Note that the solar cell 9633 is described as an example of the power generation unit, but is not particularly limited, and the battery 9635 is charged by another power generation unit such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). There may be. For example, it is good also as a structure performed combining a non-contact electric power transmission module which transmits / receives electric power by radio | wireless (non-contact), and another charging means.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

400 substrate 401 gate electrode 402 gate insulating layer 402a gate insulating layer 402b gate insulating layer 403 oxide semiconductor layer 405a source electrode 405b drain electrode 408 insulating layer 420 transistor 421 oxygen 500 substrate 502 gate insulating layer 504 interlayer insulating layer 505 color filter layer 506 Insulating layer 507 Partition 510 Transistor 511a Gate electrode 511b Gate electrode 512 Oxide semiconductor layer 513a Conductive layer 513b Conductive layer 520 Capacitance element 521a Conductive layer 521b Conductive layer 522 Oxide semiconductor layer 523 Conductive layer 530 Wiring layer intersection 533 Conductive layer 540 Light emission Element 541 Electrode layer 542 Electroluminescent layer 543 Electrode layer 601 Substrate 602 Photodiode 606a Semiconductor film 606b Semiconductor film 606c Semiconductor film 608 Adhesive layer 613 Substrate 631 Edge layer 633 Interlayer insulating layer 634 Interlayer insulating layer 640 Transistor 641a Electrode layer 641b Electrode layer 642 Electrode layer 643 Conductive layer 645 Conductive layer 656 Transistor 658 Photodiode reset signal line 659 Gate signal line 671 Photosensor output signal line 672 Photosensor reference signal Line 4001 Substrate 4002 Pixel portion 4003 Signal line driver circuit 4004 Scan line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC
4019 Anisotropic conductive layer 4021 Insulating layer 4030 Insulating layer 4031 Electrode layer 4032 Insulating layer 4033 Insulating layer 4034 Electrode layer 4035 Spacer 4038 Insulating layer 4040 Transistor 4510 Partition 4511 Electroluminescent layer 4513 Light emitting element 4514 Filler 9000 Table 9001 Housing 9002 Leg Portion 9003 Display portion 9004 Display button 9005 Power cord 9033 Fastener 9034 Switch 9035 Power switch 9036 Switch 9038 Operation switch 9100 Television apparatus 9101 Case 9103 Display portion 9105 Stand 9107 Display portion 9109 Operation key 9110 Remote control device 9201 Main body 9202 Case 9203 Display unit 9204 Keyboard 9205 External connection port 9206 Pointing device 9630 Housing 9631 Display Portion 9631a display portion 9631b display portion 9632a region 9632b region 9633 solar cell 9634 charge / discharge control circuit 9635 battery 9636 DCDC converter 9537 converter 9638 operation key 9539 button

Claims (2)

  1. After forming the source electrode and the drain electrode over the oxide semiconductor layer having a region overlapping with the gate electrode,
    Forming an oxygen excess region in at least a part of the oxide semiconductor layer exposed between the source electrode and the drain electrode;
    Forming an insulating layer covering the oxygen-excess region;
    In a state where the insulating layer is in contact with the oxide semiconductor layer, heat treatment is performed at a temperature at which hydrogen or a hydrogen compound is released from the oxide semiconductor layer, or higher than that temperature,
    The heat treatment is performed simultaneously with the formation of the insulating layer,
    A method for manufacturing a semiconductor device, wherein heat treatment for separating hydrogen or a hydrogen compound from the oxide semiconductor layer is performed only once.
  2. Oite to claim 1,
    The method for manufacturing a semiconductor device, wherein the oxygen-excess region is formed by performing oxygen doping treatment on the oxide semiconductor layer.
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