JP2010062153A - Plasma display panel, and base board structure of plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PDP in which an electric discharge delay can be improved effectively even if a stop period is long from the last electric discharge until an address electric discharge. <P>SOLUTION: By the PDP in which a priming particle emitting layer containing magnesium oxide crystallization body to which 1 to 10,000 ppm of halogen element is added is arranged so that the layer is exposed to a discharge space between two base board structures opposedly arranged, since improvement of discharge delay lasts for a long time, the discharge delay in the case the stop period is long although it is relatively small can be suppressed effectively, which results in cost reduction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display panel (hereinafter referred to as “PDP”) and a substrate structure of the PDP.

  FIG. 6 is a perspective view showing a configuration of a conventional PDP. The PDP has a structure in which a front substrate assembly 1 and a back substrate assembly 2 are bonded together. In the front substrate assembly 1, a display electrode 3 made of a transparent electrode 3 a and a metal electrode 3 b is disposed on a front substrate 1 a made of a glass substrate, and the display electrode 3 is covered with a dielectric layer 4. A protective layer 5 made of a magnesium oxide layer having a higher secondary electron emission coefficient is formed on the dielectric layer 4. In the back side substrate structure 2, address electrodes 6 are arranged on a back side substrate 2a made of a glass substrate so as to be orthogonal to the display electrodes, and a partition wall 7 is defined between the address electrodes 6 in order to define a light emitting region. Are provided, and red, green, and blue phosphor layers 8 are formed in regions separated by the partition walls 7 on the address electrodes 6. A discharge gas made of Ne—Xe gas is sealed in an airtight discharge space formed inside the bonded front-side substrate structure 1 and back-side substrate structure 2. Although not shown, the address electrode 6 is covered with a dielectric layer, and the partition wall 7 and the phosphor layer 8 are provided on the dielectric layer.

  In such a PDP, an address discharge is generated by applying a voltage between the address electrode 6 and the display electrode 3 also serving as a scan electrode, and a voltage is applied between the paired display electrodes 3, A reset discharge and a sustain discharge for display are generated.

  PDP has been put into practical use as a large-sized thin television, and in recent years, high definition has been advanced. As the resolution is increased, the number of pixels increases, and the address operation time for deciding whether to turn on or off the cell increases. In order to suppress an increase in the address operation time, it is necessary to reduce the pulse width of the address discharge voltage (also referred to as an address voltage). However, since the time (discharge delay) from when the voltage is applied to when the discharge occurs varies, the discharge may not occur if the pulse width of the address voltage is too small. In that case, there is a problem in that the cell is not properly lit during the display period, thereby degrading the image quality.

  As a means for improving the discharge delay of the PDP, there is a method in which a magnesium oxide crystal layer is provided as an electron emission layer on the front side substrate structure (see, for example, Patent Document 1).

JP 2006-59786 A

  As a result of intensive studies by the present inventors, the method described in Patent Document 1 improves the discharge delay when the pause period from the previous discharge to the address discharge is short (generally about several ms or less). Although the effect is seen, it has been clarified that the improvement effect of the discharge delay is extremely deteriorated when the rest period is long.

  The present invention has been made in view of such circumstances, and provides a PDP that can effectively improve the discharge delay even when the rest period from the previous discharge to the address discharge is long.

  According to the present invention, there is provided a PDP in which a priming particle emission layer including a magnesium oxide crystal added with 1 to 10,000 ppm of a halogen element is exposed so as to be exposed to a discharge space between two opposing substrate structures. Provided.

  As a result of intensive studies, the present inventor has conducted priming particles (hereinafter referred to as “P particles”) including magnesium oxide crystals (hereinafter referred to as “MgO crystals”) to which 1 to 10,000 ppm of a halogen element is added. ) When the emission layer is arranged so as to be exposed to the discharge space, the effect of improving the discharge delay lasts for a long time, effectively improving the discharge delay even when the rest period from the previous discharge to the address discharge is long. As a result, the present invention has been completed.

  The reason why the discharge delay improvement effect lasts for a long time according to the present invention is not necessarily clear, but the added halogen element is replaced with oxygen in the MgO crystal, which becomes an electron trap and the electron emission characteristics are improved. Presumed to be.

  According to the present invention, since the effect of improving the discharge delay lasts for a long time, it is possible to effectively suppress the discharge delay when the rest period is long even if the amount is relatively small, leading to cost reduction.

(A)-(c) is sectional drawing which shows the structure of PDP of one Embodiment of this invention, (a) is a top view, (b) and (c) are respectively (a). It is II sectional drawing and II-II sectional drawing in the inside. In the Example of this invention, it is a graph for calculating | requiring the estimated value of F addition amount of Example sample B, D, E. FIG. The voltage waveform used for the measurement of the discharge delay of the Example of this invention is shown. It is a graph which shows the relationship between a resting period and a discharge delay about PDP manufactured using Example Sample C and PDP manufactured using an additive-free MgO crystal. It is a graph which shows the relationship between the measured value or estimated value of F addition amount, and discharge delay concerning the Example of this invention. It is a perspective view which shows the structure of the conventional PDP.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The configurations shown in the drawings and the following description are merely examples, and the scope of the present invention is not limited to those shown in the drawings and the following description. In the following embodiment, the description will be given by taking a reflection type three-electrode surface discharge type PDP as an example, but the present invention is also applicable to other types of PDPs. For example, the present invention can be applied to a transmission type PDP in which the configurations of the “front side” and the “back side” are reversed, and a PDP having a different number of electrodes, electrode arrangement, discharge type, and the like.

  1A to 1C are cross-sectional views showing the structure of a PDP according to an embodiment of the present invention. Fig.1 (a) is a top view which shows the structure of PDP of this embodiment, FIG.1 (b) and (c) are II sectional drawing and II-II in Fig.1 (a), respectively. It is sectional drawing.

  The PDP according to the present embodiment includes a front side substrate assembly 1 and a back side substrate assembly 2 which are disposed to face each other. The front substrate assembly 1 includes a plurality of display electrodes 3 each composed of a transparent electrode 3a and a metal electrode 3b on the front substrate 1a, a dielectric layer 4 covering the plurality of display electrodes 3, and a dielectric layer 4 P particle emission layer 11 is provided through protective layer 5. The back side substrate structure 2 includes a plurality of address electrodes 6 intersecting (preferably orthogonal) to the display electrode 3 on the back side substrate 1b, a dielectric layer 9 covering the plurality of address electrodes 6, and a partition on the dielectric layer 9 7 and phosphor layer 8. The front side substrate structure 1 and the back side substrate structure 2 are bonded to each other with a sealing material, and a discharge gas (in the airtight discharge space between the front side substrate structure 1 and the back side substrate structure 2 is formed. For example, neon mixed with several percent of xenon) is enclosed. The P particle emission layer 11 is disposed so as to be exposed to the discharge space, and includes an MgO crystal to which 1 to 10,000 ppm of a halogen element is added. Hereinafter, each component will be described in detail.

  1-1. Substrate, Display Electrode, Dielectric Layer, Protective Layer (Front Side Substrate Structure) The front side substrate 1a is not particularly limited, and any substrate known in the art can be used. Specifically, transparent substrates, such as a glass substrate and a plastic substrate, are mentioned.

The display electrode 3 includes, for example, a wide transparent electrode 3a such as ITO or SnO _2, and, for example, Ag, Au, Al, Cu, Cr, and a laminate thereof (for example, Cr / Cu / Cu) for reducing the resistance of the electrode. And a narrow metal electrode 3b made of, for example, a Cr laminated structure. The shapes of the transparent electrode 3a and the metal electrode 3b are not particularly limited, and may be a T shape or a ladder shape. The shapes of the transparent electrode 3a and the metal electrode 3b may be the same or different from each other. For example, the transparent electrode 3a may be T-shaped or ladder-shaped, and the metal electrode 3b may be straight. Moreover, the transparent electrode 3a can also be abbreviate | omitted and the display electrode 3 consists only of the metal electrode 3b in this case.

  Each of the plurality of display electrodes 3 is paired to form a display line. As an electrode arrangement form, an arrangement in which a non-discharge region (also referred to as a reverse slit) is provided between electrode pairs, and electrodes are arranged at equal intervals Thus, the adjacent electrodes are all arranged in any of the ALIS type arrangements in which the discharge region is formed. This pair includes a scan electrode 3Y used for address discharge with the address electrode 6 and a sustain electrode 3X used for sustain discharge with the scan electrode 3Y.

  The dielectric layer 4 can be formed, for example, by applying a low-melting-point glass paste obtained by adding a binder and a solvent to a low-melting-point glass frit on the substrate after the display electrode 3 is formed and baking it. . The dielectric layer 4 may be formed by depositing silicon oxide by CVD or the like on the substrate after the display electrode 3 is formed.

  The protective layer 5 is made of a metal (more specifically, divalent metal) oxide such as magnesium oxide, calcium oxide, strontium oxide, or barium oxide, and is preferably made of magnesium oxide. The protective layer 5 is formed by vapor deposition, sputtering, coating, or the like.

  1-2. Substrate, Address Electrode, Dielectric Layer, Partition Wall, Phosphor Layer (Backside Substrate Structure) The backside substrate 2a is not particularly limited, and any substrate known in the art can be used. Specifically, transparent substrates, such as a glass substrate and a plastic substrate, are mentioned. The address electrode 6 can be composed of, for example, Ag, Au, Al, Cu, Cr, and a laminated body thereof (for example, a laminated structure of Cr / Cu / Cr). The dielectric layer 9 can be formed by the same material and method as the dielectric layer 4.

  The partition wall 7 can be formed by forming a partition wall forming material layer such as a low-melting glass paste on the dielectric layer 9, patterning the partition wall forming material layer by sandblasting or the like, and baking it. The partition wall 7 may be formed by other methods. The shape of the partition wall 7 is not limited, and can be, for example, a stripe shape, a meander shape, a lattice shape, or a ladder shape. For example, the phosphor layer 8 is coated with a phosphor paste containing phosphor powder and a binder in a groove between the adjacent barrier ribs 7 by screen printing or a method using a dispenser, and this is applied to each color (R, G , B) can be repeated and then fired.

  1-3. Priming Particle (P Particle) Emission Layer The P particle emission layer 11 is arranged so as to be exposed to the discharge space, and an MgO crystal added with 1 to 10,000 ppm of a halogen element (hereinafter referred to as an MgO crystal added with a halogen element). (Referred to as “halogen-added MgO crystal”). As used herein, “ppm” is a weight concentration. The P particle releasing material may contain components other than the halogen-added MgO crystal, may contain the halogen-added MgO crystal as a main component, or may consist only of the halogen-added MgO crystal.

  The kind of halogen element is not particularly limited. The halogen element is composed of one or more of fluorine, chlorine, bromine and iodine, for example. Although it has been confirmed that the effect of improving the discharge delay lasts for a long time in the case of fluorine, it is considered that the same effect can be obtained when halogen other than fluorine is added due to the similarity of the electronic state.

  The addition amount of the halogen element is not particularly limited. The addition amount of the halogen element is, for example, 1 to 10000 ppm. In the examples, it has been confirmed that substantially the same effect can be obtained even if the addition amount of the halogen element is changed in the range of 24 to 440 ppm. Therefore, the effect of the addition amount of the halogen element on the effect is not great. If the amount of addition is in the range of about 1 to 10,000 ppm, it is considered that the effect of improving the discharge delay lasts for a long time. The added amount of the halogen element is, for example, 1, 5, 10, 15, 20, 30, 40, 50, 60, 70, 80, 90, 100, 120, 140, 160, 180, 200, 250, 300, 350. , 400, 450, 500, 600, 700, 800, 900, 1000, 1500, 2000, 3000, 4000, 5000, 6000, 7000, 8000, 9000 or 10,000 ppm. The addition amount of the halogen element may be within a range between any two numerical values exemplified here. The addition amount of the halogen element can be measured by combustion-ion chromatography analysis.

  The method for producing the halogen-added MgO crystal is not particularly limited. In one example, the halogen-added MgO crystal can be produced by mixing and firing an MgO crystal and a halogen-containing substance, followed by crushing. The MgO crystal will be described later. Examples of the halogen-containing substance include magnesium halides (magnesium fluoride and the like) and Al, Li, Mn, Zn, Ca, Ce halides. Firing is preferably performed at 1000 to 1700 ° C. The firing temperature is, for example, 1000, 1100, 1200, 1300, 1400, 1500, 1600 or 1700 ° C. The firing temperature may be within a range between any two values exemplified here. The method for crushing the fired product is not particularly limited, and examples thereof include a method of putting the fired product in a mortar and grinding it with a pestle to form a powder.

  The halogen-added MgO crystal is preferably in the form of powder, and the size and shape are not particularly limited, but the average particle size is preferably 0.05 to 20 μm. This is because if the average particle size is too small, the effect of improving the discharge delay is small, and if the average particle size is too large, the P-particle emitting layer 11 is difficult to be formed uniformly.

  The average particle diameter of the halogen-added MgO crystal can be determined according to the following formula. Formula: Average particle diameter = a / (S × ρ) (where a is the shape factor, S is the BET specific surface area determined by the nitrogen adsorption method, and ρ is the true density of the halogen-added MgO crystal. Specifically, the average particle diameter of the halogen-added MgO crystal is, for example, 0.05, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7 0.8, 0.9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 μm . The range of the average particle diameter of the halogen-added MgO crystal may be between any two of the numerical values exemplified as the specific average particle diameter.

  Next, the MgO crystal used for manufacturing the halogen-added MgO crystal will be described. The MgO crystal has a characteristic of performing cathodoluminescence emission having a peak in a wavelength range of 200 to 300 nm by irradiation with an electron beam. The MgO crystal is preferably in a powder form, and the size and shape are not particularly limited, but the average particle diameter is preferably 0.05 to 20 μm.

  The average particle diameter of the MgO crystal can be determined according to the following formula. Formula: Average particle size = a / (S × ρ) (where a is a shape factor of 6, S is a BET specific surface area determined by a nitrogen adsorption method, and ρ is a true density of magnesium oxide) MgO crystal Specifically, the average particle size of the body is, for example, 0.05, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 μm. The range of the average particle diameter of the MgO crystal may be between any two of the numerical values exemplified as the specific average particle diameter.

  The production method of the MgO crystal is not particularly limited, but is preferably produced by a gas phase method in which magnesium vapor and oxygen are reacted. For example, the method described in JP-A No. 2004-182521, “Material” It can be produced by the method described in “Synthesis and properties of magnesia powder by vapor phase method” on pages 1157 to 1161 of the November 1987 issue, Vol. 36, No. 410. The MgO crystal may be purchased from Ube Materials Corporation. The production by the vapor phase method is preferable because a single crystal having high purity can be obtained when the MgO crystal is produced by the vapor phase method.

  The P particle emission layer 11 can be disposed on the dielectric layer 4 directly or via another layer. In FIG. 1, the P particle emission layer 11 is disposed on the dielectric layer 4 via the protective layer 5. The configuration of FIG. 1 is an example, and the P particle emission layer 11 may be disposed anywhere in the discharge space so as to be exposed to the discharge space between the front side substrate structure 1 and the back side substrate structure 2. That's fine. This is because if the P particle emission layer 11 is disposed somewhere in the discharge space, the discharge delay is improved by the P particles from the P particle emission layer 11. The P particle emission layer 11 is preferably exposed entirely in the discharge space, but may be partially exposed.

  For example, the P particle emission layer 11 may be disposed on the front substrate assembly 1 or the back substrate assembly 2. When the P particle emission layer 11 is arranged on the front substrate assembly 1, the protective layer 5 may be omitted and the P particle emission layer 11 may be arranged on the dielectric layer 4, and the protective layer 5 having an opening is formed as a dielectric. The P particle emission layer 11 may be disposed on the body layer 4 and in the opening.

  The thickness and shape of the P particle release layer 11 are not particularly limited. The P particle emission layer 11 may be disposed on the entire surface of the display region, or may be disposed only on a part thereof. For example, it may be formed only in a region overlapping the display electrode 3 in a front view or only in a region overlapping the scan electrode 3Y. In this case, it is possible to reduce the usage amount of the P particle emitting material without significantly reducing the effect of improving the discharge delay. Alternatively, it may be formed only in a region overlapping with the metal electrode 3b, or may be formed only in a region overlapping with a non-discharge line (reverse slit) between display electrode pairs where surface discharge does not occur. In this case, a decrease in luminance due to the formation of the P particle emission layer 11 can be suppressed. The P particle emission layer 11 may be formed in a straight shape, or may be formed in an island shape separated for each discharge cell.

  The method for forming the P particle release layer 11 is not particularly limited. The P particle releasing layer 11 can be formed, for example, by spraying the powdery P particle releasing material as it is or dispersed in the dispersion medium toward the protective layer 5. Further, the P particle emitting material may be attached on the protective layer 5 by screen printing. Further, the P particle release layer 11 may be formed by attaching a paste or suspension containing the P particle release material to a portion where the P particle release layer 11 is formed using a dispenser or an inkjet device.

  Examples of the present invention will be described below. In the following examples, the discharge delay improvement effect by arranging the MgO crystal added with fluorine (hereinafter referred to as “F-added MgO crystal”) so as to be exposed to the discharge space was examined. Moreover, it compared with the case where it arrange | positions so that the normal MgO crystal body to which fluorine is not added may be exposed to discharge space.

  1. Production Method of F-added MgO Crystals Five types of F-added MgO crystals (referred to as Example Samples A to E) having different F addition amounts were produced by the following method.

First, MgO crystals (product name: high-purity ultrafine magnesia (2000A) manufactured by Ube Materials Co., Ltd.) and MgF ₂ (manufactured by Furuuchi Chemical Co., Ltd., purity: 99.99%) and mortar Using a pestle, the mixture was pulverized and powdered. Next, the aggregated and crushed MgO crystal and MgF ₂ were weighed so as to have the mixing amount shown in Table 1, and mixed with a tumbler mixer. Next, the mixture was baked in the atmosphere at 1450 ° C. for 1 hour. Next, the fired powder was agglomerated and pulverized to form powder, and F-added MgO crystals of Example Samples A to E were obtained.

  Next, the F addition amount of Example Samples A and C was measured by combustion ion chromatography analysis. The results are shown in Table 1. Moreover, the estimated value of F addition amount of Example sample B, D, E estimated from the measured value of F addition amount of Example sample A and C was calculated | required according to the graph of FIG. In Table 1, the estimated value of the amount of F added is displayed in parentheses.

  2. PDP Manufacturing Method Next, a PDP having the P particle release layer 11 made of the F-added MgO crystal of Example Sample A, B, C, D, or E was manufactured by the following method. In addition, in order to use in a comparative example of a discharge delay test described later, a PDP is formed in the same manner using a MgO crystal (manufacturer, product name is the same as above) in which F is not added instead of the F-added MgO crystal. Manufactured under conditions.

  2-1. 1. Overview As shown in FIGS. 1A to 1C, a front-side substrate assembly 1 is manufactured by forming a display electrode 3, a dielectric layer 4, a protective layer 5, and a P particle emission layer 11 on a glass substrate 1a. . Further, the back-side substrate assembly 2 was fabricated by forming the address electrode 6, the dielectric layer 9, the partition wall 7, and the phosphor layer 8 on the glass substrate 2a. Next, the front side substrate structure 1 and the back side substrate structure 2 were overlapped and the peripheral edge portion was sealed with a sealing material to produce a panel having an airtight discharge space inside. Next, after exhausting the inside of the discharge space, a discharge gas was enclosed to complete the PDP.

2-2. Method for Forming P Particle Release Layer The P particle release layer 11 was formed in detail by the following method. First, the F-added MgO crystal was mixed at a ratio of 2 g to 1 L of IPA (manufactured by Kanto Chemical Co., Ltd., for electronic industry), dispersed with an ultrasonic disperser, and agglomerated and disintegrated to prepare a slurry. Next, the P particle release layer 11 was formed by repeating the process of spraying the slurry on the protective layer 5 using a coating spray gun and then spraying and drying with dry air several times. The P particle release layer 11 was formed so that the weight of the F-added MgO crystal was ² g per m ² .

  2-3. Other Other conditions are as follows.

  Front side substrate structure 1: width of display electrode 3a: 270 μm metal electrode 3b width: 95 μm width of discharge gap: 100 μm dielectric layer 4: formed by applying and baking low melting point glass paste, thickness: 30 μm protective layer 5: electron beam MgO layer by vapor deposition, thickness: 7500mm

Back side substrate structure 2: Width of address electrode 6: 70 μm Dielectric layer 9: formed by applying and baking low melting point glass paste, thickness: 10 μm Thickness of phosphor layer 8 directly above address electrode 6: 20 μm Fluorescence Material of body layer 8: Zn ₂ SiO ₄ : Mn (green phosphor) Height of partition wall 7: 140 μm Width at top: 50 μm Pitch of partition wall 7 (dimension A in FIG. 1A): 360 μm Discharge gas: Ne96 % -Xe4%, 500 Torr

  3. Next, a discharge delay test was performed on each manufactured PDP. The discharge delay test was performed using the voltage waveform for measurement shown in FIG. In the reset discharge period, a reset discharge is caused between the sustain electrode 3X and the scan electrode 3Y to reset the charge state of the dielectric layer, thereby removing the influence of the previous discharge. In the preliminary discharge period, after a specific cell was selected, a discharge was caused between the sustain electrode 3X and the scan electrode 3Y to excite the P particle emitting material. Thereafter, after a rest period of 10 μs to 50 ms had elapsed, a voltage was applied to the address electrode 6 during the address discharge period, and the time from when this voltage was applied until when the discharge was actually started was measured. The time until the start of discharge was measured 1000 times, and the time when the cumulative discharge probability was 90% was defined as the discharge delay.

  The results thus obtained are shown in Table 2, FIG. 4 and FIG. FIG. 4 is a graph showing the relationship between the rest period and the discharge delay for a PDP manufactured using Example Sample C and a PDP manufactured using an additive-free MgO crystal. FIG. 5 is a plot of Table 2.

  As is clear from FIG. 4, the PDP manufactured using the example sample C has a shorter discharge delay than the PDP manufactured using the additive-free MgO crystal, even when the rest period is long. This means that the F-added MgO crystal as in Example Sample C has a longer effect of suppressing the discharge delay than the additive-free MgO crystal.

  Further, as apparent from Table 2 and FIG. 5, it can be seen that the change in the discharge delay is small when the F addition amount is in the range of 24 to 440 ppm. This indicates that the addition amount of the F element does not significantly affect the discharge delay improvement effect. If the addition amount is in the range of about 1 to 10,000 ppm, the discharge delay improvement effect lasts for a long time. This is thought to suggest.

  1: Front side substrate structure 1a: Front side substrate 2: Back side substrate structure 2a: Back side substrate 3: Display electrode 3a: Transparent electrode 3b: Metal electrode 3X: Sustain electrode 3Y: Scan electrode 4: Dielectric layer 5: Protection Layer 6: Address electrode 7: Partition 8: Phosphor layer 9: Dielectric layer 11: Priming particle emission layer

Claims (9)

  A plasma display panel in which a priming particle emission layer including a magnesium oxide crystal added with 1 to 10000 ppm of a halogen element is disposed so as to be exposed to a discharge space between two substrate structures disposed to face each other.   The plasma display panel according to claim 1, wherein the halogen element is fluorine.   The plasma display panel according to claim 2, wherein the amount of fluorine added is 5 to 1000 ppm.   One of the said board | substrate structures is provided with the display electrode and the dielectric material layer which covers the said display electrode on a board | substrate, The said priming particle | grain emission layer is arrange | positioned on the said dielectric material layer. The plasma display panel according to any one of the above.   The plasma display panel according to claim 4, wherein a protective layer made of magnesium oxide is provided between the dielectric layer and the priming particle emitting layer.   A substrate, a plurality of display electrodes provided on the substrate, a dielectric layer covering the display electrodes, and a priming particle emission layer provided on the dielectric layer and in contact with the discharge space A substrate structure of a plasma display panel comprising the substrate structure of a plasma display panel, wherein the priming particle emitting layer is composed of a magnesium oxide crystal to which 1 to 10,000 ppm of a halogen element is added.   The substrate structure of a plasma display panel according to claim 6, wherein a protective layer made of magnesium oxide is provided between the dielectric layer and the priming particle emitting layer.   The substrate structure of the plasma display panel according to claim 6, wherein the halogen element is fluorine. The substrate structure of a plasma display panel according to claim 8, wherein the amount of fluorine added is 5 to 1000 ppm.

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