JP2010055088A - Display device and method of driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device with improved display quality and a method of driving the same. <P>SOLUTION: The display device includes: a display panel which includes many dither blocks displaying an image that corresponds to a dither image signal, each of the dither blocks including many pixels driven having respective polarities inverted every frame; and an image signal controller which generates the dither image signal by using a dither pattern that determines a plurality of dither pixels, which are to be dithered, from among the many pixels included in each of the dither blocks, wherein each of the dither blocks comprises equal numbers of positive-polarity dither pixels and negative-polarity dither pixels. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device and a driving method thereof, and more particularly to a display device capable of improving display quality and a driving method thereof.

  The display device generally includes a display panel and a panel driving unit. The display panel includes a first display panel having a pixel electrode, a second display panel having a common electrode, and a dielectric anisotropy injected between the first display panel and the second display panel. The liquid crystal molecule may be included. The panel driving unit includes a gate driver that applies gate signals to a large number of gate lines, a data driver that outputs video data voltages to a large number of data lines, and a signal control unit that outputs signals for controlling the operation of the gate driver and the data driver. May be included.

  The signal control unit may output a dithered video signal by applying a dithering pattern to a video signal provided from the outside in order to improve display quality. The dithering pattern determines dithering pixels to be dithered among pixels in each dithering block. By such dithering processing, an image having multiple gradations can be expressed. However, as a result of the dithering process, the horizontal line or the vertical line may be visually recognized or flicker may occur, thereby degrading the display quality of the display device.

Korean Patent Publication No. 10-2008-0045839

  The problem to be solved by the present invention is to provide a display device capable of improving display quality.

  Other problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

  An embodiment of a display device of the present invention for solving the above problems includes a plurality of dithering blocks that display video corresponding to a dithering video signal, and each dithering block has a polarity inverted every frame. A dithering video signal using a display panel including a large number of driven pixels and a dithering pattern that determines a plurality of dithering pixels to be dithered from among a large number of pixels in each dithering block. And the number of positive dithering pixels included in each dithering block is equal to the number of negative dithering pixels.

  Other specific details of the invention are included in the detailed description and figures.

1 is a block diagram illustrating a display device and a driving method thereof according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of one pixel (PX) included in the display panel of FIG. 1. It is a block diagram for demonstrating the signal control part of FIG. FIG. 4 is a block diagram for explaining that the video signal control unit of FIG. 3 reads a dithering pattern from the dithering memory of FIG. 1. It is a table | surface which shows the dithering set corresponding to each dithering level. 6 is a table for explaining a process of setting each dithering pattern in FIG. 5 by taking a second dithering pattern as an example. 6 is a table for explaining a process of setting each dithering pattern in FIG. 5 by taking a second dithering pattern as an example. 6 is a table for explaining a series of dithering pattern settings for each dithering level in FIG. 5. 6 is a table for explaining a series of dithering pattern settings for each dithering level in FIG. 5. 3 is a flowchart for explaining a display device driving method according to an exemplary embodiment of the present invention;

  The advantages, features, and methods of achieving the same of the present invention will become apparent with reference to the embodiments described in detail later in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below, and can be implemented in various different forms. This embodiment is provided merely for the purpose of completely informing the person skilled in the art to which the present invention pertains the scope of the invention so that the disclosure of the present invention is complete. The invention is defined only by the claims. Throughout the specification, the same reference numerals denote the same components. “And / or” includes each and every combination of one or more of the items mentioned.

  The first, second, etc. are used to describe various elements, components and / or sections. However, these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, component, or section from another element, component, or section. Therefore, the first element, the first component, or the first section mentioned below can be the second element, the second component, or the second section within the technical idea of the present invention.

  The terminology used herein is for the purpose of describing embodiments and is not intended to limit the invention. In this specification, the singular includes the plural unless specifically stated otherwise. As used herein, “comprises” and / or “comprising” refers to a component, stage, operation, and / or element referred to is one or more other components, stages, operations And / or the presence or addition of elements is not excluded.

  FIG. 1 is a block diagram for explaining a display device and a driving method thereof according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of one pixel (PX) included in the display panel of FIG.

  Referring to FIG. 1, the display device 10 may include a display panel 300, a signal controller 600, a dithering memory 800, a gate driver 400, a data driver 500, and a gradation voltage generator 700.

  The display panel 300 includes a number of gate lines G1 to Gn, a number of data lines D1 to Dm, and a number of pixels PX. The gate lines G1 to Gn are extended substantially in the row direction and are substantially parallel to each other, and the data lines D1 to Dm are extended substantially in the column direction and are substantially parallel to each other. Each pixel (PX) is defined in a region where each gate line (G1 to Gn) and each data line (D1 to Dm) intersect. Each gate signal is input from the gate driver 400 to each gate line (G1 to Gn), and each video data voltage is input from the data driver 500 to each data line (D1 to Dm). Each pixel (PX) displays an image in response to each image data voltage.

  As will be described later, the signal controller 600 may output a dithering video signal (IDAT) to the data driver 500, and the data driver outputs a video data voltage corresponding to the dithering video signal (IDAT). Also good. Since each pixel (PX) displays a video in response to each video data voltage, the pixel (PX) included in the display panel 300 finally displays a video corresponding to the dithering video signal (IDAT). May be.

  The display panel 300 may include a number of dithering blocks (not shown) that display video in response to a dithering video signal (IDAT). A dithering pattern may be applied to each dithering block included in the display panel 300. Each dithering pattern may be applied to pixels (see FIG. 5) arranged in a 4 × 4 matrix, for example. Furthermore, each dithering block may include a large number of pixels (PX) that are driven with the polarity reversed for each frame. This will be described later when each dithering pattern is described.

  FIG. 2 shows an equivalent circuit for one pixel. A pixel (PX), for example, a pixel (PX) connected to an i-th (i = 1 to n) gate line (Gi) and a j-th (j = 1 to m) data line (Dj) A switching element Q connected to the line Gi and the data line Dj, and a liquid crystal capacitor (Clc) and a storage capacitor (Cst) connected thereto. The liquid crystal capacitor (Clc) is interposed between two electrodes, for example, a pixel electrode (PE) of the first display panel 100 and a common electrode (CE) of the second display panel 200 as shown in the figure. The liquid crystal molecules 150 may be formed. When the switching element (Q) is turned on, the video data voltage applied to the jth data line (Dj) is applied to the pixel electrode (PE). The liquid crystal capacitor (Clc) is charged with a voltage difference between the common voltage (Vcom) applied to the common electrode (CE) and the video data voltage applied to the pixel electrode (PE). A color filter (CF) is formed on a part of the common electrode (CE).

  Referring to FIG. 1 again, the signal controller 600 receives the original video signal (RGB) and the external control signals (DE, Hsync, Vsync, Mclk) for controlling the display of the original video signal (RGB), and the dithering video. A signal (IDAT), a gate control signal (CONT1), and a data control signal (CONT2) are output.

  Specifically, the signal controller 600 may receive an original video signal (RGB) and output a dithering video signal (IDAT). The signal controller 600 may also receive external control signals (DE, Hsync, Vsync, Mclk) from the outside and generate a gate control signal (CONT1) and a data control signal (CONT2). Examples of the external control signal include a data enable signal (DE), a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a main clock signal (Mclk). The gate control signal (CONT1) is a signal for controlling the operation of the gate driver 400, and the data control signal (CONT2) is a signal for controlling the operation of the data driver 500. The signal control unit 600 will be described in more detail with reference to FIG.

  A series of dithering patterns corresponding to dithering levels may be stored in the dithering memory 800 in the form of a lookup table. The signal control unit 600 may read the dithering pattern from the dithering memory 800 and apply the read dithering pattern to the original video signal (RGB) to output the dithering video signal (IDAT). This will be described in more detail with reference to FIG.

  The gate driver 400 receives the gate control signal (CONT1) from the signal control unit 600 and applies the gate signal to the gate lines (G1 to Gn). Here, the gate signal may include a gate on voltage (Von) and a gate off voltage (Voff) provided from a gate on / off voltage generator (not shown).

  The data driver 500 receives the data control signal (CONT2) from the signal controller 600 and applies video data voltages corresponding to the dithering video signal (IDAT) to the data lines (D1 to Dm). The video data voltage to which the dithering video signal (IDAT) is applied may be a voltage provided from the gradation voltage generator 700.

  The gray voltage generator 700 may divide the driving voltage (AVDD) into a plurality of video data voltages based on the gray level of the dithering video signal (IDAT) and provide the video data voltage to the data driver 500. Good. The gray voltage generator 700 includes a plurality of resistors connected in series between a node to which the drive voltage (AVDD) is applied and the ground, and divides the voltage level of the drive voltage (AVDD) to generate a plurality of levels. A regulated voltage can be generated. The internal circuit of the gradation voltage generator 700 is not limited to this and can be implemented in various ways.

  FIG. 3 is a block diagram for explaining the signal control unit 600 of FIG.

  Referring to FIG. 3, the signal controller 600 may include a video signal controller 610 and a control signal generator 620.

  The video signal controller 610 reads the dithering pattern stored in the dithering memory 800, generates a dithering video signal (IDAT) using the read dithering pattern, and a data driver (see 500 in FIG. 1). ) May transmit a dithering video signal (IDAT).

  The bit number of the original video signal (RGB) provided to the video signal controller 610 is the first bit number, and the bit number of the dithering video signal (IDAT) is the second bit number smaller than the first bit number. Also good. The number of bits of the video data voltage output from the gradation voltage generator (see 700 in FIG. 1) may also be the second number of bits that is the number of bits of the dithering video signal (IDAT).

  Each dithering block included in the display panel (see 300 in FIG. 1) displays an image corresponding to the dithered video signal (IDAT) obtained by dithering the original video signal (RGB). As a result, each dithering block corresponds to the original video signal (RGB) even if the bit number of the dithering video signal (IDAT) and the bit number of the video data voltage are smaller than the bit number of the original video signal (RGB). The video can be expressed almost the same as the video to be played. This will be described in more detail with reference to FIG.

  The control signal generation unit 620 may receive an external control signal (DE, Hsync, Vsync, Mclk) from the outside, and generate and output a gate control signal (CONT1) and a data control signal (CONT2). Here, the data enable signal (DE) maintains a high level during a period in which the original video signal (RGB) is input, and a signal provided from the outside, for example, a graphic control unit (not shown) is the original video. It is a signal indicating that it is a signal (RGB). The vertical synchronization signal (Vsync) is a signal notifying the start of one frame, the horizontal synchronization signal (Hsync) is a signal for distinguishing gate lines, and the main clock signal (Mclk) is necessary for the operation of the display device 10. This is a clock signal synchronized with all signals.

  The gate control signal (CONT1) is a signal for controlling the operation of the gate driver 400. The gate control signal (CONT1) includes a vertical start signal (STV) for starting the operation of the gate driver 400, a gate clock signal (CPV) for determining the output timing of the gate-on voltage, and an output enable signal for determining the pulse width of the gate-on voltage. (OE) or the like may be included. The data control signal (CONT2) is a signal that controls the operation of the data driver 500. The data control signal (CONT2) may include a horizontal start signal (STH) for starting the operation of the data driver 500, an output instruction signal (TP) for instructing output of the video data voltage, and the like.

  FIG. 4 is a block diagram for explaining that the video signal control unit 610 in FIG. 3 reads the dithering pattern from the dithering memory 800 in FIG.

  Referring to FIG. 4, the video signal controller 610 determines a dithering level with reference to LSB (Least Significant Bits) of the original video signal (RGB), and generates a series of dithering patterns corresponding to the determined dithering level. You may read from the dithering memory 800. Here, LSB of the original video signal (RGB) means the number of least significant digits of the original video signal (RGB).

  The video signal control unit 610 may include a multiplexer 630 and a dithering processor 640.

  The multiplexer 630 uses the LSB (Least Significant Bits) of the original video signal (RGB) as a selection signal, and corresponds to the determined dithering level among a plurality of dithering sets stored in the dithering memory 800. A series of dithering patterns included in a certain dithering set may be read out. In FIG. 4, each of the first to eighth dithering patterns (810 to 880) indicates a series of dithering patterns corresponding to each dithering level, that is, each dithering set. FIG. 4 illustrates the case where the LSB of the original video signal (RGB) is the lower 3 bits.

  For example, if the LSB is 000, the first dithering pattern 810 is read, and if the LSB is 001, the second dithering pattern 820 is read. If LSB is 010, a third dithering pattern (not shown) is read, and if LSB is 011, a fourth dithering pattern (not shown) is read. If LSB is 100, a fifth dithering pattern (not shown) is read, and if LSB is 101, a sixth dithering pattern (not shown) is read. If LSB is 110, the seventh dithering pattern 870 is read, and if LSB is 111, the eighth dithering pattern 880 is read.

  The dithering processor 640 receives the dithering pattern (DTP), dithers the original video signal (RGB), and outputs a dithering video signal (IDAT). Although the dithering video signal (IDAT) has a smaller number of bits than the original video signal (RGB), the dithering pattern (DTP) is applied, so that the number of gradations is higher than that when the dithering pattern (DTP) is not applied. Can be expressed. That is, the dithering video signal (IDAT) may include video information included in the LSB of the original video signal (RGB) through dithering. This will be described in more detail with reference to FIG.

  The dithering memory 800 may store a series of dithering patterns corresponding to each dithering level of the original video signal (RGB) in the form of a look-up table.

  FIG. 5 is a table showing a dithering set corresponding to each dithering level.

With reference to FIG. 5, the case where the dithering video signal (IDAT) includes video information included in the LSB of the original video signal (RGB) will be described in more detail. As shown in FIG. 5, if the LSB of the original image signal (RGB) is 3 digits can represent 2 ^three dither level. Lower 3 bits (LSB 3 bits) “000”, “001”, “010”, “011”, “100”, “101”, “110” and “111” are dithering levels “0/8”, “ It may correspond to 1/8 ',' 2/8 ',' 3/8 ',' 4/8 ',' 5/8 ',' 6/8 'and' 7/8 '.

  The number of dithering pixels in each dithering block may be determined according to the dithering level. Here, the dithering pixel means a pixel to be dithered among many pixels included in each dithering block. The pixel to be dithered may be driven by data obtained by adding 1 to the data of the upper bits that are bits of the original video signal (RGB) excluding the lower 3 bits. That is, a video data voltage having a voltage value corresponding to data obtained by adding 1 to the data of the upper bits of the original video signal (RGB) may be applied to the pixel to be dithered. The video data voltage applied to the pixels that are not to be dithered may be a video data voltage having a voltage value corresponding to the upper bit data of the original video signal (RGB).

  Dithering levels' 0/8 ',' 1/8 ',' 2/8 ',' 3/8 ',' 4/8 ',' 5/8 ',' 6/8 ', and' 7/8 Depending on ', the number of dithering pixels in each dithering block may be determined as 0, 2, 4, 6, 8, 10, 12, 14, and 16, respectively. Good. Each dithering pattern shown in FIG. 5 displays a plurality of dithering pixels to be dithered out of a large number of pixels in each dithering block by hatching.

  Specifically, in order to display a case where the lower 3 bits of the original video signal (RGB) are “000”, all the 16 adjacent pixels correspond to the upper bit data of the original video signal (RGB). It may be driven by the video data voltage. In order to display a case where the lower 3 bits of the original video signal (RGB) are “001”, two of the 16 adjacent pixels are set to the upper bits of the original video signal (RGB). When driving with a video data voltage corresponding to data obtained by adding 1 to data, a video in which 16 pixels have an average of lower 3 bits of “001” can be displayed.

  Similarly, when the lower 3 bits of the original video signal (RGB) are “010”, four of the 16 adjacent pixels are set, and the lower 3 bits of the original video signal (RGB) are “011”. Is 6 pixels out of the 16 adjacent pixels, and 8 pixels out of the 16 adjacent pixels when the lower 3 bits of the original video signal (RGB) are '100'. When the lower 3 bits of the original video signal (RGB) are “101”, 10 pixels out of the adjacent 16 pixels are replaced with the lower 3 bits of the original video signal (RGB) of “110”. In some cases, 12 pixels out of 16 adjacent pixels are selected. In the case where the lower 3 bits of the original video signal (RGB) are “111”, 14 pixels out of the adjacent 16 pixels are selected. Video data corresponding to data obtained by adding 1 to upper bit data When driven by a voltage, it can be 16 pixels to display an image corresponding on average to each dither level.

  The dithering set corresponding to each dithering level includes a series of dithering patterns. A series of dithering patterns in each dithering set includes the same number of dithering pixels, but the positions of the dithering pixels in each dithering pattern are different from each other. When a dithering level for a dithering block is determined, a series of dithering patterns corresponding to the determined dithering level are sequentially applied to successive frames of the dithering block. FIG. 5 shows that eight dithering patterns or four dithering patterns are sequentially applied from the (8n) th frame to the (8n + 7) th frame for each dithering level. In this way, display defects such as flicker can be reduced by changing the position of dithering pixels for each frame and displaying an image.

  The setting of each dithering pattern in FIG. 5 will be described in more detail with reference to FIGS. 6A and 6B. 6A and 6B are tables for explaining the setting of each dithering pattern in FIG. 5 by taking the second dithering pattern as an example. 6A and 6B show a case where each dithering block (that is, each second dithering pattern) includes pixels arranged in a 4 × 4 matrix shape.

  Referring to FIGS. 6A and 6B, the pixels included in each dithering block may be driven with the polarity reversed for each frame. 6A and 6B, +/− means that each pixel is driven with positive polarity / negative polarity. In the (8n) th to (8n + 7) th frames, which are continuous frames, it can be confirmed that each pixel is driven with its polarity reversed for each frame.

  Each dithering pattern may be set so that the number of positive dithering pixels included in each dithering block matches the number of negative dithering pixels. 6A and 6B, the number of dithering pixels driven with positive polarity, that is, the number of positive dithering pixels, and the dithering pixel driven with negative polarity, that is, negative dithering pixels are obtained. It can be confirmed that the number matches. In each dithering pattern applied from the (8n) th frame to the (8n + 7) th frame in FIGS. 6A and 6B, the number of positive dithering pixels and the number of negative dithering pixels are one each.

  Each dithering pattern may be set so that the sum of elements constituting the dithering polarity matrix becomes zero. Each element of the dithering polarity matrix corresponds to each pixel in the dithering block. Each element of the dithering polarity matrix indicates whether each pixel in the dithering block is a dithering target, and indicates the polarity of the dithering pixel that is the target of the dithering. In the dithering polarity matrix illustrated in FIGS. 6A and 6B, 0 means a pixel that is not a dithering target, +1 means a positive dithering pixel, and -1 means a negative dithering pixel. From each dithering polarity matrix shown in FIGS. 6A and 6B, it can be confirmed that each dithering pattern is set so that the sum of the elements constituting the dithering polarity matrix is zero.

  Further, in each dithering pattern, not only the sum of the elements constituting the dithering polarity matrix becomes 0, but also at least one of the total value of the sums of the row polarities and the sum of the column polarities becomes 0. May be set. The sum of the row polarities is the sum of the elements constituting each row of the dithering polarity matrix, and the sum of the column polarities is the sum of the elements constituting each column of the dithering polarity matrix.

  The dithering polarity matrix corresponding to the dithering pattern applied to the (8n) th frame in FIG. 6A will be described as an example. The sum of the row polarities of the first row is +1, and the row polarity of the second row is The sum is 0, the sum of the row polarities of the third row is -1, and the sum of the row polarities of the fourth row is zero. Therefore, the total sum (Sum (sum of row polarities)) of the row polarities of the first to fourth rows is zero. The sum of the column polarities of the first column is +1, the sum of the column polarities of the second column is 0, the sum of the column polarities of the third column is -1, and the sum of the column polarities of the fourth column Is 0. Accordingly, the total sum (Sum (sum of column polarities)) of the column polarities of the first to fourth columns is zero. As described above, each dithering pattern may be set so that at least one of the total value of the sum of the row polarities and the total value of the sum of the column polarities becomes zero. Although the description is omitted for the sake of convenience, the same description is applied to the (8n + 1) th frame to the (8n + 7) th frame in FIGS. 6A and 6B.

  Furthermore, the dithering pattern is not only the sum of the elements constituting the dithering polarity matrix becomes 0, and at least one of the sum of the sums of the row polarities and the sum of the column polarities becomes 0, but also the row polarity And the sum of the column polarities may be set to 0. For example, when the dithering polarity matrix (not shown) corresponding to the dithering pattern applied to the (8n + 1) th and (8n + 3) th frames in the fifth dithering pattern of FIG. It can be confirmed that the dithering pattern is set so that the sum of the column polarities is 0.

  With reference to FIG. 7A and FIG. 7B, the setting of a series of dithering patterns included in the dithering set will be described. 7A and 7B are tables for explaining a series of dithering pattern settings for each dithering level in FIG.

  A series of dithering patterns included in the dithering set may be set using a sum matrix (combined matrix) obtained by summing dithering polarity matrices of the series of dithering patterns. 7A and 7B illustrate the sum matrix for each dithering level.

  The series of dithering patterns includes at least one of a total sum of row polarities that is a sum of elements constituting each row of the sum matrix and a total sum of column polarity sums that are the sum of elements constituting each column of the sum matrix. One may be set to 0.

  Taking the second dithering pattern corresponding to the 1/8 dithering level described with reference to FIGS. 6A and 6B as an example, the sum of the row polarities of the first row of the sum matrix is zero, The sum of the row polarities of the two rows is 0, the sum of the row polarities of the third row is 0, and the sum of the row polarities of the fourth row is 0. Therefore, the total sum (Sum (sum of row polarities)) of the row polarities of the first to fourth rows is zero. The sum of the column polarities of the first column is 0, the sum of the column polarities of the second column is 0, the sum of the column polarities of the third column is 0, and the sum of the column polarities of the fourth column is 0. Accordingly, the total sum (Sum (sum of column polarities)) of the column polarities of the first to fourth columns is zero. As described above, the series of dithering patterns may be set so that at least one of the total value of the sums of the row polarities and the sum of the column polarities of the sum matrix is zero. The same description applies to the first dithering pattern corresponding to the 0/8 dithering level, and the third dithering pattern to the eighth dithering pattern corresponding to the 2/8 dithering level to the 7/8 dithering level, respectively. Is done.

  Furthermore, the series of dithering patterns may be set such that the sum of the row polarities of the sum matrix and the sum of the column polarities of the sum matrix are each zero. From FIG. 7A and FIG. 7B, in all sum matrices corresponding to the 0/8 dithering level to the 7/8 dither level, the sum of the row polarities of the sum matrix and the sum of the column polarities of the sum matrix are each 0. It can be confirmed that a series of dithering patterns are set as follows.

  With reference to FIG. 8, the setting process of each dithering pattern and the series of setting process of the dithering pattern in the driving method of the display device according to the embodiment of the present invention will be described. FIG. 8 is a flowchart for explaining a method of driving a display device according to an embodiment of the present invention.

  First, a process of setting each dithering pattern in the display device driving method according to the embodiment of the present invention will be described.

  First, a dithering polarity matrix for the test dithering pattern is obtained (S710).

  Next, it is determined whether the sum of the elements constituting the dithering polarity matrix of the test dithering pattern is 0 (S720).

  Next, if the sum of the elements constituting the dithering polarity matrix of the test dithering pattern is 0, the test dithering pattern is set as the dithering pattern (S730).

  Here, not only the sum of the elements constituting the dithering polarity matrix of the test dithering pattern becomes 0, but in the dithering polarity matrix of the test dithering pattern, the total sum of the row polarities and the column polarity A test dithering pattern in which at least one of the total sums is 0 may be set as the dithering pattern.

  Furthermore, the sum of the elements constituting the dithering polarity matrix of the test dithering pattern becomes 0, and at least one of the total value of the sum of the row polarities and the sum of the column polarities becomes 0, In the dithering polarity matrix of the test dithering pattern, a test dithering pattern in which the sum of the row polarities and the sum of the column polarities is 0 may be set as the dithering pattern.

  On the other hand, if the sum of elements constituting the dithering polarity matrix of the test dithering pattern is not 0, the test dithering pattern is adjusted (S725).

  Next, a series of dithering pattern setting processes in the display device driving method according to the embodiment of the present invention will be described.

  In setting a series of dithering patterns, select a plurality of dithering patterns in which the number of positive dithering pixels and the number of negative dithering pixels included in each dithering block match, and select the plurality Set the dithering pattern to a series of dithering patterns.

  Specifically, first, the processes (S710 to S730) are repeated a number of times to set a number of dithering patterns for each dithering level.

  Next, among a plurality of dithering patterns set for each dithering level, a plurality of dithering patterns are selected (S740).

  Next, a sum matrix that is the sum of the dither polarity matrices of the selected dither patterns is obtained (S750).

  Next, it is determined whether the sum of the elements constituting the sum matrix is 0 (S760).

  Next, if the sum of the elements constituting the sum matrix is 0, the plurality of selected dithering patterns are set to a series of dithering patterns corresponding to each dithering level (S760).

  Here, not only the sum of the elements constituting the sum matrix becomes 0, but also a plurality in which at least one of the sum of the sums of the row polarities of the sum matrix and the sum of the column polarities of the sum matrix is 0 May be set to a series of dithering patterns corresponding to each dithering level.

  Further, the sum of elements constituting the sum matrix becomes 0, and not only at least one of the sum of the sums of the row polarities of the sum matrix and the sum of the column polarities of the sum matrix becomes 0, but the sum matrix A plurality of dithering patterns in which the sum of the row polarities and the sum of the column polarities of the sum matrix are each 0 may be set as a series of dithering patterns corresponding to the dithering levels.

  In this way, a series of dithering patterns is set using a sum matrix obtained by summing dithering polarity matrices of each of a plurality of selected dithering patterns.

  According to the display device and the driving method thereof according to the embodiment of the present invention, the dithering pattern is set in consideration of the polarity of the dithering pixel in the process of setting the dithering pattern. That is, a dithering polarity matrix is used for each dithering pattern, a sum matrix of a series of dithering patterns corresponding to each dithering level is used, and the dithering pixel polarity at the time of setting the dithering pattern is considered. . The display quality of the display device can be improved by setting each dithering pattern so that the number of positive dithering pixels included in each dithering block matches the number of negative dithering pixels.

  As described above, the embodiments of the present invention have been described with reference to the drawings. However, those who have ordinary knowledge in the technical field to which the present invention pertains are within the scope of the present invention without changing the technical idea and essential features. It can be understood that the present invention can be implemented in a specific form. Therefore, it should be understood that the above embodiment is illustrative in all aspects and not restrictive.

Claims (10)

Including a plurality of dithering blocks for displaying video corresponding to the dithering video signal, each dithering block including a plurality of pixels that are driven with polarity reversed for each frame; and
A video signal control unit that generates the dithering video signal using a dithering pattern that determines a plurality of dithering pixels to be dithered among a plurality of pixels in each dithering block;
Including
The display device, wherein the number of positive dithering pixels included in each dithering block is equal to the number of negative dithering pixels. Each element of the dithering polarity matrix corresponds to each pixel in the dithering block, and indicates whether each pixel is a dithering target and the polarity of the dithering pixel that is the dithering target;
The display device according to claim 1, wherein the dithering pattern is set so that a sum of elements constituting the dithering polarity matrix is zero. The sum of each row polarity is a sum of elements constituting each row of the dithering polarity matrix, and the sum of each column polarity is a sum of elements constituting each column of the dithering polarity matrix;
The display device according to claim 2, wherein the dithering pattern is set so that at least one of a total value of the sum of the row polarities and a total value of the sum of the column polarities is zero.   4. The display device according to claim 3, wherein the dithering pattern is set such that the sum of the row polarities and the sum of the column polarities are 0, respectively. The number of the dithering pixels in each dithering block is determined by the dithering level,
The display device according to claim 1, wherein a dithering set including a series of dithering patterns corresponding to the dithering level is set. Each element of the dithering polarity matrix corresponds to each pixel in the dithering block, and indicates whether each pixel is a dithering target and the polarity of the dithering pixel that is the dithering target;
6. The display according to claim 5, wherein the series of dithering patterns included in the dithering set is set using a sum matrix obtained by summing up the dithering polarity matrices of the series of dithering patterns. apparatus.   The series of dithering patterns includes a total sum of row polarities that is a sum of original elements constituting each row of the sum matrix, and a sum of column polarities that is a sum of elements that constitute each column of the sum matrix. The display device according to claim 6, wherein at least one of the total values is set to zero.   8. The series of dithering patterns is set such that a sum of the row polarities of the sum matrix and a sum of the column polarities of the sum matrix are each 0. Display device. A data driver that receives the dithering video signal and outputs a video data voltage;
The video signal control unit receives an original video signal having a first bit number, the bit number of the video data voltage is a second bit number smaller than the first bit number, and the dithering level is 6. The display device according to claim 5, wherein the display device is determined by the LSB of the original video signal.   The display device of claim 9, wherein the series of dithering patterns set for the determined dithering level is sequentially applied to successive frames.