JP2010052185A - Overvoltage protection apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an overvoltage protection apparatus which can protect a logic circuit, without having to use a transistor having a large allowable current, when an FFC which connects the head driver of an inkjet recording device electrically is applied wrongly and an overvoltage is applied. <P>SOLUTION: An overvoltage protection apparatus 50 includes a logic circuit 51, which generates a control signal for controlling a section to be controlled; a control signal output terminal 54 which is provided on the output side 51b of the logic circuit 51 for separably connecting the output side 51b of the logic circuit 51 with the section to be controlled and outputs a control signal generated from the logic circuit 51 to the section to be controlled; and an interruption circuit 52, which is provided between the output side 51b of the logic circuit 51.The control signal output terminal 54 for interrupting the current path between the output side 51b of the logic circuit 51 and the control signal output terminal 54, wherein the logic circuit 51 is protected, by interrupting the interruption circuit 52, when a voltage higher than the normal voltage on the output side 51b of the logic circuit 51 is applied to the control signal output terminal 54. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an overvoltage protection device for an ink jet recording apparatus, and in particular, in an ink jet recording apparatus having a plurality of heads, prevents destruction of a logic circuit when an FFC that electrically connects a head driver is erroneously inserted. The present invention relates to an overvoltage protection device for an ink jet recording apparatus capable of protecting a circuit.

  As various image forming apparatuses such as printers, facsimiles, copying machines, plotters, printer / fax / copier multifunction machines, etc., recording heads (printing heads) constituted by droplet discharging heads that discharge recording liquid (for example, ink) droplets are used. ) Is mounted on a carriage, and the carriage is a recording medium (hereinafter referred to as “paper”, but the material is not limited to paper, and is also referred to as recording medium, recording paper, transfer material, etc.). In addition to serial scanning in a direction orthogonal to the conveyance direction, the recording medium is intermittently conveyed according to the recording width, and an image is formed on the recording medium by repeating conveyance and recording (recording, printing, There is an ink jet recording apparatus that uses the same meaning as printing.

  FIG. 11 shows how the recording head is mounted on the carriage in such an ink jet recording apparatus. In FIG. 11, reference numeral 15 denotes a head unit mounted on the carriage 4, and a recording unit provided with a storage unit (not shown) that stores ink supplied from an ink supply source and an ejection hole that ejects ink stored in the storage unit. And a head 11.

  Reference numeral 122 denotes a printed wiring board (relay board) that controls ink ejection by the head unit 15, and 121 denotes a flexible flat cable (Flexible Flat Cable: FFC) that connects the printed wiring board (relay board) 122 and the recording head 11. A printed wiring board (relay board) 122 and a flexible flat cable 121 are connected via a connector 123.

  Reference numeral 107 denotes a carriage driving belt connected to the carriage 4, and 109 denotes a guide rail of the carriage 4. The carriage 4 can move in the S direction in the figure along the guide rail 109 in accordance with the driving of a motor (not shown), and can perform recording on the recording surface.

  FIG. 12 is a diagram illustrating a state in which the recording head and the relay substrate are connected in the carriage in the ink jet recording apparatus. 12A shows a state where the cable is normally inserted into the connector when the nozzle row and the relay board are connected, and FIG. 12B shows the cable when the nozzle row and the relay board are connected. Shows a state of being erroneously inserted into the connector.

  A relay substrate 122 is attached in the carriage 4, and the relay substrate 122 is a substrate for mainly giving a signal to a drive IC for driving the recording head 11, and other sheets disposed in the carriage 4. It also serves to provide sensor signals such as detection and ink detection to the main control board. That is, it is an input / output relay board that transmits a signal from a main control board installed in the recording apparatus main body to the recording head 11. Usually, the main control board and the relay board 122 are connected by FFC, and a signal is supplied to each recording head.

  Further, the connection from the relay substrate 122 to the flexible substrate 120 on which a drive IC or the like for driving the recording head 11 is mounted is performed using the FFC 121. That is, as shown in FIG. 12A, the recording head 11 is connected to the relay substrate 122 via the FFC 121 and the connector 123. The FFC 121 connected to the flexible board 120 is bent once or twice in the middle and connected to the relay board 122.

  When the direction perpendicular to the paper surface in FIG. 12A is the depth direction, the relay substrate 122 includes a total of four connectors 123 for flexible flat cables, for example, one for each color along the depth direction. Be placed. The number of pins of the FFC connector is determined by the number of signals to the drive IC that drives the recording head 11, but is usually about 20 to 40 pins.

  Here, in an inkjet image forming apparatus using a plurality of heads, when an FFC is used for wiring from a head to a circuit board that controls the head, when connecting the FFC to a connector arranged on the circuit board, Incorrect insertion such as oblique insertion may occur.

  FIG. 12B illustrates a state in which the FFC is erroneously inserted into the connector, which is called oblique insertion. The FFC is not inserted vertically with respect to the connector, but is inserted with an angle. If there is such an oblique insertion, adjacent terminals in the FFC cable connector may be short-circuited, and a high voltage (overvoltage) from the power supply system wiring is applied to the control system wiring, May cause damage. In particular, in the FFC wiring of the inkjet head, signals from a low voltage logic circuit unit and a high voltage and low output impedance head drive circuit unit are mixed. Therefore, the logic circuit unit and the head drive circuit unit may be short-circuited due to erroneous FFC connector insertion, and the logic circuit unit may be destroyed. Therefore, it is necessary to provide some overvoltage protection device.

  There are several known examples of such overvoltage protection devices. For example, in the cited document 1, when an overvoltage exists between the first and second input terminals, the first and second output terminals, and the second input terminal and the second output terminal, In order to prevent the overvoltage, the first field effect transistor that increases the voltage drop of the second line between the second input terminal and the second input terminal, the first input terminal, and the first input terminal In the third line provided between the first line and the second line that connect the output terminal, the source terminal and the drain terminal are connected to the third line, and the first input terminal and the second line An example of an overvoltage protection circuit including a second field effect transistor that conducts an overvoltage between two input terminals is disclosed.

Further, in the cited document 2, a Zener diode that allows current to flow with an overvoltage in a current path including a DC-DC converter connected to a DC power source, and a current that has been overvoltaged by turning on the current that has passed through the Zener diode as a trigger. An NPN transistor that short-circuits the path, a fuse that is blown when the current path is short-circuited and cuts off the short-circuit path, and a current path that is over-voltaged by this fuse being connected to the trigger terminal and turned off when the fuse is blown An overvoltage protection circuit having a PNP transistor for blocking is disclosed.
Japanese Patent No. 3424817 JP 2000-201429 A

  However, the overvoltage protection device having such an overvoltage protection circuit has the following problems.

  In the conventional overvoltage protection devices disclosed in the cited references 1 and 2, in order not to transmit the overvoltage applied to the input side to the output side, the input side and the output side when the overvoltage is applied to the input side. And a short circuit between the high-voltage side and the low-voltage side on the input side, and a switch element is provided between the high-voltage side and the low-voltage side on the input side while providing a cutoff circuit between the input side and the output side There is a problem in that the circuit configuration becomes complicated because a current path including the current path must be provided.

  Further, in the conventional overvoltage protection devices disclosed in the cited references 1 and 2, when a high voltage and low impedance circuit is connected, a large current may flow into the field effect transistor connected in parallel with the signal wiring. Therefore, it is necessary to use a transistor having a large allowable current, and there is a problem that the circuit becomes large and the cost of parts increases.

  Furthermore, in the conventional overvoltage protection device disclosed in the cited documents 1 and 2, there is a problem that it is impossible to specify the presence or absence of overvoltage and the location where the overvoltage occurs.

  The present invention has been made in view of the above points, and does not use a transistor having a large allowable current when an FFC that electrically connects a head driver of an inkjet recording apparatus is erroneously inserted and an overvoltage is applied. It is an object of the present invention to provide an overvoltage protection device that can protect a logic circuit and can detect in which wiring part of an FFC an abnormality has occurred and an overvoltage has occurred.

  According to a first aspect of the present invention, there is provided an overvoltage protection device capable of separating a logic circuit that generates a control signal for controlling a controlled unit and an output side of the logic circuit, and separating the output side of the logic circuit from the processed unit. A control signal output terminal provided for connection and for outputting the control signal generated by the logic circuit to the controlled part; and provided between the output side of the logic circuit and the control signal output terminal. A cutoff circuit that cuts off a current path between the output side of the logic circuit and the control signal output terminal, and the control signal output terminal has a voltage higher than that of the output side of the logic circuit at a normal time. When a high voltage is applied, the logic circuit is protected by blocking the blocking circuit.

  According to a second aspect of the present invention, in the overvoltage protection device according to the first aspect of the present invention, the reference is connected to the control signal output terminal and is based on the voltage of the control signal output terminal and the voltage on the output side of the logic circuit at the normal time. A comparison circuit for comparing the voltage is provided, and when a voltage higher than the reference voltage is applied to the control signal output terminal, a detection signal is output from the output terminal of the comparison circuit.

  According to a third aspect of the invention, in the overvoltage protection device according to the first or second aspect of the invention, the cutoff circuit is a diode-connected field effect transistor.

  According to a fourth aspect of the present invention, in the overvoltage protection device according to the first or second aspect of the invention, the interruption circuit is a diode.

  According to the present invention, when the FFC that electrically connects the head driver of the ink jet recording apparatus is erroneously inserted and an overvoltage is applied, the logic circuit can be protected without using a transistor having a large allowable current, In addition, it is possible to detect in which wiring portion of the FFC an abnormality has occurred and an overvoltage has occurred.

  Next, the best mode for carrying out the present invention will be described with reference to the drawings.

(First embodiment)
An ink jet recording apparatus according to a first embodiment of the present invention will be described with reference to FIGS.

  First, the system configuration of the ink jet recording apparatus according to the present embodiment will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a diagram for explaining the overvoltage protection device according to the present embodiment, and is an explanatory side view for explaining the overall structure of the mechanism portion of the ink jet recording apparatus including the overvoltage protection device. FIG. 2 is a diagram for explaining the overvoltage protection device according to the present embodiment, and is a plan explanatory diagram for explaining the overall structure of the mechanism portion of the ink jet recording apparatus including the overvoltage protection device.

  In this image forming apparatus, a carriage 4 is fixedly held by a guide rod 2 and a stay 3 which are guide members horizontally mounted on the left and right side plates 1A and 1B constituting the frame 1.

  The carriage 4 includes, for example, four droplet ejection heads 11k, 11c, 11m, and 11y that eject ink droplets of each color of black (Bk), cyan (C), magenta (M), and yellow (Y). The recording head 11 is mounted with a nozzle array composed of a plurality of ink ejection openings (nozzles) arranged in a direction perpendicular to the recording medium conveyance direction in FIG. 2 and the ink ejection direction facing downward. Although an independent droplet discharge head is used here, a configuration in which one or a plurality of heads having a plurality of nozzle rows that discharge droplets of recording liquid of each color can be used. Further, the number of colors and the arrangement order are not limited to this.

  As the ink jet head constituting the recording head 11, a head provided with a piezoelectric actuator such as a piezoelectric element as pressure generating means (actuator) for generating a pressure for discharging a droplet is used.

  A driver IC is mounted on the recording head 11 and connected to a control unit (not shown) via a harness (flexible print cable: FPC cable) 12.

  Further, the carriage 4 is equipped with sub tanks for each color (not shown) for supplying each color ink to the recording head 11. Each color sub-tank is supplementarily supplied with ink of each color from an ink cartridge of each color (not shown).

  On the other hand, as shown in FIG. 1, the paper 22 is separated from the paper stacking unit 21 one by one as a paper feeding unit for feeding the paper 22 stacked on the paper stacking unit (pressure plate) 21 of the paper feed tray 20. Opposed to the half-moon roller (sheet feeding roller) 23 and the sheet feeding roller 23 to be fed, a separation pad 24 made of a material having a large friction coefficient is provided, and this separation pad 24 is urged toward the sheet feeding roller 23 side.

  In order to feed the paper 22 fed from the paper feeding unit to the lower side of the recording head 11, a guide member 25 for guiding the paper 22, a counter roller 26, a conveyance guide member 27, and a tip pressure roller. And a holding belt 28 as a conveying means for electrostatically attracting the fed paper 22 and conveying it at a position facing the recording head 11.

  Further, a paper discharge roller 42 and a paper discharge roller 43 are provided as a paper discharge unit for discharging the paper 22 recorded by the recording head 11 to the paper discharge tray 40.

  Next, an outline of the control unit of the ink jet recording apparatus will be described with reference to FIGS.

  FIG. 3 is a diagram for explaining the overvoltage protection device according to the present embodiment, and is a block diagram for explaining the outline of the control unit of the ink jet recording apparatus including the overvoltage protection device. FIG. 4 is a diagram for explaining the overvoltage protection device according to the present embodiment, and is a block diagram for explaining an example of a head drive control unit and a head driver in the control unit of the ink jet recording apparatus including the overvoltage protection device. is there. FIG. 5 is a diagram for explaining the overvoltage protection device according to the present embodiment, and is an explanatory diagram for explaining an example of an analog switch of the head driver of the ink jet recording apparatus including the overvoltage protection device.

  As shown in FIG. 3, the control unit 200 includes a CPU 201 that controls the entire apparatus, a program executed by the CPU 201, a ROM 202 that stores other fixed data, a RAM 203 that temporarily stores image data and the like, A rewritable non-volatile memory 204 for holding data even while the power is off, image processing for performing various signal processing and rearrangement on image data, and other input / output signals for controlling the entire apparatus And an ASIC 205 for processing.

  The control unit 200 includes an I / F 206 for transmitting and receiving data and signals to and from the host side, a head drive control unit 207 including a data transfer unit for driving and controlling the recording head 11, and a carriage 4 side. A head driver (driver IC) 208 which is a head driving device for driving the provided recording head 11, a transport motor driving unit 211 for driving the transport motor 36, detection pulses from the linear encoder 74 and the wheel encoder 236. And an I / O 213 for inputting detection signals from the temperature sensor 215 for detecting the environmental temperature and detection signals from various other sensors. The control unit 200 is connected to an operation panel 214 for inputting and displaying information necessary for the apparatus.

  Here, the control unit 200 transmits print data from the host side such as an information processing device such as a personal computer, an image reading device such as an image scanner, an imaging device such as a digital camera, etc. via an I / F 206 via a cable or a network. Receive.

  Then, the CPU 201 of the control unit 200 reads and analyzes the print data in the reception buffer included in the I / F 206, performs necessary image processing, data rearrangement processing, and the like in the ASIC 205, and this image data is head-driven. The data is transferred from the control unit 207 to the head driver 208. The dot pattern data for image output may be generated by storing font data in the ROM 202, for example, or the image data is developed into bitmap data by a host-side printer driver and transferred to this apparatus. You may do it.

  The head drive control unit 207 transfers the above-described image data as serial data, and outputs a transfer clock, a latch signal, a control signal, and the like necessary for transferring the image data and confirming the transfer to the head driver 208. Includes a drive waveform generation unit including a D / A converter and an amplifier that D / A converts drive pulse pattern data stored in the ROM 202 and read out by the CPU 201. One drive pulse or a plurality of drive pulses A drive waveform composed of (drive signal) is output to the head driver 208.

  The head driver 208 selectively selects a driving pulse constituting a driving waveform supplied from the head driving control 207 based on image data corresponding to one line of the recording head 11 input serially, and generates pressure of the recording head 11. The recording head 11 is driven by applying to the actuator (piezoelectric element).

  The conveyance motor drive unit 211 calculates a control value based on a target value given from the CPU 201 side and a speed detection value obtained by sampling a detection pulse from the wheel encoder 236, and carries the conveyance motor 36 via an internal motor driver. Drive.

  Next, an example of the configuration of the head drive control unit 207 and the head driver 208 which is the head drive device according to the present invention will be described with reference to FIG.

  As described above, the head drive control unit 207 generates a drive waveform (common drive waveform) composed of a plurality of drive pulses (drive signals) within one ejection cycle, and outputs an image. A data transfer unit 302 that outputs data (print data), a transfer clock (not shown), a latch signal, and a droplet control signal. A droplet control signal corresponding to a large droplet mask signal to a fine driving mask signal, which will be described later, is a signal that instructs each droplet to open and close an analog switch 315 that is a switch means described later of the head driver 208, and discharge period of the common driving waveform. The state transitions to the H level with the waveform to be selected according to the state, and the state transitions to the L level when not selected.

  The head driver 208 includes a shift register 311 for inputting a transfer clock (shift clock) and serial image data from the data transfer unit 302, a latch circuit 312 for latching each register value of the shift register 311 with a latch signal, and an image. A decoder 313 that decodes data and control signals and outputs a result, a level shifter 314 that converts the logic level voltage signal of the decoder 313 to a level at which the analog switch 315 can operate, and a decoder 313 that is provided via the level shifter 314 And an analog switch 315 that is turned on / off (opened / closed) by the output of

  The analog switch 315 is connected to the piezoelectric element 318 and receives the common drive waveform from the drive waveform generation circuit 301. Accordingly, when the analog switch 315 is turned on in accordance with the result of decoding the serially transferred image data and control signal by the decoder 313, a required drive signal constituting the common drive waveform passes (is selected). Applied to the piezoelectric element 318.

  The analog switch 315 is composed of a CMOS (Complementary Metal Oxide Semiconductor) analog switch in the same manner as the analog switch of the conventional configuration described above. That is, as shown in FIG. 5, a pair of P-channel transistors 321 and N-channel transistors 322 are provided, and the gates of the transistors 321 and 322 are driven by inverter circuits 323 and 324, and the inverters 323 and 324 are level shifters 314. It is driven by the signal. In this setting, the output A of the level shifter 314 is L (low) level, the output B is H (high) level, and the analog switch 315 is turned on. Cost reduction can be achieved by using a CMOS analog switch.

  Further, in the present embodiment, the data transfer unit 302 includes a logic circuit 51 and a cutoff circuit 52. The data transfer unit 302 and the head driver 208 are connected via the connector 123 and the FFC 121. A part of the connector 123 is a control signal output terminal 54. On the other hand, the drive waveform generation circuit 301 and the head driver 208 are connected via a connector 123 and an FFC 121. A part of the connector 123 is an output terminal 304 of the drive waveform generation circuit 301.

  4, the overvoltage protection device 50 includes a logic circuit 51, a cutoff circuit 52, and a control signal output terminal 54, and is indicated as 50 surrounded by a dotted line. Moreover, as shown in FIG. 4, the several overvoltage protection apparatus 50 can also be provided in parallel.

  Note that a current path in which an overvoltage is applied to the overvoltage protection device 50 from the power supply system circuit of the drive waveform generation circuit 301 through the control signal output terminal 54 due to contact between adjacent terminals due to erroneous insertion in the connector 123 is illustrated. Indicated by the bold line 4.

  Next, a circuit of the overvoltage protection circuit according to the present embodiment will be described with reference to FIG.

  FIG. 6 is a circuit diagram of the overvoltage protection device according to the present embodiment.

  The overvoltage protection device 50 according to the present embodiment includes a logic circuit 51, a cutoff circuit (field effect transistor) 52, a resistor 53, and a control signal output terminal 54.

  As shown in FIG. 4, the logic circuit 51 generates a control signal for controlling the head driver 208, which is a controlled unit, via the control signal output terminal 54 and the FFC 121. As shown in FIG. 6, the logic circuit 51 has an input terminal (input side) 51a and an output terminal (output side) 51b. When a digital signal is input to the input terminal 51a, the output terminal (output side) 51b is logically output with the same value as the value applied to the input terminal (input side) 51a, or the input terminal (Input side) The result of logical operation such as AND, OR, NOT, XOR or the like is output to the value added to 51a. This circuit is normally composed of a TTL (Transistor Transistor Logic) circuit, a CMOS circuit, etc., operates at a low voltage of 5 V or less, and the input and output voltages are usually 5 V or less.

  The cutoff circuit 52 is a field effect transistor and has a drain terminal 52a, a gate terminal 52b, and a source terminal 52c. An Nch junction field effect transistor is used as the field effect transistor. The field effect transistor is diode-connected. That is, the gate terminal 52b and the source terminal 52c are connected.

  The resistor 53 has a terminal 53a and a terminal 53b. During normal operation when no overvoltage is applied to the control signal output terminal 54, the control signal output terminal 54 is connected to a circuit such as the level shifter 314 in FIG. The potential of the source terminal 52c becomes unstable, and the operation of the field effect transistor becomes unstable. In that case, the resistor 53 can stabilize the potentials of the gate terminal 52b and the source terminal 52c of the field effect transistor.

  The output terminal (output side) 51 b of the logic circuit 51 is connected to the drain terminal 52 a of the field effect transistor 52. The gate terminal 52b of the field effect transistor 52 is connected to the source terminal 52c, the terminal 53a of the resistor 53, and the control signal output terminal 54. A terminal 53b of the resistor 53 is connected to the ground.

  Normally, a voltage higher than the operating voltage of the logic circuit 51 (the voltage of the output terminal (output side) 51b of the logic circuit 51) is not applied to the control signal output terminal 54. Therefore, the drain terminal 52a and the source terminal 52c of the field effect transistor 52 are turned on, and the voltage of the control signal output terminal 54 is equal to the voltage of the output terminal (output side) 51b of the logic circuit 51. In addition, since the resistance between the drain terminal 52 a and the source terminal 52 c of the field effect transistor 52 is smaller than that of the resistor 53, there is almost no current flowing through the resistor 53 to the ground.

  However, when an abnormality occurs, that is, when an overvoltage equal to or higher than the operating voltage of the logic circuit 51 (voltage of the output terminal (output side) 51 b of the logic circuit 51) is applied to the control signal output terminal 54, the drain terminal 52 a of the field effect transistor 52. And the source terminal 52c are turned off, so that the overvoltage applied to the control signal output terminal 54 is not applied to the output terminal (output side) 51b of the logic circuit 51.

  As described above, the field effect transistor 52 is a diode having a forward direction when a voltage higher than the source terminal 52c is applied to the drain terminal 52a and a reverse direction when a voltage higher than the drain terminal 52a is applied to the source terminal 52c. Function. By providing such a diode-connected field effect transistor between the control signal output terminal 54 and the output terminal (output side) 51 b of the logic circuit 51, the output terminal (output) of the logic circuit 51 is connected to the control signal output terminal 54. Side) When a voltage higher than 51b is applied, the logic circuit 51 can be prevented from being destroyed.

  As described above, a diode-connected field-effect transistor is provided between the logic circuit and the head driver (controlled unit), and a connector serving as a control signal output terminal from the logic circuit to the head driver (controlled unit) is connected to the ground. By providing the resistor, even when the connector is erroneously inserted and an overvoltage is applied to the logic circuit, the logic circuit can be prevented from being destroyed, and the overvoltage protection circuit can be reduced in size and cost. .

(Modification of the first embodiment)
Next, a modification of the first embodiment will be described with reference to FIGS.

  FIG. 7 is a diagram for explaining an overvoltage protection device according to this modification, and is a block diagram for explaining an example of a head drive control unit and a head driver in a control unit of an ink jet recording apparatus including the overvoltage protection device. . FIG. 8 is a circuit diagram of an overvoltage protection device according to this modification. However, in the following text, the same reference numerals are given to the parts described above, and the description may be omitted (the same applies to the following modified examples and embodiments).

  The overvoltage protection device in this modification is different from the control circuit in the first embodiment in that a detection signal is output when an overvoltage is applied to the control signal output terminal. That is, in the first embodiment, unlike having no means for detecting when an overvoltage is applied to the control signal output terminal, the overvoltage protection device in this modification is connected to the control signal output terminal, When a voltage higher than the reference voltage is applied to the control signal output terminal, the comparator has a comparison circuit that compares the voltage of the control signal output terminal with a reference voltage based on the normal voltage on the output side of the logic circuit. A detection signal is output from the output terminal of the comparison circuit.

  Referring to FIG. 7, in this modification, the data transfer unit 302 includes a logic circuit 61 and a cutoff circuit 62. The data transfer unit 302 and the head driver 208 are connected via the connector 123 and the FFC 121. A part of the connector 123 is a control signal output terminal 64. On the other hand, the drive waveform generation circuit 301 and the head driver 208 are connected via a connector 123 and an FFC 121. A part of the connector 123 is an output terminal 304 of the drive waveform generation circuit 301.

  7, the overvoltage protection device 60 includes a logic circuit 61, a cutoff circuit 62, a control signal output terminal 64, and a comparison circuit 66, and is indicated as 60 surrounded by a dotted line. As shown in FIG. 7, a plurality of overvoltage protection devices 60 can be provided in parallel.

  A current path through which an overvoltage is applied from the power supply system circuit of the drive waveform generation circuit 301 to the control signal output terminal 64 due to contact between adjacent terminals due to erroneous insertion in the connector 123 is indicated by a thick line in FIG.

  Next, a circuit of an overvoltage protection circuit according to this modification will be described with reference to FIG.

  The overvoltage protection device 60 according to this modification includes a logic circuit 61, a cutoff circuit (field effect transistor) 62, a resistor 63, a control signal output terminal 64, a resistor 65, a comparator (comparator circuit) 66, a reference voltage generator 67, an overvoltage. A detection signal output terminal 68 is provided.

  As shown in FIG. 7, the logic circuit 61 generates a control signal for controlling the head driver 208, which is a controlled unit, via the control signal output terminal 64 and the FFC 121. As shown in FIG. 8, the logic circuit 61 has an input terminal (input side) 61a and an output terminal (output side) 61b. When a digital signal is input to the input terminal (input side) 61a, the output terminal (output side) 61b is logically output with the same value as the value added to the input terminal (input side) 61a. Alternatively, a result obtained by performing a logical operation such as AND, OR, NOT, or XOR on the value applied to the input terminal (input side) 61a is output. This circuit is normally composed of a TTL circuit, a CMOS circuit, etc., operates at a low voltage of 5 V or less, and the input and output voltages are usually 5 V or less.

  The cutoff circuit 62 is a field effect transistor and has a drain terminal 62a, a gate terminal 62b, and a source terminal 62c. An Nch junction field effect transistor is used as the field effect transistor. The field effect transistor is diode-connected. That is, the gate terminal 62b and the source terminal 62c are connected.

  The resistor 63 has a terminal 63a and a terminal 63b. The resistor 65 has a terminal 65a and a terminal 65b. During normal operation in which no overvoltage is applied to the control signal output terminal 64, the control signal output terminal 64 is connected to a circuit such as the level shifter 314 in FIG. 7, so that it is in a high impedance state and the gate terminal 62b of the field effect transistor. The potential of the source terminal 62c becomes unstable, and the operation of the field effect transistor becomes unstable. In that case, the potential of the gate terminal 52b and the source terminal 52c of the field effect transistor can be stabilized by the resistor 63 and the resistor 65. When an overvoltage is applied to the control signal output terminal 64, the voltage divided by the resistors 63 and 65 is applied to the positive input terminal of the comparator 66. Thereby, an overvoltage detection signal can be detected without using a comparator having a large allowable input voltage.

  The comparator 66 compares the voltage at the control signal output terminal 64 with the reference voltage generated by the reference voltage generator 67 and outputs the result from the overvoltage detection signal output terminal 68.

  The output terminal (output side) 61 b of the logic circuit 61 is connected to the drain terminal 62 a of the field effect transistor 62. The gate terminal 62b of the field effect transistor 62 is connected to the source terminal 62c, the terminal 63a of the resistor 63, and the control signal output terminal 64. The terminal 63b of the resistor 63 is connected to the terminal 65a of the resistor 65, and the terminal 65b of the resistor 65 is connected to the ground. The positive input terminal of the comparator 66 is connected to the terminal 63 b of the resistor 63 and the terminal 65 a of the resistor 65. The negative input terminal of the comparator 66 is connected to the positive terminal of the reference voltage generator 67. The negative terminal of the reference voltage generator 67 is connected to the ground. The reference voltage generated by the reference voltage generator 67 is a voltage determined in advance based on the voltage at the normal output terminal (output side) 61 b of the logic circuit 61.

  Normally, a voltage equal to or higher than the operating voltage of the logic circuit 61 (the voltage of the output terminal (output side) 61b of the logic circuit 61) is not applied to the control signal output terminal 64. Therefore, the drain terminal 62a and the source terminal 62c of the field effect transistor 62 are turned on, and the voltage of the control signal output terminal 64 is equal to the voltage of the output terminal (output side) 61b of the logic circuit 61. Further, since the resistance between the drain terminal 62a and the source terminal 62c of the field effect transistor 62 is smaller than the sum of the resistances 63 and 65, there is almost no current flowing through the resistances 63 and 65 to the ground.

  Further, since there is almost no current flowing through the resistor 63, the voltage applied to the positive input terminal of the comparator 66 can be made substantially equal to the voltage of the control signal output terminal 64, for example, by making the resistor 63 smaller than the resistor 65. it can. The reference voltage of the reference voltage generator 67 applied to the negative input terminal of the comparator 66 is the positive input terminal of the comparator 66 when a voltage is applied from the output terminal (output side) 61b of the logic circuit 61, for example. In general, the voltage applied to the positive input terminal of the comparator 66 is equal to the voltage applied to the positive input terminal of the comparator 66 by making the voltage 20% larger than the voltage applied to the voltage (substantially equal to the voltage of the output terminal (output side) 61b of the logic circuit 61). Since the voltage is smaller than the voltage applied to the negative input terminal 66, no detection signal is output from the overvoltage detection signal output terminal 68 connected to the output terminal of the comparator 66.

  However, when an abnormality occurs, that is, when an overvoltage equal to or higher than the operating voltage of the logic circuit 61 (the voltage of the output terminal (output side) 61b of the logic circuit 61) is applied to the control signal output terminal 64, the drain terminal 62a of the field effect transistor 62. And the source terminal 62c are turned off, so that the overvoltage applied to the control signal output terminal 64 is not applied to the output terminal (output side) 61b of the logic circuit 61.

  Further, current flows through the resistors 63 and 65. For example, by making the resistor 63 smaller than the resistor 65, the voltage applied to the positive input terminal of the comparator 66 can be made substantially equal to the voltage of the control signal output terminal 64. it can. Here, when the voltage applied to the control signal output terminal 64 becomes 20% or more larger than the voltage equal to the voltage of the output terminal (output side) 61b of the logic circuit 61 in the normal state, the magnitude relationship with the reference voltage described above is increased. Since the voltage applied to the positive input terminal of the comparator 66 is greater than the voltage applied to the negative input terminal of the comparator 66, the detection signal is output from the overvoltage detection signal output terminal 68 connected to the output terminal of the comparator 66. Is output.

  Similarly to the first embodiment, the field effect transistor 62 applies a higher voltage to the drain terminal 62a than the source terminal 62c, and applies a higher voltage to the source terminal 62c than the drain terminal 62a. It functions as a diode that reverses the case. By providing such a diode-connected field effect transistor between the control signal output terminal 64 and the output terminal (output side) 61b of the logic circuit 61, the output terminal (output) of the logic circuit 61 is connected to the control signal output terminal 64. Side) When a voltage higher than 61b is applied, the logic circuit 61 can be prevented from being destroyed.

(Second Embodiment)
Next, an overvoltage protection device according to a second embodiment will be described with reference to FIG.

  FIG. 9 is a circuit diagram of the overvoltage protection device according to the present embodiment.

  The overvoltage protection device according to the present embodiment is different from the overvoltage protection device according to the first embodiment in that a diode is used for the cutoff circuit. In other words, in the first embodiment, the cutoff circuit is a diode-connected field effect transistor, and in this embodiment, the cutoff circuit is a diode.

  The configurations of the head drive control unit and the head driver and the configuration of the overvoltage protection device therein are the same as those in the first embodiment, and are the same as those shown in FIG. However, since the overvoltage protection device 70 according to the present embodiment includes the logic circuit 71, the cutoff circuit (diode) 72, the resistor 73, and the control signal output terminal 74, the overvoltage protection device 50, the logic circuit 51, and the cutoff circuit in FIG. Reference numerals of the circuit 52 and the control signal output terminal 54 are the reference numerals in parentheses, and are the overvoltage protection device 70, the logic circuit 71, the cutoff circuit 72, and the control signal output terminal 74.

  As shown in FIG. 4, the logic circuit 71 generates a control signal for controlling the head driver 208, which is a controlled unit, via the control signal output terminal 74 and the FFC 121. As shown in FIG. 9, the logic circuit 71 has an input terminal (input side) 71a and an output terminal (output side) 71b. When a digital signal is input to the input terminal (input side) 71a, whether the same value as the value logically applied to the input terminal (input side) 71a is output to the output terminal (output side) 71b. Alternatively, a result obtained by performing a logical operation such as AND, OR, NOT, XOR or the like on the value applied to the input terminal (input side) 71a is output. This circuit is normally composed of a TTL circuit, a CMOS circuit, etc., operates at a low voltage of 5 V or less, and the input and output voltages are usually 5 V or less.

  Unlike the first embodiment, the cutoff circuit 72 is a diode and has an anode terminal 72a and a cathode terminal 72b.

  The resistor 73 has a terminal 73a and a terminal 73b. During a normal operation in which no overvoltage is applied to the control signal output terminal 74, the control signal output terminal 74 is connected to a circuit such as the level shifter 314 in FIG. 7, and thus enters a high impedance state, and the potential of the cathode terminal 72b of the diode. Becomes unstable, and the operation of the diode becomes unstable. In that case, the resistance 73 can stabilize the potential of the cathode terminal 72b of the diode.

  The output terminal (output side) 71 b of the logic circuit 71 is connected to the anode terminal 72 a of the diode 72. The cathode terminal 72 b of the diode 72 is connected to the terminal 73 a of the resistor 73 and the control signal output terminal 74. A terminal 73b of the resistor 73 is connected to the ground.

  Normally, a voltage higher than the operating voltage of the logic circuit 71 (the voltage of the output terminal (output side) 71b of the logic circuit 71) is not applied to the control signal output terminal 74. Accordingly, the anode terminal 72a and the cathode terminal 72b of the diode 72 are turned on, and the voltage of the control signal output terminal 74 is equal to the voltage of the output terminal (output side) 71b of the logic circuit 71. Further, since the resistance between the anode terminal 72a and the cathode terminal 72b of the diode 72 is smaller than that of the resistance 73, there is almost no current flowing through the resistor 73 to the ground.

  However, when an abnormality occurs, that is, when an overvoltage equal to or higher than the operating voltage of the logic circuit 71 (voltage of the output terminal (output side) 71b of the logic circuit 71) is applied to the control signal output terminal 74, the anode terminal 72a of the diode 72 and the cathode Since the terminal 72b is turned off, the overvoltage applied to the control signal output terminal 74 is not applied to the output terminal (output side) 71b of the logic circuit 71.

  Thus, by providing the diode 72 between the control signal output terminal 74 and the output terminal (output side) 71b of the logic circuit 71, the control signal output terminal 74 is connected to the output terminal (output side) 71b of the logic circuit 71. When a higher voltage is applied, the logic circuit 71 can be prevented from being destroyed.

(Modification of the second embodiment)
Next, a modification of the second embodiment will be described with reference to FIG.

  FIG. 10 is a circuit diagram of an overvoltage protection device according to this modification.

  The overvoltage protection device in the present modification is different from the control circuit in the second embodiment in that a detection signal is output when an overvoltage is applied to the control signal output terminal. That is, in the second embodiment, unlike having no means for detecting when an overvoltage is applied to the control signal output terminal, the overvoltage protection device in this modification is connected to the control signal output terminal, When a voltage higher than the reference voltage is applied to the control signal output terminal, the comparator has a comparison circuit that compares the voltage of the control signal output terminal with a reference voltage based on the normal voltage on the output side of the logic circuit. A detection signal is output from the output terminal of the comparison circuit.

  This modification is the same as the modification of the first embodiment in which a diode is used for the cutoff circuit.

  The configurations of the head drive control unit and the head driver and the configuration of the overvoltage protection device in the modified example are the same as the modified example of the first embodiment, and are the same as the configuration shown in FIG. However, the overvoltage protection device 80 according to this modification includes a logic circuit 81, a cutoff circuit (diode) 82, a resistor 83, a control signal output terminal 84, a resistor 85, a comparator (comparison circuit) 86, a reference voltage generator 87, an overvoltage. Since the detection signal output terminal 88 is provided, the symbols of the overvoltage protection device 60, the logic circuit 61, the cutoff circuit 62, and the control signal output terminal 64 in FIG. 7 are the symbols in parentheses, and the overvoltage protection device 80, the logic circuit. 81, a cutoff circuit 82, and a control signal output terminal 84.

  As shown in FIG. 7, the logic circuit 81 generates a control signal for controlling the head driver 208, which is a controlled unit, via the control signal output terminal 84 and the FFC 121. As shown in FIG. 10, the logic circuit 81 has an input terminal (input side) 81a and an output terminal (output side) 81b. When a digital signal is input to the input terminal (input side) 81a, the output terminal (output side) 81b is logically output with the same value as the value applied to the input terminal (input side) 81a. Alternatively, a result obtained by performing a logical operation such as AND, OR, NOT, or XOR on the value applied to the input terminal (input side) 81a is output. This circuit is normally composed of a TTL circuit, a CMOS circuit, etc., operates at a low voltage of 5 V or less, and the input and output voltages are usually 5 V or less.

  The cutoff circuit 82 is a diode and has an anode terminal 82a and a cathode terminal 82b.

  The resistor 83 has a terminal 83a and a terminal 83b. The resistor 85 has a terminal 85a and a terminal 85b. During normal operation in which no overvoltage is applied to the control signal output terminal 84, the control signal output terminal 84 is connected to a circuit such as the level shifter 314 in FIG. The potential becomes unstable, and the operation of the field effect transistor becomes unstable. In that case, the potential of the cathode terminal 82b of the diode can be stabilized by the resistors 83 and 85. Further, when an overvoltage is applied to the control signal output 84, the voltage divided by the resistors 83 and 85 is applied to the positive input terminal of the comparator 86. Thereby, an overvoltage detection signal can be detected without using a comparator having a large allowable input voltage.

  The comparator 86 compares the voltage at the control signal output terminal 84 with the reference voltage generated by the reference voltage generator 87 and outputs the result from the overvoltage detection signal output terminal 88.

  The output terminal (output side) 81 b of the logic circuit 81 is connected to the anode terminal 82 a of the diode 82. The cathode terminal 82 b of the diode 82 is connected to the terminal 83 a of the resistor 83 and the control signal output terminal 84. The terminal 83b of the resistor 83 is connected to the terminal 85a of the resistor 85, and the terminal 85b of the resistor 85 is connected to the ground. The positive input terminal of the comparator 86 is connected to the terminal 83 b of the resistor 83 and the terminal 85 a of the resistor 85. The negative input terminal of the comparator 86 is connected to the positive terminal of the reference voltage generator 87. The negative terminal of the reference voltage generator 87 is connected to the ground. The reference voltage generated by the reference voltage generator 87 is a voltage determined in advance based on the voltage of the normal output terminal (output side) 81 b of the logic circuit 81.

  Normally, a voltage higher than the operating voltage of the logic circuit 81 (voltage on the output side of the logic circuit 81) is not applied to the control signal output terminal 84. Therefore, the anode terminal 82a and the cathode terminal 82b of the diode 82 are turned on, and the voltage of the control signal output terminal 84 is equal to the voltage of the output terminal (output side) 81b of the logic circuit 81. Further, since the resistance between the anode terminal 82a and the cathode terminal 82b of the diode 82 is smaller than the sum of the resistors 83 and 85, there is almost no current flowing through the resistors 83 and 85 to the ground.

  Further, since there is almost no current flowing through the resistor 83, the voltage applied to the positive input terminal of the comparator 86 can be made substantially equal to the voltage of the control signal output terminal 84, for example, by making the resistor 83 smaller than the resistor 85. it can. The reference voltage of the reference voltage generator 87 applied to the negative input terminal of the comparator 86 is, for example, the normal input terminal of the comparator 86 when a voltage is applied from the output terminal (output side) 81b of the logic circuit 81 during normal operation. In general, the voltage applied to the positive input terminal of the comparator 86 is equal to the voltage applied to the positive input terminal of the comparator 86 by making the voltage 20% larger than the voltage applied to the voltage (approximately equal to the voltage of the output terminal (output side) 81b of the logic circuit 81) Since the voltage is smaller than the voltage applied to the negative input terminal 86, the detection signal is not output from the overvoltage detection signal output terminal 88 connected to the output terminal of the comparator 86.

  However, when an abnormality occurs, that is, when an overvoltage equal to or higher than the operating voltage of the logic circuit 81 (voltage of the output terminal (output side) 81b of the logic circuit 81) is applied to the control signal output terminal 84, the anode terminal 82a and the cathode of the diode 82 Since the terminal 82c is turned off, the overvoltage applied to the control signal output terminal 84 is not applied to the output terminal (output side) 81b of the logic circuit 81.

  Furthermore, current flows through the resistors 83 and 85. For example, the voltage applied to the positive input terminal of the comparator 86 can be made substantially equal to the voltage of the control signal output terminal 84 by making the resistor 83 smaller than the resistor 85, for example. it can. Here, when the voltage applied to the control signal output terminal 84 is 20% or more larger than the voltage equal to the voltage of the output terminal (output side) 81b of the logic circuit 81 in the normal state, the magnitude relationship with the above-described reference voltage is obtained. Since the voltage applied to the positive input terminal of the comparator 86 becomes larger than the voltage applied to the negative input terminal of the comparator 86, the detection signal is output from the overvoltage detection signal output terminal 88 connected to the output terminal of the comparator 86. Is output.

  Thus, by providing the diode 82 between the control signal output terminal 84 and the output terminal (output side) 81b of the logic circuit 81, the control signal output terminal 84 is connected to the output terminal (output side) 81b of the logic circuit 81. When a higher voltage is applied, the logic circuit 81 can be prevented from being destroyed.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims. Can be modified or changed.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the overvoltage protection apparatus which concerns on the 1st Embodiment of this invention, and is side explanatory drawing explaining the whole structure of the mechanism part of the inkjet recording device containing an overvoltage protection apparatus. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining an overvoltage protection device according to a first embodiment of the present invention, and is an explanatory plan view for explaining an overall configuration of a mechanism unit of an ink jet recording apparatus including the overvoltage protection device. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the overvoltage protection apparatus which concerns on the 1st Embodiment of this invention, and is block explanatory drawing explaining the outline | summary of the control part of the inkjet recording device containing an overvoltage protection apparatus. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure for demonstrating the overvoltage protection apparatus which concerns on the 1st Embodiment of this invention, and is block explanatory drawing explaining an example of the head drive control part and head driver in the control part of the inkjet recording device containing an overvoltage protection apparatus It is. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram for explaining an overvoltage protection device according to a first embodiment of the present invention, and is an explanatory diagram for explaining an example of an analog switch of a head driver of an ink jet recording apparatus including the overvoltage protection device. 1 is a circuit diagram of an overvoltage protection device according to a first embodiment of the present invention. It is a figure for demonstrating the overvoltage protection apparatus which concerns on the modification of the 1st Embodiment of this invention, and demonstrates an example of the head drive control part and head driver in the control part of the inkjet recording device containing an overvoltage protection apparatus. It is block explanatory drawing. It is a circuit diagram of the overvoltage protection apparatus which concerns on the modification of the 1st Embodiment of this invention. It is a circuit diagram of the overvoltage protection apparatus which concerns on the 2nd Embodiment of this invention. It is a circuit diagram of the overvoltage protection apparatus which concerns on the modification of the 2nd Embodiment of this invention. FIG. 3 is a perspective view illustrating a state in which a recording head is mounted on a carriage in the inkjet recording apparatus. FIG. 2 is a diagram illustrating a state in which a recording head and a relay substrate are connected in a carriage in an ink jet recording apparatus.

Explanation of symbols

4 Carriage 11 Recording head 22 Recording medium (paper)
31 Conveying belt 32 Conveying roller 36 Conveying motors 50, 60, 70, 80 Overvoltage protection devices 51, 61, 71, 81 Logic circuits 51a, 61a, 71a, 81a Input terminals 51b, 61b, 71b, 81b Output terminals 52, 62 Shut off Circuit (field effect transistor)
52a, 62a Drain terminal 52b, 62b Gate terminal 52c, 62c Source terminal 53, 63, 65, 73, 83, 85 Resistor 53a, 63a, 65a, 73a, 83a, 85a Terminal 53b, 63b, 65b, 73b, 83b, 85b Terminals 54, 64, 74, 84 Control signal output terminals 66, 86 Comparators 67, 87 Reference voltage generators 68, 88 Overvoltage detection signal output terminals 72, 82 Cutoff circuit (diode)
120 flexible substrate 121 FFC (flexible flat cable)
122 Printed wiring board (relay board)
123 connector 200 control unit 207 head drive control unit 208 head driver 301 drive waveform generation circuit 302 data transfer unit

Claims (4)

A logic circuit for generating a control signal for controlling the controlled part;
Control provided on the output side of the logic circuit to connect the output side of the logic circuit in a separable manner with the processing target and to output the control signal generated by the logic circuit to the controlled unit A signal output terminal;
A cutoff circuit that is provided between the output side of the logic circuit and the control signal output terminal, and that cuts off a current path between the output side of the logic circuit and the control signal output terminal;
The overvoltage protection, wherein when the voltage higher than the output side voltage of the logic circuit is applied to the control signal output terminal, the logic circuit is protected by blocking the blocking circuit. apparatus. A comparison circuit connected to the control signal output terminal, for comparing a voltage of the control signal output terminal with a reference voltage based on a voltage on the output side of the logic circuit at a normal time;
2. The overvoltage protection device according to claim 1, wherein when a voltage higher than the reference voltage is applied to the control signal output terminal, a detection signal is output from the output terminal of the comparison circuit.   The overvoltage protection device according to claim 1, wherein the blocking circuit is a diode-connected field effect transistor.   The overvoltage protection device according to claim 1, wherein the interruption circuit is a diode.

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