JP2018192791A - Element substrate, recording head, and recording apparatus - Google Patents

Abstract

To provide an element substrate which resets or latches signals in consideration of the roll played by each functional circuit even when a transfer error occurs.SOLUTION: The element substrate comprises a plurality of functional circuits that perform a plurality of functions, respectively, necessary to perform recording actions. Further, there are provided: a data identification circuit, which receives data signals from outside and transfers the received data signals to corresponding functional circuits according to results of identifying kinds of data included in the received data signals; and an error sensing circuit, which senses whether transfer errors occur in the received data signals. Here, a latch signal received from outside and a reset signal are made to reflect a sensing result by the error sensing circuit. According to a function served by each of the plurality of functional circuits, a part of the functional circuits is made to latch data signals transferred by latch signals where sensing results are reflected. On the other hand, the remaining functional circuits are controlled to reset data signals transferred by reset signals where a sensing result is reflected.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an element substrate, a recording head, and a recording apparatus, and in particular, an element substrate provided with a circuit including a plurality of recording elements that perform recording on a recording medium and a driving element that drives each recording element, and the element substrate And a recording apparatus using the recording head.

  As a method of driving an ink jet recording head (hereinafter referred to as recording head), an electrothermal conversion element (heater) is provided at a portion communicating with an ejection port for ejecting ink droplets, and an electric current is supplied to the heater to generate heat. A method of ejecting ink droplets by boiling is known. A switching element is connected to each heater, and a current flows through the heater when the switching element is turned on according to data. In order to drive a plurality of heaters provided corresponding to a plurality of discharge ports arranged in a row, a system in which a plurality of heaters are divided into a plurality of blocks and the heaters of each block are time-division driven is generally used. It's being used.

  FIG. 10 is a diagram showing a configuration of a transistor as a plurality of heaters mounted on an element substrate of a conventional recording head and a switching element for driving each heater. FIG. 10 illustrates m × n heaters 1001-11 to 1001 -mn and transistors 1002-11 to 1002 -mn. m × n heaters are respectively provided in m × n discharge ports.

  As shown by a broken line in FIG. 10, m × n heaters and transistors are divided into m groups each including n. That is, m × n heaters and transistors are divided into m groups 1003-1 to 1003-m every n, and the ground side of each heater 1000-ij is connected to the NMOS transistor 1002-ij. Yes. In FIG. 10, the n-th recording element of the m group is represented as 1001-mn.

  For example, the sources of the NMOS transistors 1002-m1 to mn of the group m are electrically connected to the ground pad 1005. On the other hand, the heaters 1001-m1 to mn are electrically connected to a power supply voltage pad 1004 for supplying power from the outside. When a drive signal is generated based on data from a printing apparatus (not shown) and a drive voltage is applied to the gate of the NMOS transistor 1002-ij, a current flows through the corresponding heater 1001-ij, and thermal energy is applied to the ink to discharge the ink. It is discharged from the outlet. By time-division driving, a maximum of one heater of the same group is driven simultaneously during one block driving time, so that the voltage drop is constant regardless of the number of simultaneous driving.

  In the source follower configuration in which the source of the NMOS transistor is connected to the power supply voltage, the heater is driven when a drive voltage is applied to the gate of the NMOS transistor. In a configuration in which an NMOS transistor and a PMOS transistor are arranged on both sides of the heater, when a drive voltage is applied to the gates of both transistors, the recording element is driven.

  Now, as the recording by the recording head becomes multicolored, the recording width of the recording head becomes longer, and the recording speed increases, the amount of signals transferred to the recording head increases and the signal transmission path becomes longer. There is a possibility that an error occurs in the transfer of recording data.

  For example, if a transfer error occurs in the data for selecting the heater, the wrong heater is driven, and if a transfer error occurs in the signal that defines the drive time, a drive pulse with a pulse width different from that desired is generated. The quality of the recorded image is reduced. Therefore, in order to prevent deterioration of image quality, a circuit for detecting a transfer error is provided in the element substrate, and when the data is in error, control is performed to stop driving the heater at the next time division timing. Yes.

  In addition to the data for selecting the heater, the data transferred from the recording device includes the data for controlling the heater from the recording device based on the temperature information of the element substrate. Various error information is selected from the recording head. Data to be transmitted to the recording device. For example, since the ink discharge amount and the ink discharge speed vary depending on the detected temperature of the element substrate, it is necessary to prevent temperature control based on erroneous data from being executed.

  As described above, as data transfer speeds up and the amount of data increases, it is detected whether data transfer is being performed normally. Action must be taken. For example, Patent Document 1 proposes a configuration in which when an error occurs in reading from a memory, it is reset at high speed and read again to prevent malfunction caused by the error.

  Now, in a full line recording head with a long recording width and a large number of ejection ports, a plurality of element substrates are mounted, and the number of terminals and the number of wirings of the recording head increase, so these must be suppressed as much as possible. . In addition, the data transfer rate is naturally required to be increased. Under such restrictions, data is not transferred for every transfer operation for all the functions of the recording head, but only the necessary amount is transferred at the timing of executing the target function. .

Japanese Patent No. 5039061

  However, with the recent increase in data transfer speed to the recording head, there is no time for resetting and rereading the memory as in Patent Document 1, so that the target processing can be performed only by one transfer. Required.

  In addition, when the data is transferred at an arbitrary cycle instead of transferring the corresponding data for each transfer operation, if the data signal is reset, the function corresponding to the next cycle cannot be used. End up. For this reason, the recording operation cannot be executed normally, and the recording medium may be wasted.

  Also, in the method of receiving the error detection result from the recording head on the recording apparatus main body side and performing the recording control corresponding to this, the feedback control takes time, so the processing corresponding to the error occurrence in the element substrate Is required to complete.

  The present invention has been made in view of the above conventional example. In consideration of the role played by each functional circuit even if a transfer error occurs, an element substrate for resetting and latching a signal, and a recording head including the element substrate An object of the present invention is to provide a recording apparatus including the recording head.

  In order to achieve the above object, the element substrate of the present invention has the following configuration.

  That is, an element substrate on which a plurality of recording elements and a plurality of driving elements that drive the plurality of recording elements are mounted, and a plurality of functional circuits that respectively execute a plurality of functions necessary for executing a recording operation; Receives a data signal from the outside, identifies the type of data included in the received data signal, and transfers the received data signal to a corresponding functional circuit among the plurality of functional circuits according to the identification result A data identification circuit that receives the data signal, an error detection circuit that detects whether a transfer error has occurred in the received data signal, a latch signal received from the outside, and a reset signal received from the error Reflecting the detection result by the detection circuit, and according to the function performed by each of the plurality of functional circuits, for some functional circuits among the plurality of functional circuits The transferred data signal is latched by a latch signal reflecting the knowledge result, and the other function circuit among the plurality of function circuits is transferred by the reset signal reflecting the detection result. And a control circuit that controls to reset the data signal.

  In another aspect of the present invention, a recording head using the element substrate having the above configuration is provided.

  According to another aspect of the present invention, a recording apparatus for recording on a recording medium using the recording head is provided.

  According to the present invention, it is possible to reset or latch a signal in consideration of the role played by each functional circuit even if a transfer error occurs. As a result, regarding the execution of a certain function, even if a transfer error occurs, it is possible to perform a quick response by performing an operation using previously held data.

1 is a perspective view illustrating a schematic configuration of a recording apparatus that performs recording by ejecting ink from an inkjet recording head that is a representative embodiment of the present invention. FIG. 2 is a block diagram illustrating a control configuration of the recording apparatus illustrated in FIG. 1. 1 is a block diagram showing a schematic configuration of an element substrate according to Example 1. FIG. It is a figure which shows the timing chart of the signal from the outside input into the element board | substrate shown in FIG. 3, and the various signals produced | generated inside an element board | substrate. 6 is a block diagram showing a schematic configuration of an element substrate according to a modification of Example 1. FIG. 6 is a block diagram showing a schematic configuration of an element substrate according to Example 2. FIG. It is a figure which shows the timing chart of the signal from the outside input into the element board | substrate shown in FIG. 6, and the various signals produced | generated inside an element board | substrate. 6 is a block diagram showing a schematic configuration of an element substrate according to Example 3. FIG. FIG. 10 is a block diagram showing a schematic configuration of an element substrate according to a fourth embodiment. It is a figure which shows the structure of a transistor as a switching element which drives the several heater mounted in the element board | substrate of the conventional recording head, and each heater.

  Hereinafter, preferred embodiments of the present invention will be described more specifically and in detail with reference to the accompanying drawings. In the following description, the same components are referred to with the same reference numerals throughout the drawings. Therefore, the components once described are referred to using the same reference numerals, and the description thereof will not be repeated.

  In this specification, “recording” (sometimes referred to as “printing”) is not limited to the case of forming significant information such as characters and graphics, but may be significant. Furthermore, it also represents a case where an image, a pattern, a pattern, or the like is widely formed on a recording medium or a medium is processed regardless of whether or not it is manifested so that a human can perceive it visually.

  “Recording medium” refers not only to paper used in general recording apparatuses but also widely to cloth, plastic film, metal plate, glass, ceramics, wood, leather, and the like that can accept ink. Shall.

  Further, “ink” (sometimes referred to as “liquid”) should be interpreted widely as in the definition of “recording (printing)”. Therefore, by being applied on the recording medium, it is used for formation of images, patterns, patterns, etc., processing of the recording medium, or ink processing (for example, solidification or insolubilization of the colorant in the ink applied to the recording medium). It shall represent a liquid that can be made.

  Further, the “recording element” (sometimes referred to as “nozzle”) is a general term for an ink discharge port, a liquid path communicating with this, and an element that generates energy used for ink discharge unless otherwise specified. Say it.

  An element substrate (head substrate) for a recording head to be used below does not indicate a simple substrate made of a silicon semiconductor but indicates a configuration in which each element, wiring, and the like are provided.

  Further, the term “on the substrate” means not only the element substrate but also the surface of the element substrate and the inside of the element substrate near the surface. In addition, the term “built-in” as used in the present invention is not a term indicating that each individual element is simply arranged separately on the surface of the substrate, but each element is manufactured in a semiconductor circuit. It shows that it is integrally formed and manufactured on an element plate by a process or the like.

<Description of Inkjet Recording Apparatus (FIG. 1)>
FIG. 1 is an external perspective view showing an outline of the configuration of an ink jet recording apparatus 1 which is a typical embodiment of the present invention.

  As shown in FIG. 1, an ink jet recording apparatus (hereinafter referred to as a recording apparatus) has an ink jet recording head (hereinafter referred to as a recording head) 3 that performs recording by discharging ink in accordance with an ink jet system. Recording is performed by reciprocating in the direction. A recording medium P such as recording paper is fed through the paper feeding mechanism 5 and conveyed to a recording position, and recording is performed by discharging ink from the recording head 3 to the recording medium P at the recording position.

  In addition to mounting the recording head 3 on the carriage 2 of the recording apparatus 1, an ink cartridge 6 for storing ink to be supplied to the recording head 3 is mounted. The ink cartridge 6 is detachable from the carriage 2.

  The recording apparatus 1 shown in FIG. 1 is capable of color recording. For this reason, the carriage 2 contains four inks containing magenta (M), cyan (C), yellow (Y), and black (K) inks, respectively. An ink cartridge is installed. These four ink cartridges are detachable independently.

  The recording head 3 of this embodiment employs an ink jet system that ejects ink using thermal energy. For this reason, an electrothermal converter is provided. The electrothermal transducer is provided corresponding to each of the ejection ports, and ink is ejected from the corresponding ejection port by applying a pulse voltage to the corresponding electrothermal transducer in accordance with the recording signal.

<Control Configuration of Inkjet Recording Apparatus (FIG. 2)>
FIG. 2 is a block diagram showing a control configuration of the recording apparatus shown in FIG.

  As shown in FIG. 2, the controller 600 includes an MPU 601, a ROM 602, a special purpose integrated circuit (ASIC) 603, a RAM 604, a system bus 605, an A / D converter 606, and the like. Here, the ROM 602 stores a program corresponding to a control sequence to be described later, a required table, and other fixed data. The ASIC 603 generates control signals for controlling the carriage motor M1, the transport motor M2, and the recording head 3. The RAM 604 is used as a development area for image data, a work area for program execution, and the like. A system bus 605 connects the MPU 601, the ASIC 603, and the RAM 604 to each other to exchange data. The A / D converter 606 inputs analog signals from the sensor group described below, performs A / D conversion, and supplies a digital signal to the MPU 601.

  In FIG. 2, reference numeral 610 denotes a computer (or a reader for image reading, a digital camera, etc.) serving as a supply source of image data, and is collectively referred to as a host device. Image data, commands, status signals, and the like are transmitted and received between the host apparatus 610 and the recording apparatus 1 via an interface (I / F) 611. This image data is input in a raster format, for example.

  Reference numeral 620 denotes a switch group, which includes a power switch 621, a print switch 622, a recovery switch 623, and the like.

  Reference numeral 630 denotes a sensor group for detecting the apparatus state, and includes a position sensor 631, a temperature sensor 632, and the like.

  Further, 640 is a carriage motor driver that drives a carriage motor M1 for reciprocating scanning of the carriage 2 in the direction of arrow A, and 642 is a conveyance motor driver that drives a conveyance motor M2 for conveying the recording medium P. Reference numeral 644 denotes a head driver that drives the recording head based on recording data and control signals transferred from the controller 600.

  The ASIC 603 transfers data for driving a recording element (ejection heater) to the recording head while directly accessing the storage area of the RAM 604 during recording scanning by the recording head 3. In addition to this, the ASIC 603 receives data for controlling the temperature of the element substrate (start instruction data / stop instruction data) and detection element selection data for selecting a detection element from a plurality of detection elements for the print head. Forward. The data update interval is determined for each type of data. For this reason, the data transfer interval differs depending on the type of data. Data for controlling the temperature of the element substrate The ASIC 603 outputs a reset signal RESET of “H” (high level) to the recording head for a predetermined time, for example, when the power is turned on. In other cases, the ASIC 603 outputs an “L” (low level) reset signal RESET to the recording head. The circuit of the recording head is initialized when a reset signal RESET of “H” is received. The timing at which the ASIC 603 outputs the “H” (high level) signal may be other timing. For example, the timing from when the “L” (low level) pulse signal is input to the latch signal LT to before the data signal DATA is input may be used.

  Next, an example of the element substrate mounted on the recording head mounted on the recording apparatus having the above configuration will be described.

  In this embodiment, the recording element driving configuration as described with reference to FIG. 10 is used. However, other driving configurations may be used. In the embodiments described below, a configuration will be described in which an element substrate responds to an error in a self-contained manner, particularly with respect to an error occurring in a recording head (element substrate).

  FIG. 3 is a block diagram showing a schematic configuration of the element substrate according to the first embodiment.

  As shown in FIG. 3, the element substrate 101 includes a data receiving circuit 102, a recording element selection circuit 103, a drive time generation circuit 104, and a drive circuit 105. The element substrate 101 includes a reception terminal for receiving the data signal DATA, a reception terminal for receiving the latch signal LT, and a terminal for receiving the reset signal RESET.

  The data receiving circuit 102 includes a data identification circuit 201 and an error detection circuit 202. The data identification circuit 201 identifies the data signal DATA received from the outside, transfers it to the corresponding functional circuit, and outputs a data presence / absence identification result RST1 indicating whether or not drive time generation data has been sent. Note that the data receiving circuit 102 transfers data corresponding to each functional circuit regardless of whether there is a data error. Therefore, in other words, the data receiving circuit 102 can be said to be a transfer circuit that transfers data according to the identification result.

  The functional circuit here corresponds to the recording element selection circuit 103 and the drive time generation circuit 104. The recording element selection circuit 103 receives a recording data signal from the data receiving circuit 102 and selects a recording element to be driven in each block based on the recording data signal when driving a plurality of recording elements of the recording head 3 in a time-sharing manner. It performs a specific function. On the other hand, the drive time generation circuit 104 receives a drive time signal that defines the time for driving the recording elements from the data receiving circuit 102 when driving the plurality of recording elements of the recording head 3 in a time-sharing manner. It performs a specific function of transmitting a signal to the drive circuit 105. As described above, since the recording element selection circuit 103 and the drive time generation circuit 104 each perform a specific function in the recording operation, they are generally called function circuits.

  The error detection circuit 202 checks whether there is an error in the transfer of the data signal DATA. Specifically, a parity check circuit or a CRC circuit is used for the circuit. The recording element selection circuit 103 includes a shift register 203 and a latch circuit 204. The drive time generation circuit 104 includes a shift register 205 and a latch circuit 206. The results OUT1 and OUT2 output from the recording element selection circuit 103 and the driving time generation circuit 104 are calculated by the driving circuit 105, and the switching elements (driving elements) corresponding to the recording elements according to the driving configuration described with reference to FIG. Driven. Therefore, the drive circuit 105 is mounted with the same circuit as shown in FIG.

  The NOR circuit 303 calculates a negative logical sum (NOR) of the detection result RST2 from the error detection circuit 202 and the latch signal LT received from the outside, and the calculation result RST3 and the data presence / absence identification result RST1 are negative logic by the NAND circuit 304. The product is calculated. The operation result RST4 by the NAND circuit 304 is transmitted to the latch circuit 206 of the drive time generation circuit 104. Further, a logical sum (OR) is calculated for the detection result RST2 of the error detection circuit 202 by the reset signal received from the outside and the OR circuit 309, and the calculation result RST5 is transmitted to the shift register 203 of the recording element selection circuit 103.

  The circuit configuration shown in FIG. 3 is summarized as follows.

  A data signal DATA, a latch signal LT for latching the data signal by a latch circuit, and a reset signal RESET for resetting the data signal DATA held inside the element substrate are externally supplied to the element substrate 101 (controller 600 of the recording apparatus). Is entered. The element substrate 101 checks whether or not there is a transfer error in the received data signal DATA, and reflects the result in the received latch signal LT and reset signal RESET.

  The shift register 203 of the recording element selection circuit 103 holds the recording data signal identified by the data identification circuit 201, while the recording data signal held by the reset signal RESET reflecting the transfer error detection result is reset ( Cleared). Accordingly, the record data signal held in the shift register 203 is cleared by RST5. That is, when a transfer error occurs, the latch circuit 204 of the recording element selection circuit 103 latches the clear data held by the shift register 203. On the other hand, the latch circuit 204 of the recording element selection circuit 103 latches the recording data signal held in the shift register 203 by the received latch signal LT.

  On the other hand, the shift register 205 of the driving time generation circuit 104 holds the heat signal identified by the data identification circuit 201, and the heat signal held by the received reset signal RESET is reset. In this embodiment, when the reset signal RESET is “H”, the contents of the shift register 205 are reset (cleared). On the other hand, the latch circuit 206 of the drive time generation circuit 104 latches the heat signal held in the shift register 205 with a latch signal LT that reflects the transfer error detection result. Supplementally, when no transfer error occurs, the latch circuit 206 receives a signal having the same logic as the latch signal LT received by the receiving circuit 102. That is, the latch circuit 206 receives the latch signal LT as it is. Therefore, the latch circuit 206 latches the heat signal held in the shift register 205. However, when a transfer error occurs, even if the receiving circuit 102 receives the latch signal LT, the transfer error detection result is reflected in the logic of the signal, and therefore the transfer of the latch signal LT to the latch circuit 206 is not performed. Deterred. Therefore, when a transfer error occurs, the latch circuit 206 does not latch the heat signal held by the shift register 205. For this reason, the latch circuit 206 continues to hold the heat signal latched before the transfer error occurs. In addition, when receiving a data presence / absence identification result RST1 from the data identification circuit 201 indicating that the predetermined type of data data has not been received, the reception circuit 102 may receive the latch signal LT. The result of the notification is reflected in the signal logic. For this reason, the transfer of the latch signal LT to the latch circuit 206 is inhibited.

  With the circuit configuration as described above, an operation in which the transfer error detection result is reflected in the reset of the recording data signal in the recording element selection circuit 103 and the transfer error detection result is reflected in the latch of the heat signal in the drive time generation circuit 104 is executed. Is done.

  FIG. 4 is a diagram showing timing charts of external signals input to the element substrate shown in FIG. 3 and various signals generated inside the element substrate.

  Only the data signal DATA necessary for each recording operation is transmitted from the recording apparatus main body. The header of the data signal DATA includes data received by the data identification circuit 201, and the footer thereof includes data that is determined by the error detection circuit 202 executing an error detection process. Since the plurality of recording elements mounted on the recording head 3 are driven in a time-sharing manner, the recording data used for recording in the recording elements of each block (BLK1, BLK2,...) Is latched by the latch signal LT. FIG. 4 shows input of data signals corresponding to five blocks (BLK1 to BLK5). For explanation, it is assumed that data signals having different states are input to these blocks. If the states are different, the element substrate 101 performs different operations. Hereinafter, the operation accompanying the data signal input of each block will be described in detail. In the period of FIG. 4, the state of the reset signal RESET received from the outside is “L” (not shown).

-Data signal input in block BLK1 (normal signal input)
According to FIG. 4, with respect to the first block BLK1, normal signals 1A and 2A are inserted between the header and footer of the data signal DATA. Signal 1A is recording element selection data, and signal 2A is drive time generation data. After the signals 1A and 2A are received, they are transferred to the corresponding shift registers 203 and 205, respectively. In FIG. 4, data stored in the shift register 203 is indicated by DATA-P, and data stored in the shift register 205 is indicated by DATA-H.

  When the result of the error detection process determined by the footer is OK (no error: normal), “L” is output as the error detection result RST2. When the data identification circuit 201 receives the drive time generation data, “H” is output to the data presence / absence identification signal RST1 when the data (heat signal) is identified. As a result, the calculation result RST4 input to the latch circuit 206 of the drive time generation circuit 104 by the NAND circuit 304 becomes the same signal as the latch signal LT.

  The signals 1A and 2A are latched at the rising edge of the latch signal LT of the block BLK2, and stored in the corresponding latch circuits 204 and 206. In FIG. 4, this is represented by DATA-P ′ and DATA-H ′, and a desired recording element is driven in the drive circuit 105 by this signal.

・ Data signal input (abnormal signal input) in block BLK2
FIG. 4 shows a case where a signal indicating a state in which data transfer is determined to be an error is detected in the next block BLK2.

  As shown in FIG. 4, since the drive time generation data is transmitted as the signal 2B from the recording apparatus main body, the data presence / absence identification signal RST1 is similar to the block BLK1 when the data (heat signal) is identified. H "is output. On the other hand, since the result of the error detection processing by the error detection circuit 202 is NG (error present, abnormal), “H” is output as the error detection result RST2 after the error is confirmed in the footer data. As a result, the calculation result RST3 of the NOR circuit 303 reflecting the error detection result becomes “L”. However, since the operation result RST4 input to the latch circuit 206 of the drive time generation circuit 104 by the NAND circuit 304 remains “H”, the signal 2B is not latched and the signal 2A is held.

  Further, a logical sum is calculated by the OR signal 309 and the reset signal RESET inputted from the outside with “H” of the error detection result RST 2, and the calculation result RST 5 is inputted to the shift register 203 of the recording element selection circuit 103. As a result, the data input to the shift register 203 is cleared. Therefore, unlike the block BLK1, the latch circuit 204 does not latch the signal 1B.

  The error detection result RST2 returns to “L” at the timing when reception of the data header of the next block BLK3 is started. If the latch signal LT returns to “L” at the rise timing of the latch signal LT of the block BLK3, the error detection result RST2 may fall before the latch signal LT rises to “H”. In this case, since the data is latched in the latch circuit 206, it is necessary to reliably return the error detection result RST2 to “L” after the latch signal LT. In addition, it is necessary to reset the data in the shift register 205 before the next latch signal LT after the error is confirmed in the data footer and the error detection result RST2 is output. Otherwise, the data DATA-P of the signal 1B is latched by the latch circuit 204.

-Data signal input in block BLK3 (data input that does not cause a recording operation)
According to FIG. 4, in the block BLK3, the data signal DATA received by the element substrate does not include the recording element selection data and the drive time generation data.

  In this case, the data presence / absence identification result RST1 is “L” because there is no drive time generation data, and the calculation result RST4 input to the latch circuit 206 of the drive time generation circuit 104 remains “H”. Therefore, the latch circuit 206 does not latch the input data signal at the first timing of the block BLK4, and holds the previous signal 2A.

  On the other hand, since the result of the error detection processing by the error detection circuit 202 is OK (no error: normal), the error detection result RST2 is “L”, and the calculation result RST5 input to the recording element selection circuit 103 is “L”. Become. As a result, the shift register 203 of the recording element selection circuit 103 sends the contents cleared in the block BLK 2 to the latch circuit 204. When data that causes a recording operation over a plurality of blocks is not included, the state of the block BLK3 continues.

・ Data signal input in block BLK4 and 5 (normal signal input)
The block BLK4 includes printing element selection data and drive time generation data. In this case, when the error detection result RST2 indicating that the result of the error detection processing by the error detection circuit 202 is OK is output, the operation is the same as that of the block BLK1 described above. Accordingly, normal data is latched by the corresponding circuit at the rising edge of the latch signal LT in the block BLK5.

  Therefore, according to the above-described embodiment, when a data signal transfer error occurs, the printing element selection data is reset, but the drive time generation data is not latched, and the data for confirming normality by error detection processing is present. Can be held until obtained. As a result, it is possible to prevent the recording element from being driven with erroneous data, and to retain the driving time generation data that is not transferred for each block, so that the recording operation can be resumed as soon as the data transfer is resumed. . As described above, the data that is updated and the data that is not updated are distinguished by the block cycle of the time-division drive of the printing element, and reset and latch are performed according to the distinction. In FIG. 3 of the first embodiment, the data identification circuit 201 outputs the data presence / absence identification result RST1, but if the data presence / absence identification is unnecessary, the NAND circuit 304 is omitted and the latch circuit 206 is the NOR circuit 303. May be configured to receive RST3.

<Modification>
Although the element substrate described here has a configuration including one data identification circuit, a plurality of data identification circuits may be provided corresponding to a plurality of data signal inputs.

  FIG. 5 is a block diagram illustrating a schematic configuration of an element substrate according to a modification of the first embodiment. Here, an example in which two data identification circuits having the same configuration are mounted is shown. In FIG. 5, the same reference numerals and symbols are used to refer to the components and signals already described in FIG. 3, and descriptions thereof are omitted. The data identification circuits 201A and 201B are provided corresponding to the recording element selection circuit 103 and the drive time generation circuit 104, respectively. Further, the data identification circuits 201A and 201B have the same configuration and the same configuration as the data identification circuit 201 described in FIG. 3, and the error detection circuits 202A and 202B also have the same configuration, and the error detection described in FIG. The circuit has the same configuration as the circuit 202. The difference between the data identification circuits 201A and 201B is that the data identification circuit 201A does not output the signal RST1, and the data identification circuit 201B outputs the signal RST1. Also in this modification, the data receiving circuit 102 transfers data corresponding to the functional circuit regardless of whether there is a data error.

  In the example of FIG. 5, the data signal DATA1 is input to the data identification circuit 201A, and the DATA2 is input to the data identification circuit 201B. Then, error detection processing is executed on the data signal DATA1 by the error detection circuit 202A, and error detection processing is executed on the data signal DATA2 by the error detection circuit 202B. The data identification circuit 201B outputs the data presence / absence identification result RST1 as in the first embodiment.

  When the error detection circuit 202A detects an error, the error detection result RST2A is ORed with the input reset signal RESET and the OR circuit 309A, and the shift register 203 of the recording element selection circuit 103 is reset by the calculation result RST5. . On the other hand, when an error is detected by the error detection circuit 202B, the NOR circuit 303 calculates a negative logical sum (NOR) between the error detection result RST2B and the input latch signal LT. The NAND circuit 304 calculates a negative logical product of the calculation result RST3 and the data presence / absence identification result RST1. NAND circuit 304 outputs operation result RST4 to latch circuit 206. Then, until the next normal data signal is received, the latch circuit 206 of the drive time generation circuit 104 is not latched.

  With the circuit configuration as described above, when one of the error detection circuits detects a transfer error, the normal recording operation (drive of the recording element) is performed by resetting the shift register or suppressing the latch operation of the latch circuit. Can be suppressed. Further, by providing an independent data signal input terminal and a data identification circuit, it is not necessary to output the data presence / absence identification result RST1 for the data signal DATA1.

  Note that the circuit configuration illustrated in FIG. 5 is merely an example, and a combination of connections of the data identification circuit, the error detection circuit, and each functional circuit can be arbitrarily configured.

  FIG. 6 is a block diagram showing a schematic configuration of an element substrate according to the second embodiment. In FIG. 6, the same reference numbers and symbols are used to refer to the components and signals already described in FIG. 3, and descriptions thereof are omitted. As can be seen by comparing FIG. 6 and FIG. 3, in this element substrate, the error detection result RST2 is logically ORed by the reset signal RESET and the OR circuit 309 via the latch circuit 207, and the operation result RST5 is calculated by the shift register 203. Are connected to the latch circuit 204. When the calculation result RST5 is input, the signals input to the shift register 203 and the latch circuit 204 are cleared.

  According to this configuration, after the error detection result RST2 is output, if the reset of the shift register 203 is not in time before the next rise of the latch signal LT, the error detection result RST2 is latched at the rise of the latch signal LT of the next block. Latch at 207. The latched error detection result RST2 is transmitted again to the shift register 203 and the latch circuit 204 as an operation result RST5 that is a result of a logical OR operation with the input reset signal RESET. Note that the latch circuit 207 is reset by a reset signal RESET1 output from the error detection circuit 202.

  FIG. 7 is a timing chart of external signals input to the element substrate shown in FIG. 6 and various signals generated inside the element substrate. In FIG. 7, the signals already described in FIG. 4 and the operations according to the signals are referred to using the same symbols, and the description thereof is omitted. Even during the period of FIG. 7, the state of the reset signal RESET received from the outside is “L” (not shown).

  As shown in FIG. 7, the erroneous signal 1 </ b> B input to the shift register 203 may be temporarily input to the latch circuit 204 during the latch operation to the latch circuit 204. However, according to the circuit configuration of the element substrate of this embodiment, the calculation result RST5 is also input to the latch circuit 204 at the rise of the latch signal LT in the block BLK3, and is reset. The error detection circuit 202 outputs a reset signal RESET1 at the start of reception of the data header of the block BLK3, and resets the latch circuit 207. As a result, the calculation result RST5 falls before the next block driving data signal after the header is input.

  Therefore, according to the embodiment described above, when a data signal transfer error is detected, an error detection result is output even if the shift register storing the data signal is not in time before the next latch signal rises. If it is done, it can be reset. For this reason, the timing constraint until the error detection processing time and the data signal latch operation is relaxed.

  FIG. 8 is a block diagram showing a schematic configuration of an element substrate according to the third embodiment. In FIG. 8, the same reference numerals and symbols are used to refer to the components and signals already described in FIG. 3, and description thereof is omitted. As can be seen from a comparison between FIG. 8 and FIG. 3, this element substrate does not include a shift register in the recording element selection circuit 103 and the drive time generation circuit 104, and includes a shift register 208 in the data identification circuit 201. There is a feature.

  In this element substrate, as soon as it is identified what function the data received by the data identification circuit 201 corresponds to, the switch 217 is switched according to the identification result, and the corresponding latch circuit 204 or 206 as the transfer destination is switched. Transfer the corresponding data.

  The data received by the data identification circuit 201 and stored in the shift register 208 is reset when the error detection result RST2 is an error (H). However, since the error detection result RST2 is determined by the footer of the transfer data, the error data transferred earlier has already been transmitted by the latch circuit 204 or 206. For this reason, the data of the latch circuit 204 of the recording element selection circuit 103 is reset by inputting the reset signal RST5 when an error is detected.

  On the other hand, the latch circuit 206 of the drive time generation circuit 104 does not latch data when an error is detected, and holds previous data until normal data is transferred.

  Therefore, according to the embodiment described above, it is possible to prevent the printing element from being driven with erroneous data at the time of a data transfer error as in the first embodiment, and to retain drive time generation data that is not transferred for each drive block. be able to. As a result, the driving of the recording element can be resumed as soon as normal data is transferred.

  Further, according to this embodiment, in the first embodiment, the shift register provided in the recording element selection circuit and the drive time generation circuit is arranged in the circuit on the data reception side. With such an arrangement, the number of wires from the data receiving circuit to each functional circuit is increased as compared with the first embodiment, but the circuit area on each functional circuit side can be reduced.

  FIG. 9 is a block diagram showing a schematic configuration of an element substrate according to the fourth embodiment. In FIG. 9, the same reference numerals and symbols are used to refer to the components and signals already described in FIG. 3, and description thereof is omitted. As can be seen from a comparison between FIG. 9 and FIG. 3, this element substrate includes a temperature detection circuit 106, a temperature control circuit 107, and an error output selection circuit 108 in addition to the configuration of the element substrate described in the first embodiment. There are features. According to the definition of the functional circuit described in the first embodiment, each of these circuits also performs a specific function. Therefore, these circuits can also be called functional circuits.

  In FIG. 9, a temperature detection circuit 106 detects a resistance value (analog signal) of a temperature detection element 109 such as a diode sensor mounted on the element substrate 101, and records from the temperature information output terminal 215 as temperature information TEMP. Is output to the controller 600. This output is made at the timing when the element substrate 101 receives the instruction signal from the controller 600. In the controller 600, the output temperature information is converted into a digital signal by the A / D converter 606, the MPU 601 analyzes the information, and an instruction signal for temperature control based on the analysis result is received by the data signal DATA. Transmit to the substrate 101.

  The data receiving circuit 102 extracts a temperature control instruction signal from the received data signal, and drives the temperature control circuit 107 based on the data included in the instruction signal to control the temperature of the element substrate 101. Examples of data included in the instruction signal include start instruction data and stop instruction data. The temperature control circuit 107 drives the heater mounted on the element substrate 101 for a time according to the instruction signal to heat the element substrate 101. The drive circuit 110 includes a heater mounted on the element substrate 101 and a transistor that drives the heater. As another form, when a plurality of heaters mounted on the element substrate 110 and a plurality of transistors for driving these heaters are provided, the start instruction data and the stop instruction data correspond to each of the plurality of heaters. Prepared.

  The error output selection circuit 108 includes detection signals output from various detection elements (sensors) 111 that monitor the state of the element substrate mounted on the element substrate 101 in a selection instruction input from the controller 600 of the printing apparatus. The detection element selection data is selected. The selected detection signal is output as error information ERROR from the error information output terminal 216 to the controller 600 of the recording apparatus.

  As shown in FIG. 9, the temperature detection circuit 106, the temperature control circuit 107, and the error output selection circuit 108 are provided with shift registers 209, 211, and 213 and latch circuits 210, 212, and 214, respectively. Similarly to the recording element selection circuit 103, the reset signal RST5 reflecting the error detection result RST2 is input to the shift registers 209 and 211 of the temperature detection circuit 106 and the temperature control circuit 107. As a result, the shift registers 209 and 211 are reset upon a transfer error.

  Since the temperature detection circuit 106 detects temperature information from a plurality of temperature detection elements 109, when a transfer error occurs, it cannot be determined from which temperature detection element the temperature information is transferred. However, since the temperature detection circuit 106 in this embodiment includes the shift register 209, the temperature information TEMP is fixed to a specific signal level when the content is reset by the reset signal RST5 reflecting the error detection result RST2. So that Thus, when the controller 600 of the recording apparatus receives the temperature information TEMP at the specific level, it is determined that the output is clearly abnormal, and the controller 600 of the recording apparatus does not use the temperature information.

  Further, when the recording head 3 is mounted with a plurality of element substrates, the temperature information TEMP is bundled and output from each of the plurality of element substrates to one signal line in order to reduce the number of terminals of the recording head. There is. In such a configuration, by setting the output of the temperature information TEMP from the element substrate including the reset shift register to be OPEN, it is possible to avoid logic collision due to the output of each of the plurality of element substrates. it can.

  The contents of the shift register 211 of the temperature control circuit 107 are reset to the value of the stop instruction data by the reset signal RST5 reflecting the error detection result RST2. When the latch signal is input, the stop instruction data is latched in the latch circuit 212. For this reason, when the recording device transmits a temperature control instruction signal for stopping temperature control, even if the transmission results in a transfer error, the contents of the shift register 211 are reset and the temperature control is forcibly stopped. can do. This makes it possible to prevent unexpected temperature control.

  On the other hand, the shift register 213 and the latch circuit 214 of the error output selection circuit 108 have the same input configuration as that of the drive time generation circuit 104. Further, in the error output selection circuit 108, when there are a plurality of types of error signals corresponding to various detection elements provided on the element substrate 101, the selected error signal is used to reduce the number of output terminals from the element substrate 101. Only output. The shift register 213 and the latch circuit 214 hold a selection instruction signal (detection element selection data) which is received from the controller 600 of the printing apparatus and selects which detection element.

  For this reason, if the shift register 213 is reset by the reset signal RST5 reflecting the error detection result RST2 as in the temperature detection circuit 106 and the temperature control circuit 107, the selected error information cannot be output. End up. Therefore, as in the drive time generation circuit 104, the NAND operation result signal of the data presence / absence identification result RST1 and the latch signal RST3 reflecting the error detection result RST2 is used to reset the latch circuit 214. Thus, even when a transfer error occurs, the previously latched data can be used, and the selected error information is continuously output.

  Therefore, according to the embodiment described above, even when a transfer error from the printing apparatus to the element substrate occurs, signal output and control can be individually executed according to the role of the functional circuit. For example, the shift registers of some functional circuits can be reset by a reset signal that reflects the error detection result, and the latch circuits of the remaining functional circuits can be latched by a latch signal that reflects the error detection result become.

101 element substrate, 102 data receiving circuit, 103 recording element selection circuit,
104 drive time generation circuit, 105 drive circuit, 106 temperature detection circuit,
107 temperature control circuit, 108 error output selection circuit,
201 data identification circuit, 202 error detection circuit, 203 shift register,
204 latch circuit, 205 shift register, 206 latch circuit,
207 latch circuit, 208, 209, 211, 213 shift register,
210, 212, 214 Latch circuit, 215 Temperature information output terminal,
216 Error information output terminal

Claims (20)

An element substrate on which a plurality of recording elements and a plurality of driving elements for driving the plurality of recording elements are mounted,
A plurality of functional circuits that respectively execute a plurality of functions necessary for executing a recording operation;
Receives a data signal from the outside, identifies the type of data included in the received data signal, and transfers the received data signal to a corresponding functional circuit among the plurality of functional circuits according to the identification result A data identification circuit for
An error detection circuit that receives the data signal and detects whether a transfer error has occurred in the received data signal;
Reflecting the detection result of the error detection circuit in the latch signal received from the outside and the reset signal received, and for some of the plurality of functional circuits according to the function performed by each of the plurality of functional circuits Causes the transferred data signal to be latched by a latch signal reflecting the detection result, and for the remaining functional circuits of the plurality of functional circuits, the transfer is performed by a reset signal reflecting the detection result. And a control circuit for controlling the resetting of the generated data signal. Each of the plurality of functional circuits is
A shift register for holding the received data signal transferred from the data identification circuit;
A latch circuit that latches the data signal held by the shift register,
The shift register is reset by the received reset signal or a reset signal reflecting the detection result,
The element substrate according to claim 1, wherein the latch circuit performs latching by the received latch signal or a latch signal reflecting the detection result. The data signal includes a first data signal that selects a recording element and a second data signal that defines a driving time;
The plurality of functional circuits are:
A selection circuit that selects a recording element to be driven from the plurality of recording elements based on the first data signal;
A generating circuit that generates a driving time of the recording element to be driven based on the second data signal;
The shift register of the selection circuit is reset by a reset signal reflecting the detection result,
The element substrate according to claim 2, wherein the latch circuit of the generation circuit performs latching by a latch signal in which the detection result is reflected. The control circuit includes a latch circuit that latches the received latch signal and the detection result,
4. The element substrate according to claim 3, wherein the latch circuit of the selection circuit is further reset based on a latch signal reflecting the detection result latched in the latch circuit of the control circuit.   2. The control circuit according to claim 1, wherein the control circuit outputs and stops a latch signal to some of the plurality of functional circuits based on an error detection result by the error detection circuit. Element substrate. The plurality of functional circuits further includes
Based on an instruction received from the outside, a temperature detection circuit that outputs temperature information detected from the temperature detection element mounted on the element substrate to the outside, and
A temperature control circuit for controlling the temperature of the element substrate by driving a heater mounted on the element substrate based on an instruction received from the outside;
An error output selection circuit that selects one of detection signals from a plurality of detection elements mounted on the element substrate based on a selection instruction received from the outside, and outputs the selected detection signal as an error signal. The element substrate according to claim 2, wherein the element substrate is provided. The shift register of the temperature detection circuit and the shift register of the temperature control circuit are reset by a reset signal reflecting the detection result,
The element substrate according to claim 6, wherein the latch circuit of the error output selection circuit performs latching by a latch signal in which the detection result is reflected. It has multiple input terminals that receive data signals according to the type of data signal,
8. The element substrate according to claim 1, comprising a plurality of data identification circuits and a plurality of error detection circuits, respectively, according to the type. 9. The plurality of recording elements are time-division driven by the plurality of driving elements,
In the control circuit, the transferred data signal is latched by a latch signal in which the detection result is reflected according to data updated and data not updated every block period in the time-division driving, 9. The element substrate according to claim 1, wherein the transferred data signal is reset by a reset signal in which a detection result is reflected.   A recording head comprising the element substrate according to claim 1.   The recording head according to claim 10, wherein the recording head is an inkjet recording head. A recording head according to claim 10 or claim 11,
A recording apparatus comprising: a controller that transfers a data signal, a latch signal, and a reset signal to the recording head in order to perform recording on a recording medium using the recording head. A first receiving terminal for receiving a data signal;
A second receiving terminal for receiving a latch signal;
A third receiving terminal for receiving a reset signal;
A plurality of recording elements;
A plurality of drive elements for driving the plurality of recording elements;
An identification circuit for identifying the type of data included in the data signal received at the first receiving terminal;
An error detection circuit for detecting whether a transfer error has occurred in the data signal;
Each has a shift register that holds data included in the data signal and a latch circuit that latches data held by the shift register, and each has a plurality of functions necessary for driving the plurality of driving elements. Multiple functional circuits to execute;
A transfer circuit that transfers the received data signal to a corresponding functional circuit of the plurality of functional circuits according to the identification result of the identification circuit;
Based on the latch signal received at the second reception terminal and the error detection result by the error detection circuit, a first control is performed to control whether or not a latch signal is output to some of the plurality of functional circuits. A control circuit of
When the reset signal is received at the third receiving terminal, the reset signal is transferred to the remaining functional circuits of the plurality of functional circuits, and the error is detected when the reset signal is not received at the third receiving terminal. And a second control circuit that generates a reset signal when a circuit error is detected and transfers the reset signal to the remaining functional circuits among the plurality of functional circuits.   When the error detection circuit detects the occurrence of an error, the first control circuit stops transfer to some of the plurality of functional circuits even when the latch signal is received. The recording head according to claim 13. The identification circuit further identifies the presence / absence of reception of a predetermined type of data, and if the predetermined type of data is not received, performs notification to the first control circuit,
The recording head according to claim 13, wherein the first control circuit stops outputting the latch signal to the functional circuit even if the latch signal is received based on the notification. The data signal includes first data for selecting a recording element and second data for defining a driving time;
A part of the plurality of functional circuits includes a selection circuit that selects a recording element to be driven from the plurality of recording elements based on the first data;
14. The recording head according to claim 13, wherein the remaining functional circuits of the plurality of functional circuits include a generation circuit that generates a driving time of the recording element to be driven based on the second data. The plurality of functional circuits further includes
A temperature detection circuit that outputs temperature information detected by a temperature detection element mounted on the element substrate of the recording head; and
A temperature control circuit for controlling the temperature of the element substrate by driving a heater mounted on the element substrate of the recording head;
An error output selection circuit that selects any one of detection signals from a plurality of detection elements mounted on the element substrate of the recording head and outputs the selected detection signal as an error signal. The recording head according to claim 13. The recording element selected by the selection circuit is time-division driven,
The recording head according to claim 16, wherein the element substrate of the recording head receives the data signal and the latch signal for each block period in the time-division driving. A recording head according to any one of claims 13 to 18,
A recording apparatus comprising: a controller that transfers a data signal, a latch signal, and a reset signal to the recording head in order to perform recording on a recording medium using the recording head.   The recording apparatus according to claim 19, wherein the recording head is an inkjet recording head.

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