JP2010044480A - Hardware reset method for control circuit, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose a hardware reset method for a control circuit, allowing a hardware reset based on a reset instruction even when operation when the reset instruction is issued is set to power-off operation of turning off a power supply by a manual changeover switch. <P>SOLUTION: The power-off operation is started when the reset instruction is issued when the dip switch 5 is set to the power-off operation, so that power supply voltage gradually falls. Here, when the issued reset instruction is a reset instruction issued by a CPU 3 itself, the hardware reset is executed. Before the power supply voltage during the fall reaches a prescribed value, the power supply voltage is made to return to an original value. As a result, the hardware reset of the CPU 3 can be performed without turning off the power supply. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  According to the present invention, an operation performed when one operation switch such as a power switch is operated is changed to one of a reset operation for performing a hardware reset of the control circuit and a power off operation for turning off the power. The present invention relates to a hardware reset method for a control circuit in an electronic device that can be set, and the electronic device.

  A power supply circuit of an electronic device such as a printer converts an AC voltage into a DC voltage, supplies 24 V to a drive system such as a motor, and supplies 5 V or 3.3 V to a control system such as a CPU. Since such a power supply circuit includes a capacitor for rectification and prevention of a drop in the power supply voltage, when the power supply is turned off by operating the power switch, the power supply voltage is The power supply is lowered over a certain period of time due to the capacitance included in the supply circuit, and then the power is turned off. Japanese Patent Application Laid-Open No. 2004-151561 describes a technique for discharging residual charges in a short time from a power supply circuit of such a power supply device. Patent Document 2 describes a technique for increasing the discharge time constant of such a power supply circuit.

Some information devices are configured so that a power-off operation for turning off the power and a reset operation for hardware resetting the control circuit can be selectively performed by operating a power switch. is there. For example, in the information device described in Patent Document 3, the power-off operation is performed when the power switch is pressed and the pressing is released within a predetermined time, and the reset operation is performed when the pressing is continued for a predetermined time or more. Is done.
JP 2007-202247 A Japanese Patent Application Laid-Open No. 07-144104 International Publication No. W02004 / 021154

  In an electronic device such as a printer, a device that sets an operation performed when a power switch is operated to one of a power-off operation and a reset operation by a manual changeover switch such as a dip switch has been proposed.

  In such a printer, when it is set so that the power-off operation is performed by the manual changeover switch, when the power switch is operated and a predetermined control command is issued, the power-off operation is performed and the power is turned off. Turns off. On the other hand, when it is set so that the reset operation is performed by the manual changeover switch, when the power switch is operated and a predetermined control command is issued, the reset operation is performed and the control circuit is hardware reset. The That is, the control command for instructing to turn off the power and the control command for instructing the hardware reset are the same predetermined control commands, and their operations are determined by the manual changeover switch.

  Here, when it is determined that an error that cannot be repaired has occurred in the control circuit, or when firmware has been updated in the memory, the control circuit issues a control command for instructing the hardware reset itself. May be issued. However, if the operation set with the manual selector switch is a power-off operation, the power-off operation will be performed even if the control circuit attempts to perform a hardware reset, so the reset operation cannot be performed. There is.

  In view of the above, the problem of the present invention is that the operation when a reset command (a control command by operating a power switch, a control command by which the control circuit instructs a hardware reset itself) is issued by a manual switch. A hardware reset method for a control circuit in an electronic device such as a printer capable of performing a hardware reset based on a reset command without turning off the power even when the power is set to be turned off. To propose electronic equipment.

In order to solve the above problems, the present invention provides a reset operation for performing a hardware reset and a power-off for turning off the power when a reset command for performing a hardware reset or power-off of a control circuit is issued. It can be set by a manual changeover switch so that either one of the operations is performed. When the power-off operation is performed, the power supply voltage drops over a certain period of time and the power is turned off. A hardware reset method for a control circuit in an electronic device,
When the reset command is issued,
Check the manual switch setting,
In the case where the power-off operation is set to be performed by the manual changeover switch, the power-off operation is started,
Determining whether the reset command is issued when a predetermined control command is input to the control circuit, or whether the control circuit is issued by itself;
When the control circuit issues the reset command itself, the reset operation is started before the power supply voltage that is dropping due to the power-off operation reaches a predetermined value, and the power supply voltage is It is characterized by returning to a value.

  According to the present invention, when the reset command is issued, the setting of the manual changeover switch is confirmed, and when the setting of the manual changeover switch is the power-off operation, the power-off operation is started. In addition, it is determined whether the reset command is issued when a predetermined control command is input to the control circuit, or is issued by the control circuit itself, and the reset command is issued by the control circuit itself. If it is, the reset operation is started. When the control circuit issues the reset command itself, the power supply voltage is returned to the original value before the power supply voltage that is dropping due to the power-off operation reaches a predetermined value. In other words, when the power is turned off, the power supply voltage gradually decreases over a certain period of time due to the capacitance contained in the power supply circuit of the electronic device, so the power supply voltage is reset to the control circuit by hardware. The power supply voltage is returned to the original value before becoming lower than a predetermined value necessary for performing the operation. As a result, a hardware reset can be performed without turning off the power, and the control circuit can be shifted to the initialized state. Therefore, if an unrecoverable error occurs in the control circuit or if a firmware update is performed, etc., if a reset command is issued due to a request from the control circuit, the hardware will not be affected regardless of the manual switch setting. Wear reset can be performed.

Further, the present invention is a hardware reset method for a control circuit that starts turning off a power supply when a reset command is issued,
When the control circuit issues the reset command itself, or when a predetermined setting is made,
A hardware reset of the control circuit is started and the voltage of the power supply is restored after the power supply is turned off and before the voltage of the power supply being lowered reaches a predetermined value.

  According to the present invention, when a reset command is issued, power off is started. In addition, when the reset command is issued by the control circuit itself or when a predetermined setting is made, the reset operation is started before the power supply voltage dropping due to power-off reaches a predetermined value. In addition, the power supply voltage is restored to the original value. When the power is turned off, the power supply voltage gradually decreases over a predetermined time due to the electrostatic capacity component included in the control circuit and the substrate. At this time, during the period until the power supply voltage drops to the lower limit value of the operating voltage of the control circuit, it is possible to control the power supply voltage to the original value while continuing the operation of the control circuit. If a hardware reset is performed during this period, the hardware reset can be performed without completely turning off the power. In other words, it is originally a reset command for powering off the control circuit, but it is possible to perform a hardware reset while maintaining a voltage that allows the control circuit to operate continuously without completely turning off the power. it can. Both power off and hardware reset are possible.

  The case where the control circuit issues itself is when a signal that triggers a hardware reset is generated by an instruction of the control circuit after a firmware or data rewrite in the memory or when a memory error occurs. It is. The predetermined setting can be set with a dip switch, a memory switch, or the like.

  In the present invention, the predetermined control command may be input as a command from a connected external device as a command, but the predetermined control command is input to the control circuit by manually operating an operation switch. Can be.

  In the present invention, in order to recognize that the hardware reset has been performed after the control circuit shifts to the initialization state, when it is determined that the control circuit is issuing the reset command itself, When the determination result is written in the nonvolatile memory and the power supply voltage returns to the original value, it is desirable to read the determination result from the nonvolatile memory and maintain the power supply voltage based on the determination result. In this way, since the power supply voltage is maintained, the electronic device can be used after the hardware reset is completed.

Next, the present invention provides either one of a reset operation for performing the hardware reset and a power off operation for turning off the power when a reset command for performing hardware reset or power off of the control circuit is issued. The electronic device can be set by a manual changeover switch so that the power is turned off, and when the power-off operation is performed, the power supply voltage drops over a certain time and the power is turned off. ,
When the reset command is issued,
Setting confirmation means for confirming the setting of the manual selector switch;
Power off means for performing the power off operation based on the reset command when the manual switch is set to perform the power off operation;
Determining means for determining whether the reset command is issued when a predetermined control command is input to the control circuit, or whether the control circuit is issued by itself;
When the manual changeover switch is set to perform the reset operation, or when the control circuit issues the reset command itself, a reset unit that performs the reset operation based on the reset command;
When the control circuit issues the reset command by itself when it is set to perform the power-off operation by the manual changeover switch, the power supply voltage that is dropping due to the power-off operation reaches a predetermined value. And a return means for returning the power supply voltage to the original value.

  According to the present invention, when the reset command is issued, the setting confirmation means confirms the setting of the manual changeover switch, and when the setting of the manual changeover switch is the power-off operation, the power-off means performs the power-off operation. Be started. Further, it is determined by the determining means whether the reset command is issued when a predetermined control command is input to the control circuit, or is issued by the control circuit itself, and the reset command is issued by the control circuit itself. If issued, the reset operation is started by the reset means. Then, when the control circuit issues the reset command itself, the return means returns the power supply voltage to the original value before the power supply voltage that is dropping due to the power-off operation reaches a predetermined value. In other words, when the power is turned off, the power supply voltage gradually decreases over a certain period of time due to the capacitance contained in the power supply circuit of the electronic device, so the power supply voltage is reset to the control circuit by hardware. The power supply voltage is returned to the original value before becoming lower than a predetermined value necessary for performing the operation. As a result, a hardware reset can be performed without turning off the power, and the control circuit can be shifted to the initialized state. Therefore, if an unrecoverable error occurs in the control circuit or if a firmware update is performed, etc., if a reset command is issued due to a request from the control circuit, the hardware will not be affected regardless of the manual switch setting. Wear reset can be performed.

The electronic device of the present invention is
A control circuit;
A power supply for supplying a voltage to the control circuit;
Reset command generating means for generating a reset command for hardware resetting the control circuit;
An electronic device comprising power control means for controlling on / off of the power,
When a reset command is input to the control circuit from the reset command generation means,
The control circuit, after outputting an off command to turn off the power to the power control means, starts its own hardware reset,
An on command to turn on the power is output to the power control means.

  According to the present invention, when a reset command is issued from the reset command generation unit, the power-off operation is started by the power control unit. Then, the reset operation is started. Before the power supply voltage that is dropping due to the power-off operation reaches a predetermined value, the power supply control means restores the power supply voltage to the original value. In other words, when the power is turned off, the power supply voltage gradually decreases over a certain period of time due to the capacitance contained in the power supply circuit of the electronic device, so the power supply voltage is reset to the control circuit by hardware. Before the value becomes lower than a predetermined value necessary for performing the operation, an on command to turn on the power is output to the power control means, and the power supply voltage is returned to the original value. As a result, a hardware reset can be performed without turning off the power, and the control circuit can be shifted to the initialized state. Therefore, a hardware reset can be performed when a reset command is issued in response to a request from the control circuit when an unrecoverable error occurs in the control circuit or when firmware is updated.

  In the present invention, although the predetermined control command may be input as a command from a connected external device as a command, an operation switch for inputting the predetermined control command to the control circuit by manual operation is provided. It is desirable that

  In the present invention, in order to recognize that the hardware reset has been performed after the control circuit shifts to the initialization state, the reset command is set when the manual switch is set to perform the power-off operation. When the control circuit determines that the control circuit has issued itself, the storage holding means for writing the determination result to the nonvolatile memory and the determination from the nonvolatile memory when the power supply voltage returns to the original value. It is desirable to provide a maintaining means for reading the result and maintaining the power supply voltage based on the determination result. In this way, since the power supply voltage is maintained, the electronic device can be used after the hardware reset is completed.

  According to the present invention, when the reset command is issued, the setting of the manual changeover switch is confirmed, and when the setting of the manual changeover switch is the power-off operation, the power-off operation is started. In addition, it is determined whether the reset command is issued when a predetermined control command is input to the control circuit, or is issued by the control circuit itself, and the reset command is issued by the control circuit itself. If it is, the reset operation is started. When the control circuit issues the reset command itself, the power supply voltage is returned to the original value before the power supply voltage that is dropping due to the power-off operation reaches a predetermined value. In other words, when the power is turned off, the power supply voltage gradually decreases over a certain period of time due to the capacitance contained in the power supply circuit of the electronic device, so the power supply voltage is reset to the control circuit by hardware. The power supply voltage is returned to the original value before becoming lower than a predetermined value necessary for performing the operation. As a result, a hardware reset can be performed without turning off the power, and the control circuit can be shifted to the initialized state. Therefore, if an unrecoverable error occurs in the control circuit or if a firmware update is performed, etc., if a reset command is issued due to a request from the control circuit, the hardware will not be affected regardless of the manual switch setting. Wear reset can be performed.

  Embodiments of an example of a printer in an electronic apparatus to which the present invention is applied will be described below with reference to the drawings.

  FIG. 1 is a schematic block diagram showing a power control unit mounted on a printer.

  A power supply control unit (control circuit) 1 controls a power supply circuit (power supply control means and power supply) 2 for supplying power to the printer, and is configured around a CPU 3. A power switch (operation switch) 4 and a dip switch (manual changeover switch) 5 are connected to the input side of the CPU 3. The CPU 3 has a reset output port 6 and a power supply control output port 7 as output ports. A reset IC 8 is connected to the reset output port 6, and the output of the reset IC 8 is input to the CPU 3. An OR circuit 9 is connected to the power control output port 7, and a signal from the DIP switch 5 is also input to the OR circuit 9. A power supply circuit 2 is connected to the output side of the OR circuit 9. The power supply circuit 2 converts AC voltage into DC voltage, supplies 24 V to a drive system such as a motor mounted on the printer, and supplies 3.3 V to a control system such as a CPU 3 (control circuit). To do.

  The CPU 3 includes a setting confirmation unit 10, a determination unit 11, a power-off unit 12, a reset unit 13, a return unit 14, a memory holding unit 15, and a maintaining unit 16. In addition, a nonvolatile memory 17 is connected to the CPU 3.

  The power switch 4 is a push button type switch. When the operator pushes the power switch 4, a predetermined signal (predetermined control command) is input to the CPU 3.

  The dip switch 5 sets the operation when the reset command is issued by the CPU 3 to one of a reset operation for performing a hardware reset of the CPU 3 and a power-off operation for turning off the power. When the DIP switch 5 is ON, the reset operation is set, and the DIP switch 5 outputs a HIGH state setting signal. When the DIP switch 5 is OFF, the power-off operation is set, and the DIP switch 5 outputs a setting signal for the LOW state.

  The setting confirmation means 10 confirms the setting by the dip switch 5 by detecting the signal input from the dip switch 5.

  The determination unit 11 determines whether the reset command is issued when a predetermined signal is input to the CPU 3 or is issued by the CPU 3 itself. That is, some reset commands are issued by the CPU 3 when the power switch 4 is operated and a predetermined signal is input to the CPU 3. In addition, there is a type in which a predetermined signal similar to that when the power switch 4 is operated by a command input from an external device is input to the CPU 3 and issued by the CPU 3 based on the predetermined signal. Furthermore, there are cases where the CPU 3 issues itself when it is determined that an unrecoverable error has occurred in the CPU 3 or when firmware has been updated. Here, it is known by the CPU 3 itself whether the reset command is issued when a predetermined signal is input to the CPU 3 or issued by the CPU 3 itself.

  The power-off means 12 performs the power-off operation based on the reset command when the setting of the dip switch 5 is the power-off operation. Since the CPU 3 outputs the PSC signal in the HIGH state from the power control output port 7 while the power supply to the printer is necessary, the CPU 3 sets the PSC signal to the LOW state when the power-off operation is started.

  The reset means 13 performs a reset operation based on the reset command when the setting of the dip switch 5 is a reset operation or when the CPU 3 issues a reset command by itself. That is, when a reset command is issued, the CPU 3 outputs a predetermined pulse (HIGH) MR signal from the reset output port 6. When the MR signal is input to the reset IC 8, the reset IC 8 inputs a RESET signal having a predetermined pulse (LOW) to the CPU 3. When the RESET signal is input to the CPU 3, the CPU 3 resets its own hardware. When the CPU 3 resets its own hardware, the HIGH state PSC signal output from the power control output port 7 changes to the LOW state as the CPU 3 is initialized.

  In the return means 14, when the setting of the dip switch 5 is the power-off operation, and the CPU 3 issues a reset command itself, the power supply voltage that is falling due to the power-off operation reaches a predetermined value. Before, the power supply voltage is restored to the original value. More specifically, before the power supply voltage reaches a predetermined value, the PSC signal that is in the LOW state by the power-off operation is set to the HIGH state. Here, the predetermined value is a voltage capable of continuing to supply 3.3V necessary for the operation to the logic circuit including the CPU 3, and is 9V in this example.

  When the setting of the DIP switch 5 is in the power-off operation, the memory holding unit 15 displays the determination result when the determination unit 11 determines that the CPU 3 has issued a reset command by itself. Write to. This writing is performed before the start of the power-off operation or while the power-supply voltage is dropping after the power-off operation is started.

  When the power supply voltage returns to the original value, the maintaining means 16 reads the determination result written in the nonvolatile memory 17 by the storage holding means 15 and maintains the power supply voltage based on this determination result. Specifically, the PSC signal output from the power control output port 7 is set to the HIGH state.

  FIG. 2 is an explanatory diagram showing the state of the voltage maintenance signal input from the OR circuit 9 to the power supply circuit 2. The OR circuit 9 outputs a HIGH state voltage maintenance signal when the DIP switch 5 is ON and a HIGH state setting signal is input from the DIP switch 5. Further, when a high-level PSC signal is output from the power supply control output port 7, a high-level voltage maintaining signal is output. While the HIGH voltage maintaining signal is input from the OR circuit 9 to the power supply circuit 2, the power supply circuit 2 maintains the power supply voltage. On the other hand, the OR circuit 9 is in the LOW state when the DIP switch 5 is OFF and the LOW state setting signal is output, and the power control output port 7 outputs the LOW state PSC signal. Outputs a voltage maintenance signal. When a voltage position signal in the LOW state is input from the OR circuit 9 to the power supply circuit 2, the power supply voltage is not maintained by the power supply circuit 2, and the power is turned off. Here, since the power supply circuit 2 includes a capacitor for rectification and prevention of a drop in the power supply voltage, the power supply voltage gradually decreases over a certain time due to the capacitance included in the power supply circuit 2. After that, the power is turned off.

(Reset operation when the DIP switch setting is reset)
FIG. 3 is a table showing the output state of each signal when the reset command is issued when the setting of the dip switch 5 is the reset operation.

  First, the DIP switch 5 is set to ON, and the HIGH state setting signal is input from the DIP switch 5 to the OR circuit 9. In a state before the reset command is issued, the MR signal is in the LOW state, the PSC signal is in the HIGH state, and the RESET signal is in the HIGH state. The voltage maintaining signal input from the OR circuit to the power supply circuit 2 is in a HIGH state, and the power supply voltage is maintained.

  When the power switch 4 is operated, a predetermined signal is input to the CPU 3 and a reset command is issued, or when the CPU 3 issues a reset command itself, the setting confirming means 10 confirms the setting of the dip switch 5. . Since the dip switch 5 is set to the reset operation, the reset operation is started. That is, the reset means 13 outputs an MR signal having a predetermined pulse (HIGH). Then, a RESET signal having a predetermined pulse (LOW) is input from the reset IC 8 to the CPU 3. As a result, the hardware reset of the CPU 3 is performed. Further, the PSC signal changes to the LOW state.

  Here, even if the PSC signal changes to the LOW state, since the HIGH state setting signal is input from the DIP switch 5 to the OR circuit 9, the HIGH state voltage maintaining signal is input to the power supply unit. Therefore, the reset operation is performed without turning off the power.

(Power off operation when the DIP switch setting is set to power off)
FIG. 4 is a table showing the output state of each signal when a reset command is issued by inputting a predetermined signal to the CPU 3 when the setting of the dip switch 5 is the power-off operation.

  First, the dip switch 5 is set to OFF, and a LOW state setting signal is input to the OR circuit 9 from the dip switch 5. In a state before the reset command is issued, the MR signal is in the LOW state, the PSC signal is in the HIGH state, and the RESET signal is in the HIGH state. The voltage maintaining signal input from the OR circuit to the power supply circuit 2 is in a HIGH state, and the power supply voltage is maintained.

  When a predetermined signal is input to the CPU 3 by operating the power switch 4 or the like and a reset command is issued by the CPU 3, the setting confirmation means 10 confirms the setting of the dip switch 5. Since the power-off operation is set in the dip switch 5, the power-off means 12 starts the power-off operation. That is, the PSC signal is set to the LOW state. Note that the MR signal remains in the LOW state and the RESET signal also remains in the HIGH state, and neither generates a pulse.

  Here, when the PSC signal is in the LOW state, the LOW state setting signal is also input to the OR circuit 9 from the DIP switch 5, and therefore the LOW state voltage maintaining signal is input to the power supply unit. Accordingly, the power supply voltage is not maintained by the power supply circuit 2 and the power supply is turned off.

(Reset operation when the DIP switch is set to power off)
A reset operation when the CPU 3 issues a reset command by itself when the setting of the dip switch 5 is the power-off operation will be described. FIG. 5 is a flowchart showing the reset operation. FIG. 6 is a table showing the output state of each signal. FIG. 7 is a timing chart during a hardware reset after a reset command is issued.

  First, the dip switch 5 is set to OFF, and a LOW state setting signal is input to the OR circuit 9 from the dip switch 5. In a state before the reset command is issued, the MR signal is in the LOW state, the PSC signal is in the HIGH state, and the RESET signal is in the HIGH state. The voltage maintaining signal input from the OR circuit to the power supply circuit 2 is in a HIGH state, and the power supply voltage is maintained.

  When a reset command is issued by the CPU 3 (step ST1), the setting confirmation means 10 confirms the setting of the dip switch 5 (step ST2). Further, the determination unit 11 determines whether the reset command is issued when a predetermined signal is input to the CPU 3 or issued by the CPU 3 itself (step ST3). Since it is determined that this reset command is issued by the CPU 3 itself, the determination result is written in the nonvolatile memory 17 by the memory holding means 15 (step ST4).

  Here, since the power-off operation is set in the dip switch 5, the power-off means 12 starts the power-off operation (step ST5). When the power off operation is started, the PSC signal becomes LOW. When the PSC signal is in the LOW state, the LOW state setting signal is also input from the DIP switch 5 to the OR circuit 9, and therefore the LOW state voltage maintaining signal is input to the power supply unit. Therefore, the power supply voltage is not maintained by the power supply circuit 2, and the power supply voltage gradually decreases from 24V as shown in FIG.

  Further, since the reset command is issued by the CPU 3 itself, the reset means 13 starts the reset operation (step ST6). When the reset operation is started, the reset means 13 outputs an MR signal having a predetermined pulse (HIGH). Then, a RESET signal having a predetermined pulse (LOW) is input from the reset IC 8 to the CPU 3. As a result, the hardware reset of the CPU 3 is performed. The PSC signal is maintained in the LOW state.

  Here, before the power supply voltage drops to a predetermined value of 9 V, the return means 14 returns the PSC signal from the LOW state to the HIGH state (step ST7). As a result, a HIGH state PSC signal is input to the OR circuit 9, so that a HIGH state power supply maintenance signal is input from the OR circuit 9 to the power supply circuit 2. Therefore, the power supply circuit 2 maintains the power supply voltage, and the power supply voltage rises and returns to the original value as shown in FIG.

  When the hardware reset is completed (step ST8), the CPU 3 has shifted to the initialization state. Therefore, the MR signal is in the LOW state, the PSC signal is in the LOW state, the RESET signal is in the HIGH state, and the voltage maintenance signal input from the OR circuit to the power supply circuit 2 is in the LOW state. The logic circuit including the CPU 3 is supplied with 3.3V.

  Here, when the power supply voltage returns to the original value, the return means 14 reads the determination result from the nonvolatile memory 17 (step ST9). Further, since the CPU 3 has issued a reset command by the read determination result, it can be confirmed that the hardware reset has been performed (step ST10), so that the PSC signal is set to the HIGH state (step ST11). . As a result, the power supply voltage is maintained by the power supply circuit 2.

  In step ST2, when the setting of the dip switch 5 is the reset operation, the reset operation is performed (step ST12). If a reset command is issued by inputting a predetermined signal to the CPU 3 in step ST3, a power-off operation is performed (step 13).

  Further, in the printer of this example, when the setting of the dip switch 5 is the power-off operation, the power is turned on when the power switch 4 is not pushed in for more than 5 seconds when the power is turned on. I can't do it. For this reason, when it is not confirmed in step ST10 that the CPU 3 has issued the reset command itself, the setting of the dip switch 5 is confirmed (step ST14).

  In step ST14, when the setting of the dip switch 5 is the power-off operation, the power switch push-in time is confirmed (step ST15). When the power switch push-in time exceeds 5 seconds, the PSC signal is set to the HIGH state (step ST11), and the power supply voltage is maintained. If the setting of the dip switch 5 is reset in step ST14, the process proceeds to step ST11 where the PSC signal is set to the HIGH state and the power supply voltage is maintained.

(Effects of this embodiment)
As described above, according to this example, when the reset command is issued, the setting of the dip switch 5 is confirmed, and when the setting of the dip switch 5 is the power-off operation, the power-off operation is started. If the reset command is issued when a predetermined signal is input to the CPU 3 or issued by the CPU 3 itself, the reset command is issued by the CPU 3 itself. The reset operation is started. When the CPU 3 issues a reset command itself, the power supply voltage is returned to the original value before the power supply voltage that is dropping due to the power-off operation reaches a predetermined value. That is, when the power-off operation is performed, the power supply voltage gradually decreases over a certain time due to the capacitance included in the power supply circuit 2 of the printer, so that the power supply voltage causes the CPU 3 to perform a hardware reset. It returns to the original value before it becomes lower than the predetermined value required for the above. As a result, a hardware reset can be performed without turning off the power, so that the CPU 3 can be shifted to the initialized state. Therefore, when an unrecoverable error occurs in the CPU 3 or when firmware is updated, a hardware reset is issued regardless of the setting of the DIP switch 5 when a reset command is issued in response to a request from the CPU 3. It can be performed.

  Further, according to this example, when it is determined that the power-off operation is set by the DIP switch 5, when it is determined that the CPU 3 issues the reset command itself, the determination result is non-volatile. When the data is written in the memory 17 and the power supply voltage returns to the original value, the determination result is read from the nonvolatile memory 17. Therefore, the CPU 3 can recognize that the hardware reset has been performed after the CPU 3 shifts to the initialization state based on the determination result written in the nonvolatile memory 17. In addition, since the power supply voltage is maintained based on the determination result read from the nonvolatile memory 17, the printer can be used after the hardware reset is completed.

It is a schematic block diagram which shows the power supply control part mounted in the printer. It is a table | surface which shows the state of the voltage maintenance signal input into a power supply circuit from an OR circuit. It is a table | surface which shows the output state of each signal when a reset instruction | command is issued. It is a table | surface which shows the output state of each signal when a reset instruction | command is issued. It is a flowchart when a hardware reset is performed. It is a table | surface which shows the output state of each signal when a hardware reset is performed. It is a timing chart when a hardware reset is performed.

Explanation of symbols

1. Power supply control unit 2. Power supply circuit 3. CPU (control circuit) 4. Power switch (operation switch) 5. Dip switch (manual changeover switch) 6. Reset output port 7. Power control Output port, 8 · reset IC, 9 · OR circuit, 10 · setting confirmation means, 11 · determination means, 12 · power off means, 13 · reset means, 14 · return means, 15 · memory retention means, 16 · maintenance Means, 17. Nonvolatile memory

Claims (8)

When a reset command for issuing a hardware reset or power off of the control circuit is issued, one of the reset operation for performing the hardware reset and the power off operation for turning off the power is performed. This is a hardware reset method for a control circuit in an electronic device that can be set by a manual changeover switch, and when the power-off operation is performed, the power supply voltage drops over a certain time and the power is turned off. And
When the reset command is issued,
Check the manual switch setting,
In the case where the power-off operation is set to be performed by the manual changeover switch, the power-off operation is started,
Determining whether the reset command is issued when a predetermined control command is input to the control circuit, or whether the control circuit is issued by itself;
When the control circuit issues the reset command itself, the reset operation is started before the power supply voltage dropping due to the power-off operation reaches a predetermined value, and the power supply voltage is restored to the original value. A hardware reset method for a control circuit, wherein the value is reset to a value. In the control circuit hardware reset method according to claim 1,
The control circuit hardware reset method, wherein the predetermined control command is input to the control circuit by manually operating an operation switch. In the hardware reset method of the control circuit according to claim 1 or 2,
If it is determined that the reset command is issued by the control circuit, the determination result is written in a nonvolatile memory.
When the power supply voltage returns to the original value, the determination result is read from the nonvolatile memory, and the power supply voltage is maintained based on the determination result. When a reset command for issuing a hardware reset or power off of the control circuit is issued, one of the reset operation for performing the hardware reset and the power off operation for turning off the power is performed. An electronic device that can be set by a manual changeover switch, and when the power-off operation is performed, the power supply voltage drops over a certain period of time and the power is turned off.
When the reset command is issued,
Setting confirmation means for confirming the setting of the manual selector switch;
Power off means for performing the power off operation based on the reset command when the manual switch is set to perform the power off operation;
Determining means for determining whether the reset command is issued when a predetermined control command is input to the control circuit, or whether the control circuit is issued by itself;
When the manual changeover switch is set to perform the reset operation, or when the control circuit issues the reset command itself, a reset unit that performs the reset operation based on the reset command;
When the control circuit issues the reset command by itself when it is set to perform the power-off operation by the manual changeover switch, the power supply voltage that is dropping due to the power-off operation reaches a predetermined value. An electronic device comprising: a return unit that previously returns the power supply voltage to the original value. In the electronic device according to claim 4,
An electronic device comprising an operation switch for inputting the predetermined control command to the control circuit by manual operation. The electronic device according to claim 4 or 5,
When it is determined that the power supply OFF operation is set by the manual changeover switch and the control circuit issues the reset command itself, the determination result is stored in the nonvolatile memory. Means,
An electronic apparatus comprising: a maintaining unit that reads the determination result from the nonvolatile memory and maintains the power supply voltage based on the determination result when the power supply voltage returns to the original value. A hardware reset method for a control circuit that starts turning off power when a reset command is issued,
When the control circuit issues the reset command itself, or when a predetermined setting is made,
A control circuit which starts a hardware reset of the control circuit and restores the voltage of the power supply before starting the power-off and before the voltage of the power supply being lowered reaches a predetermined value Hardware reset method. A control circuit;
A power supply for supplying a voltage to the control circuit;
Reset command generating means for generating a reset command for hardware resetting the control circuit;
An electronic device comprising power control means for controlling on / off of the power,
When a reset command is input to the control circuit from the reset command generation means,
The control circuit, after outputting an off command to turn off the power to the power control means, starts its own hardware reset and outputs an on command to turn on the power by the power control means. Electronic equipment.

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