JP2010028018A - Semiconductor wafer, semiconductor device, and method for manufacturing semiconductor device - Google Patents

Semiconductor wafer, semiconductor device, and method for manufacturing semiconductor device Download PDF

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JP2010028018A
JP2010028018A JP2008190897A JP2008190897A JP2010028018A JP 2010028018 A JP2010028018 A JP 2010028018A JP 2008190897 A JP2008190897 A JP 2008190897A JP 2008190897 A JP2008190897 A JP 2008190897A JP 2010028018 A JP2010028018 A JP 2010028018A
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Manabu Takei
学 武井
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer which suppresses the generation of a leak current due to a super junction structure exposed to a cutting plane, even when a stripe-like pattern in which the cutting plane of the super junction structure is exposed is equipped, in producing a semiconductor device as a single chip. <P>SOLUTION: The semiconductor wafer includes a super junction structure 5 which is arranged in stripe-like planar shape at equal intervals all over a semiconductor substrate 1 in the surface of the semiconductor substrate 1 of a first conductor type, and an arrangement in which a lattice-like pattern arranged using a semiconductor device dimension as a pitch interval is parallel or orthogonal to the pattern of the super junction structure 5, wherein the semiconductor device includes an MOS structure region, a withstanding voltage structure region 22 surrounding the relevant region, a lattice-like cutting region 18 arranged in the outermost periphery, and an etching groove 17 arranged along the relevant region, and the etching groove 17 includes a first conductor type surface layer 19 which covers a depth and an interior surface reaching the semiconductor substrate 1 from the surface of the super junction structure 5. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は超接合構造を備える電力用半導体装置に関し、特にはＳＪ−ＭＯＳＦＥＴに関する。   The present invention relates to a power semiconductor device having a superjunction structure, and more particularly to an SJ-MOSFET.

超接合構造（以降、ＳＪ構造と略記することもある）を利用して従来の特性限界を破るようなＭＯＳＦＥＴが開発されている。このＭＯＳＦＥＴの製造方法の主流である多段エピタキシャル方式（以降、多段エピ方式と略記することもある）は、高不純物濃度のｎ型半導体基板の表面にエピタキシャル層を多数回に分けて成長させる。各成長段階の前にパターニングおよびイオン注入によって、前記半導体基板の主面に垂直方向に薄層状または柱状のｐ型層およびｎ型層を形成する。このｐ型層およびｎ型層が、主面に平行な方向では前記ｐ型層とｎ型層が交互に繰り返し隣接するように、ｐｎ層の並列構造またはコラム構造を形成するという製造方法である。ｐｎ層のコラム構造の平面パターン（セル状パターンということもある）は、たとえばｎ型層中に複数の円または矩形状のｐ型層を所定の間隔で配置される構成を有し、ｐｎ層の並列構造の平面パターンは複数のストライプ状のｐ型層とｎ型層が、相互に平行で、交互に隣接して配置される構成となる。   MOSFETs have been developed that use a superjunction structure (hereinafter sometimes abbreviated as SJ structure) to break the conventional characteristic limit. In the multi-stage epitaxial method (hereinafter sometimes abbreviated as multi-stage epi method), which is the main method of manufacturing the MOSFET, an epitaxial layer is grown on the surface of a high impurity concentration n-type semiconductor substrate in a number of times. Prior to each growth step, thin or columnar p-type and n-type layers are formed in the direction perpendicular to the main surface of the semiconductor substrate by patterning and ion implantation. In this manufacturing method, the p-type layer and the n-type layer form a parallel structure or a column structure of pn layers so that the p-type layer and the n-type layer are alternately and repeatedly adjacent in a direction parallel to the main surface. . The planar pattern (sometimes referred to as a cellular pattern) of the column structure of the pn layer has a configuration in which, for example, a plurality of circular or rectangular p-type layers are arranged at predetermined intervals in the n-type layer, and the pn layer The plane pattern of the parallel structure is configured such that a plurality of striped p-type layers and n-type layers are arranged in parallel and alternately adjacent to each other.

一方、近年になって製造コストを安くすることが可能であるトレンチ埋め込みエピタキシャル方式（以降、トレンチ埋め込みエピ方式と略記）が開発されている。この方式は高不純物濃度のｎ型半導体基板（以降、高濃度ｎ型基板と略記）の表面にｎ型エピタキシャル層を成長させたウエハを材料とし、このウエハの表面から、ｎ型エピタキシャル層を貫き、前記高濃度ｎ型基板に達するような高アスペクト比のトレンチを所定の間隔で異方性エッチングにより形成（場合によっては完全には貫通せず、基板に到達しなくても良い）する。その後、このトレンチ内にｐ型エピタキシャル層を成長させることによりトレンチを完全に埋め込み、前述の多段エピ方式と同様のｐｎ層の並列構造またはコラム構造からなるＳＪ構造を形成する方式である。   On the other hand, recently, a trench buried epitaxial method (hereinafter abbreviated as a trench buried epi method) has been developed that can reduce the manufacturing cost. This method uses a wafer obtained by growing an n-type epitaxial layer on the surface of a high impurity concentration n-type semiconductor substrate (hereinafter abbreviated as a high concentration n-type substrate), and penetrates the n-type epitaxial layer from the surface of the wafer. Then, trenches having a high aspect ratio that reach the high-concentration n-type substrate are formed by anisotropic etching at a predetermined interval (in some cases, they do not penetrate completely and may not reach the substrate). Thereafter, a p-type epitaxial layer is grown in the trench to completely fill the trench, and an SJ structure having a parallel structure of pn layers or a column structure similar to the above-described multi-stage epi system is formed.

また、ウエハ表面に前述のｐｎ層の並列構造またはコラム構造からなるＳＪ構造を配置する平面的なレイアウトに、大きく分けて２つの方法がある。一（前者）の方法は、ウエハ内に繰り返し複数格子状に配置される半導体チップ毎に、前記ｐｎ層の並列構造またはコラム構造からなるＳＪ構造を分離独立させて配置する方法であり、他（後者）の方法はウエハ内に配置される半導体チップの大きさおよび位置に関係なく、ウエハ内の全面に前記ｐｎ層の並列構造またはコラム構造からなるＳＪ構造を連続的に配置する方法である。これらのいずれの方法についても、通常、ウエハへのＳＪ構造のパターン配置はウエハの最下部に配置されるオリエンテーションフラット（通称オリフラ）に対して直交または平行になるように行われるので、前記ｐｎ層の並列構造のストライプパターンは前記オリフラに対しては直交または平行にされる。前記半導体チップの配置パターンについても、前記オリフラと前記半導体チップの格子状配置パターンとは相互に直交または平行にされる。従って、前者の方法は前記オリフラに平行な方向と直角な方向の両方にパターン合わせが必要となるため、アライメントマーカーを別途ウエハ表面に設けておく必要がある。後者の方法では、相互のパターンが斜交することは無いので、前記ｐｎ層の並列構造のストライプパターンに対して半導体チップのＭＯＳ構造のパターンを平行ではなく直交するように配置させれば、マスク合わせが不要になるという特徴を有する。   In addition, there are roughly two methods for the planar layout in which the above-described parallel structure of pn layers or the SJ structure having a column structure is arranged on the wafer surface. One (the former) method is a method in which an SJ structure composed of a parallel structure or a column structure of the pn layers is arranged separately and independently for each semiconductor chip repeatedly arranged in a plurality of lattices in a wafer. The latter method is a method in which the SJ structure composed of the parallel structure of the pn layers or the column structure is continuously disposed on the entire surface of the wafer regardless of the size and position of the semiconductor chips disposed in the wafer. In any of these methods, the pattern layout of the SJ structure on the wafer is usually performed so as to be orthogonal or parallel to an orientation flat (commonly referred to as an orientation flat) disposed at the bottom of the wafer. The stripe pattern of the parallel structure is orthogonal or parallel to the orientation flat. Regarding the arrangement pattern of the semiconductor chip, the orientation flat and the lattice arrangement pattern of the semiconductor chip are made orthogonal or parallel to each other. Therefore, since the former method requires pattern alignment in both a direction parallel to the orientation flat and a direction perpendicular to the orientation flat, it is necessary to separately provide an alignment marker on the wafer surface. In the latter method, since the mutual patterns do not cross each other, if the MOS structure pattern of the semiconductor chip is arranged not to be parallel but orthogonal to the stripe pattern of the parallel structure of the pn layer, the mask The feature is that alignment is not necessary.

前述のように、ｐｎ層のコラム構造をウエハ全面に形成すると共に、このｐｎ層のコラム構造を、半導体チップを構成する半導体層の一部として用い、同時に、前記半導体チップをウエハ内に格子状に複数繰り返し配置する製造方法とすることにより、ｐｎ層のコラム構造の平面パターンと半導体チップの表面層に形成されるＭＯＳ構造との正確なマーカーを用いるパターン合わせを不要にする方法については既に公開されている（特許文献１）。また、ｐｎ層のコラム構造をウエハ全面に形成すると共に、半導体チップを高耐圧で使用できるように、半導体チップの周辺耐圧構造部には活性領域よりも高い濃度で、しかも拡散係数の大きいセレン、硫黄などのｎ型ドーパントによるイオン注入を行う製造方法が知られている。すなわち、周辺耐圧構造部のｐ型層を、ｎ型ドーパントの補償作用によって活性領域部内のｐ層よりもいっそう強く補償して高抵抗にすることにより高耐圧が得られるようにする製造方法である（特許文献２、３）。
特開２００４−３５６５７７号公報 特表２００３−５２９２０４号公報 特表２０００−５０４８７９号公報 As described above, the column structure of the pn layer is formed on the entire surface of the wafer, and the column structure of the pn layer is used as a part of the semiconductor layer constituting the semiconductor chip, and at the same time, the semiconductor chip is latticed in the wafer. A method of eliminating the need for pattern matching using a precise marker between the planar pattern of the column structure of the pn layer and the MOS structure formed on the surface layer of the semiconductor chip by using a manufacturing method in which a plurality of layers are repeatedly arranged on the surface has already been disclosed. (Patent Document 1). In addition, a pn layer column structure is formed on the entire surface of the wafer, and the peripheral breakdown voltage structure of the semiconductor chip has a higher concentration than the active region and a large diffusion coefficient so that the semiconductor chip can be used at a high breakdown voltage. A manufacturing method for performing ion implantation with an n-type dopant such as sulfur is known. That is, this is a manufacturing method in which a high breakdown voltage can be obtained by compensating the p-type layer of the peripheral breakdown voltage structure portion more strongly than the p-layer in the active region portion by the compensation action of the n-type dopant to increase the resistance. (Patent Documents 2 and 3).
Japanese Patent Laid-Open No. 2004-356577 Special table 2003-529204 gazette Special Table 2000-504879

前述した通常の多段エピ方式およびトレンチ埋込みエピ方式のいずれのＳＪ構造の製造方式においても、製造する半導体のチップサイズに合わせて、チップ毎に分離および独立したＳＪ構造を形成する場合は、チップ間の切断領域にはＳＪ構造が形成されないようになっている。このように、切断領域にＳＪ構造を形成しない理由は、半導体チップの主電流の流れる活性領域とチップの周辺に設けられ耐圧を保持するための表面領域である周辺耐圧構造部のＳＪ構造を個別に設計することができ、設計の自由度が向上するからである。また、ストライプ状の平面パターンを有するＳＪ構造においては、切断領域にＳＪ構造を形成しない平面パターンとすることにより、ウエハから半導体チップを切り出した後にも、ＳＪ構造のｐ型層が半導体チップの切断面に露出しなくなるので、この切断に起因する漏れ電流の発生を防ぐことができるからである。   In any of the above-described ordinary multi-stage epi method and trench buried epi method, both of the SJ structures can be manufactured in accordance with the chip size of the semiconductor to be manufactured. The SJ structure is not formed in the cutting region. As described above, the reason why the SJ structure is not formed in the cut region is that the SJ structure of the active region where the main current flows in the semiconductor chip and the peripheral withstand voltage structure portion, which is a surface region provided around the chip for maintaining the withstand voltage, are individually provided. This is because the degree of freedom of design is improved. Further, in the SJ structure having the stripe-like planar pattern, the p-type layer having the SJ structure can be cut into the semiconductor chip even after the semiconductor chip is cut out from the wafer by forming the planar pattern in which the SJ structure is not formed in the cutting region. This is because it is not exposed to the surface, so that it is possible to prevent the occurrence of leakage current due to this cutting.

しかしながら、この場合、前述のトレンチ埋込みエピ方式ではＳＪ構造とＭＯＳ構造とを正確にアライメントマーカーを用いて位置合わせする必要がある。このためアライメント用のマーカーを別途形成する必要が生じるなど追加工程が必要になり、製造コストが増加するという問題がある。
また、前記特許文献１には、ウエハ全面にＳＪ構造を形成して正確なアライメントを不要にする方法が開示されている。一方、トレンチ埋め込みエピ方式においては、良好なエピタキシャル層の埋め込み性という観点では、ストライプ状平面パターンによるｐｎ層の並列構造が他の円または矩形状の平面パターンなどによるｐｎ層のコラム構造よりも優れている。しかし、ウエハ全面にストライプ状平面パターンを有するＳＪ構造を形成する場合、図５の半導体チップの周辺部の斜視断面図に示すように、ウエハから半導体チップをダイシングなどにより切り出す際に半導体チップの切断面にＳＪ構造の切断面が必ず露出する。前記図５の矢印で示すように、その切断の際にできる結晶欠陥に起因して、ドレイン電極２０からソース電極１５へ流れる漏れ電流が増大することが問題となる。その原因はダイシング後の半導体チップ側壁には切断により形成される結晶欠陥が残存していることと、前記側壁切断面を表面保護膜で覆って不活性化していないためである。従って、ウエハ全面に連続的にストライプ状トレンチの平面パターンを形成してｐｎ層の並列構造のＳＪ構造を形成するトレンチ埋め込みエピ方式はトレンチへの良好な埋め込み性と正確なアライメントを不要とする点で優れているが、半導体チップ切断面に起因する前述の漏れ電流の増大という問題を抱えている。 However, in this case, it is necessary to accurately align the SJ structure and the MOS structure using the alignment marker in the above-described trench buried epi method. For this reason, there is a problem that an additional process such as the necessity of separately forming an alignment marker is required, resulting in an increase in manufacturing cost.
Japanese Patent Application Laid-Open No. H10-228867 discloses a method of forming an SJ structure on the entire wafer surface and making accurate alignment unnecessary. On the other hand, in the trench buried epi method, the parallel structure of the pn layers based on the stripe-shaped planar pattern is superior to the column structure of the pn layer based on other circular or rectangular planar patterns from the viewpoint of good epitaxial layer embedding. ing. However, when an SJ structure having a striped planar pattern is formed on the entire surface of the wafer, the semiconductor chip is cut when the semiconductor chip is cut out from the wafer by dicing or the like, as shown in the perspective sectional view of the periphery of the semiconductor chip in FIG. The cut surface of the SJ structure is always exposed on the surface. As indicated by the arrows in FIG. 5, there is a problem that leakage current flowing from the drain electrode 20 to the source electrode 15 increases due to crystal defects formed at the time of cutting. This is because crystal defects formed by cutting remain on the side wall of the semiconductor chip after dicing, and the side wall cut surface is covered with a surface protective film and is not inactivated. Therefore, the trench buried epi method in which the planar pattern of the stripe-shaped trench is continuously formed on the entire surface of the wafer to form the SJ structure of the parallel structure of the pn layer does not require good burying property and accurate alignment in the trench. However, it has the problem that the leakage current increases due to the cut surface of the semiconductor chip.

本発明は、以上説明した点に鑑みてなされたものであり、本発明の目的は、半導体装置のチップ化の際に、チップの切断面に超接合構造の切断面が露出するストライプ状の平面パターンを備える半導体装置であっても、半導体チップの切断面に露出する超接合構造に起因する漏れ電流の発生を抑制することのできる半導体ウエハ、半導体装置およびその製造方法を提供することである。   The present invention has been made in view of the above-described points, and an object of the present invention is a striped plane in which a cut surface of a superjunction structure is exposed on a cut surface of a chip when a semiconductor device is formed into a chip. It is an object to provide a semiconductor wafer, a semiconductor device, and a method for manufacturing the same that can suppress the occurrence of leakage current caused by a superjunction structure exposed on a cut surface of a semiconductor chip even in a semiconductor device having a pattern.

特許請求の範囲の請求項１記載の発明によれば、第一導電型の半導体基板の主面上に設けられ、該主面に垂直方向であって薄層状の第一導電型層および第二導電型層が、前記主面に平行な方向では、ストライプ状平面形状であって交互に繰り返し隣接すると共に、前記半導体基板の全面に亘って等間隔で配置されている超接合構造と、該超接合構造の表面に半導体装置の縦横寸法をピッチ間隔として配置される該半導体装置の格子状パターンが前記超接合構造のストライプ状平面形状に平行および直交する配置を有し、該半導体装置が、前記超接合構造のストライプ状平面形状に直交するように表面層に配置されるストライプ状のＭＯＳ構造領域と該ＭＯＳ構造領域を取り巻く耐圧構造領域と最外周に格子状に配置される切断領域と該切断領域に沿って配置されるエッチング溝とを備え、該エッチング溝が前記超接合構造の表面から前記半導体基板に達する深さと、該エッチング溝の内面を覆う第一導電型表面層を備える半導体ウエハとすることにより、前記本発明の目的は達成される。   According to the first aspect of the present invention, the first conductive type layer and the second conductive layer which are provided on the main surface of the first conductive type semiconductor substrate and are perpendicular to the main surface and have a thin layer shape. A superjunction structure in which the conductive type layer has a stripe-like planar shape in a direction parallel to the main surface and is alternately adjacent to each other, and is disposed at equal intervals over the entire surface of the semiconductor substrate; The lattice pattern of the semiconductor device arranged on the surface of the junction structure with the vertical and horizontal dimensions of the semiconductor device as pitch intervals is parallel to and orthogonal to the stripe-like planar shape of the superjunction structure, Striped MOS structure region arranged on the surface layer so as to be orthogonal to the stripe-like planar shape of the superjunction structure, a breakdown voltage structure region surrounding the MOS structure region, a cutting region arranged in a grid pattern on the outermost periphery, and the cutting Territory And a depth of the etching groove reaching the semiconductor substrate from the surface of the superjunction structure, and a first conductivity type surface layer covering the inner surface of the etching groove. Thus, the object of the present invention is achieved.

特許請求の範囲の請求項２記載の発明によれば、前記エッチング溝の長手方向に直角方向の切断面がＶ字形である特許請求の範囲の請求項１記載の半導体ウエハとする。
特許請求の範囲の請求項３記載の発明によれば、前記エッチング溝の長手方向に直角方向の切断面がＵ字形である特許請求の範囲の請求項１記載の半導体ウエハとする。
特許請求の範囲の請求項４記載の発明によれば、第一導電型の半導体基板の主面上に設けられ、該主面に垂直方向であって薄層状の第一導電型層および第二導電型層が、前記主面に平行な方向では、ストライプ状平面形状であって交互に等間隔で繰り返し隣接する超接合構造と、該超接合構造の前記ストライプ状平面形状に直交するように表面層に配置されるストライプ状のＭＯＳ構造領域と該ＭＯＳ構造領域を取り巻く耐圧構造領域と最外周に配置される切断領域と該切断領域に沿って配置されるエッチング溝とを備え、該エッチング溝が前記超接合構造の表面から前記半導体基板に達する深さと、該エッチング溝の内面を覆う第一導電型表面層を備える半導体装置とすることにより、前記本発明の目的は達成される。 According to a second aspect of the present invention, the semiconductor wafer according to the first aspect of the present invention has a V-shaped cut surface perpendicular to the longitudinal direction of the etching groove.
According to a third aspect of the present invention, the semiconductor wafer according to the first aspect of the present invention has a U-shaped cut surface perpendicular to the longitudinal direction of the etching groove.
According to the invention of claim 4, the first conductive type layer and the second conductive layer which are provided on the main surface of the first conductive type semiconductor substrate and are perpendicular to the main surface and are thin layered. In a direction parallel to the main surface, the conductive type layer has a stripe-like planar shape, and is alternately adjacent to each other at equal intervals, and a superjunction structure that is perpendicular to the stripe-like planar shape of the superjunction structure. A striped MOS structure region disposed in the layer, a breakdown voltage structure region surrounding the MOS structure region, a cutting region disposed at the outermost periphery, and an etching groove disposed along the cutting region, The object of the present invention is achieved by providing a semiconductor device including a depth reaching the semiconductor substrate from the surface of the super junction structure and a first conductivity type surface layer covering the inner surface of the etching groove.

特許請求の範囲の請求項５記載の発明によれば、前記エッチング溝の長手方向に直角方向の切断面がＶ字形である特許請求の範囲の請求項４記載の半導体装置とする。
特許請求の範囲の請求項６記載の発明によれば、前記エッチング溝の長手方向に直角方向の切断面がＵ字形である特許請求の範囲の請求項４記載の半導体装置とする。
特許請求の範囲の請求項７記載の発明によれば、前記超接合構造と、該超接合構造のストライプ状平面形状に直交するストライプ状のＭＯＳ構造領域と、該ＭＯＳ構造領域を取り巻く耐圧構造領域と、最外周に配置される切断領域とを形成した後、該切断領域に沿ってウェットエッチングによりエッチング溝を形成し、このエッチング溝内の表面層に第一導電型のイオンを注入して第一導電型表面層を形成する特許請求の範囲の請求項１または２記載の半導体装置の製造方法とする。 According to the fifth aspect of the present invention, the semiconductor device according to the fourth aspect of the present invention is such that the cut surface perpendicular to the longitudinal direction of the etching groove is V-shaped.
According to a sixth aspect of the present invention, the semiconductor device according to the fourth aspect of the present invention is such that a cut surface perpendicular to the longitudinal direction of the etching groove is U-shaped.
According to the invention of claim 7, the superjunction structure, a stripe-shaped MOS structure region orthogonal to the stripe-like planar shape of the superjunction structure, and a breakdown voltage structure region surrounding the MOS structure region And a cutting region disposed on the outermost periphery, an etching groove is formed by wet etching along the cutting region, and ions of the first conductivity type are implanted into the surface layer in the etching groove. The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the one-conductivity type surface layer is formed.

特許請求の範囲の請求項８記載の発明によれば、前記エッチングが加熱アルカリ水溶液を用いたウェットエッチングである特許請求の範囲の請求項７記載の半導体装置の製造方法とする。
特許請求の範囲の請求項９記載の発明によれば、前記エッチングがＲＩＥエッチングによる異方性エッチングである特許請求の範囲の請求項７記載の半導体装置の製造方法とする。 According to the eighth aspect of the present invention, in the method for manufacturing a semiconductor device according to the seventh aspect, the etching is wet etching using a heated alkaline aqueous solution.
According to the ninth aspect of the present invention, in the method for manufacturing a semiconductor device according to the seventh aspect, the etching is anisotropic etching by RIE etching.

前記課題を解決するために、ウエハ全面に亘って同じ幅および同じ間隔でストライプ状ＳＪ構造を形成する半導体ウエハにおいて、ＭＯＳ構造の製造プロセス終了後に、各半導体チップの最外周辺部に、異方性ウェットエッチングによりエッチング溝を形成し、ｎ型イオンを注入して溝表面層にｎ型表面層を形成する。このｎ型表面層を切断領域に設けることにより、ウエハから半導体チップを切り出すために切断する際に、切断による欠陥層がストライプ状のＳＪ構造部には発生せず、空乏層がエッチング溝表面に現れないため、漏れ電流が抑えられる。   In order to solve the above-mentioned problem, in a semiconductor wafer in which a stripe SJ structure is formed with the same width and the same interval over the entire surface of the wafer, after the manufacturing process of the MOS structure is completed, An etching groove is formed by reactive wet etching, and n-type ions are implanted to form an n-type surface layer in the groove surface layer. By providing this n-type surface layer in the cutting region, when cutting to cut a semiconductor chip from the wafer, a defective layer due to cutting does not occur in the striped SJ structure portion, and a depletion layer is formed on the etching groove surface. Since it does not appear, the leakage current is suppressed.

本発明によれば、半導体ウエハから半導体チップを切り出す際に、切断面に超接合構造の断面が露出するストライプ状の超接合構造パターンを有する半導体装置であっても、半導体チップの切断面に露出する超接合構造に起因する漏れ電流の発生を抑制する半導体ウエハ、半導体装置およびその製造方法を提供することができる。   According to the present invention, when a semiconductor chip is cut out from a semiconductor wafer, even a semiconductor device having a stripe-shaped superjunction structure pattern in which a cross section of the superjunction structure is exposed on the cut surface is exposed on the cut surface of the semiconductor chip. It is possible to provide a semiconductor wafer, a semiconductor device, and a method for manufacturing the same that suppress the occurrence of leakage current due to the super junction structure.

以下、本発明の半導体ウエハ、半導体装置およびその製造方法について、図面を参照して詳細に説明する。本発明はその要旨を超えない限り、以下に説明する実施例の記載に限定されるものではない。図１〜図４は本発明の６００Ｖ−ＳＪ−ＭＯＳＦＥＴの実施例にかかる主要な製造工程を順に示す要部断面図である。図６は本発明と従来のＳＪ−ＭＯＳＦＥＴの漏れ電流分布を比較するグラフ図である。図８は本発明にかかるストライプ状ＳＪ構造を有するＳＪ−ＭＯＳＦＥＴのストライプ状ＳＪ構造に平行な切断領域の部分の斜視断面図である。図９は本発明にかかるストライプ状ＳＪ構造を有するＳＪ−ＭＯＳＦＥＴの切断領域近傍の斜視断面図（ａ）、同平面図（ｂ）である。（ａ）は（ｂ）のＡ−Ａ線断面を含む斜視断面図である。   Hereinafter, a semiconductor wafer, a semiconductor device, and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist. 1 to 4 are cross-sectional views showing the main parts in order of main manufacturing steps according to an embodiment of the 600V-SJ-MOSFET of the present invention. FIG. 6 is a graph comparing the leakage current distribution between the present invention and a conventional SJ-MOSFET. FIG. 8 is a perspective sectional view of a portion of a cutting region parallel to the stripe SJ structure of the SJ-MOSFET having the stripe SJ structure according to the present invention. 9A and 9B are a perspective sectional view (a) and a plan view (b) in the vicinity of a cutting region of an SJ-MOSFET having a stripe SJ structure according to the present invention. (A) is a perspective sectional view containing the AA line section of (b).

図１〜図４に実施例１にかかるトレンチ埋め込みエピ方式による６００Ｖ耐圧のＳＪ−ＭＯＳＦＥＴの主要な製造工程順に並べた半導体基板の要部断面図を示す。厚さ６２５μｍの低比抵抗、高不純物濃度のｎ型半導体基板１に５０μｍ厚で、不純物濃度４×１０１５ｃｍ−３のｎ型半導体層２をエピタキシャル成長させたウエハ３をウエハプロセスへの投入材料とする。 1 to 4 are cross-sectional views of main parts of a semiconductor substrate arranged in the order of main manufacturing steps of a 600V breakdown voltage SJ-MOSFET according to a trench buried epi method according to the first embodiment. A wafer 3 obtained by epitaxially growing an n-type semiconductor layer 2 having an impurity concentration of 4 × 10 15 cm −3 on an n-type semiconductor substrate 1 having a thickness of 625 μm and a low specific resistance and a high impurity concentration is input to the wafer process. And

厚さ２．４μｍの酸化膜４を１１５０℃／１５時間のパイロジェニック酸化により形成する。レジスト塗布およびベーク後に露光し、超接合構造の一部となるｐ型層をエピタキシャル成長により埋め込むためのトレンチ６形成用の幅６μｍのストライプ状平面パターンをウエハ３の全面に形成する。酸化膜４をエッチングしてｎ型半導体層２のＳｉ面を露出させた後、レジストを除去する（図１（ａ））。Ｓｉエッチャーにより深さ５０μｍの高アスペクトトレンチ６を形成する。トレンチエッチング中に酸化膜４もエッチングされ、残厚は１．１μｍになる（図１（ｂ））。エピタキシャル成長法により、１０００℃にてトリクロロシラン、塩化水素、ジボラン、および水素を供給しながらトレンチ６内部をｐ型エピタキシャル層５ａで埋め込む（図２（ａ））。形成したトレンチ６の平面パターンは、ウエハ３の面内に終端部のない連続ストライプ状パターンの方がエピタキシャル層の埋め込みには好都合である。円柱状または角柱状のセル状パターンの場合、ｐ型エピタキシャル層５ａの埋め込み工程において、先にトレンチ６の開口部が閉塞し、トレンチ６の内部に空洞が閉じ込められ易くなる。トレンチ６内空洞は漏れ電流の増加という悪影響を及ぼすため、極力避ける必要がある。従って、トレンチ埋め込みエピ方式によりｐ型エピタキシャル層５ａを形成するＳＪ−ＭＯＳＦＥＴにおいては、空洞のでき難いストライプ状のトレンチパターンが望ましい。ただし、後述するように、ウエハ３の面内に終端部の無い連続性ストライプパターンの場合は、ウエハから半導体チップを切り出す際に、半導体チップ外周部での切断時に付随して発生する結晶欠陥部に起因して漏れ電流が増大することが問題となる。なお、従来の多段エピ方式によるＳＪ−ＭＯＳＦＥＴの場合はセル状パターン状のＳＪ構造の適用が問題なく適用できるので、特に半導体チップ外周部の漏れ電流が増大することはなく、対策は不要である。   An oxide film 4 having a thickness of 2.4 μm is formed by pyrogenic oxidation at 1150 ° C./15 hours. A striped planar pattern having a width of 6 μm for forming a trench 6 for embedding a p-type layer that becomes a part of the superjunction structure by epitaxial growth is formed on the entire surface of the wafer 3 after resist application and baking. After the oxide film 4 is etched to expose the Si surface of the n-type semiconductor layer 2, the resist is removed (FIG. 1A). A high aspect trench 6 having a depth of 50 μm is formed by a Si etcher. The oxide film 4 is also etched during the trench etching, and the remaining thickness becomes 1.1 μm (FIG. 1B). The trench 6 is filled with the p-type epitaxial layer 5a while supplying trichlorosilane, hydrogen chloride, diborane, and hydrogen at 1000 ° C. by the epitaxial growth method (FIG. 2A). The planar pattern of the formed trench 6 is more convenient for embedding the epitaxial layer if the continuous stripe pattern having no terminal portion in the plane of the wafer 3 is used. In the case of a columnar or prismatic cell-like pattern, the opening of the trench 6 is first closed in the step of filling the p-type epitaxial layer 5a, and the cavity is easily confined inside the trench 6. Since the cavity in the trench 6 has an adverse effect of increasing leakage current, it must be avoided as much as possible. Therefore, in the SJ-MOSFET in which the p-type epitaxial layer 5a is formed by the trench buried epi method, a striped trench pattern in which a cavity is difficult to form is desirable. However, as will be described later, in the case of a continuous stripe pattern without a terminal portion in the surface of the wafer 3, when a semiconductor chip is cut out from the wafer, a crystal defect portion that occurs accompanying cutting at the outer periphery of the semiconductor chip The problem is that the leakage current increases due to the above. In the case of a conventional multi-stage epi-type SJ-MOSFET, the application of the SJ structure in the form of a cell pattern can be applied without any problem, so that the leakage current at the outer periphery of the semiconductor chip does not increase and no countermeasure is required. .

次にＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ Ｍａｃｈｉｎｅ）により基板表面に成長させたエピタキシャル層を酸化膜４の表面位置まで研磨する。その後、この酸化膜４と同程度の高さのエピタキシャル層をＳｉエッチャーにより酸化膜厚分だけエッチバックしてｐ型層５ａとする（図２（ｂ））。次に、酸化膜４を除去した後、ＭＯＳ構造の形成工程に入る。ストライプ状のＳＪ構造５とＭＯＳ構造の平面パターンを相互に直交させるように配置させると、前述のように、ＳＪ構造パターンとＭＯＳ構造のパターンとのアライメントは不要となる。半導体チップでＭＯＳ構造が形成される活性領域を取り巻く周辺部に配置される耐圧構造領域２２を覆うフィールド酸化膜２３の形成およびそのパターニングを経て、活性領域に前記フィールド酸化膜をマスクにしてゲート酸化膜１０およびゲートポリシリコン１１を形成する。次にゲートポリシリコン１１をパターニングし、これにセルフアラインさせてイオン注入および熱拡散によりｐ型ベース領域１２を形成する。ｎ型ソース領域１３、層間絶縁膜（ＢＰＳＧ）１４、ソース電極１５ならびにポリイミドなどの表面保護膜１６を形成する（図３）。ストライプ状パターンのＳＪ構造の場合は、ウエハから半導体チップを切り出すための切断領域１８にウェットエッチングによりＶ字溝１７を形成する。ＴＭＡＨ（テトラメチルアンモニウムハイドロオキサイド（ｔｅｔｒａｍｅｔｈｙｌ ａｍｍｏｎｉｕｍ ｈｙｄｒｏｘｉｄｅ））などのアルカリ水溶液を８０℃に熱し、ウェットエッチングするとシリコン層が異方性エッチングされて（１１１）面が現われる。ポリイミド膜などの表面保護膜１６やアルミニウムからなるソース電極１５はエッチングされないので、エッチングマスクとなる。このようにして切断領域１８にはＶ字溝１７が形成され、その先端部（底部）は低比抵抗ｎ型基板１に到達する深さとする（図４（ａ））。Ｖ字溝１７にドーズ量１×１０１５ｃｍ−２のリンイオンを注入し、Ｖ字溝１７の側壁表面に高濃度ｎ型表面層１９を形成する。最後に裏面ドレイン電極２０を蒸着により形成してウエハプロセスが終了する（図４（ｂ））。符号２１はウエハから半導体チップを切り出す際のダイシングラインである。しかし、本発明において切断領域１８に形成されるエッチング溝は、前述のようにＶ字溝の形成だけに限定されるものではない。ＲＩＥ（反応性イオンエッチング）による異方性のドライエッチングにより基板表面に対して垂直な側壁を有するＵ字溝であってもよい。ただし、このＲＩＥによりＵ字溝を形成する場合は、前述のＶ字溝の形成に比べて、枚葉設備のために生産性が悪く、設備価格が高く、ガス費が高いなどのため工程コストが高い。ウェットエッチングと比較して側壁に結晶ダメージが入り易く、漏れ電流増大が懸念され、さらに、追加のウェットエッチングを必要とする。Ｕ字溝の内面に高不純物濃度のｎ型表面層を形成するための斜めイオン注入時において、側壁両側に確実に注入するために、少なくとも２回のイオン注入が必要であるなどの追加プロセスや追加プロセスコストが生じるので、ウェットエッチングによるＶ字溝の形成の方がより好ましいと言える。 Next, the epitaxial layer grown on the substrate surface is polished up to the surface position of the oxide film 4 by CMP (Chemical Mechanical Polishing Machine). Thereafter, the epitaxial layer having the same height as that of the oxide film 4 is etched back by the oxide film thickness by the Si etcher to form the p-type layer 5a (FIG. 2B). Next, after the oxide film 4 is removed, a MOS structure forming process is started. When the stripe-shaped SJ structure 5 and the planar pattern of the MOS structure are arranged so as to be orthogonal to each other, as described above, alignment between the SJ structure pattern and the MOS structure pattern becomes unnecessary. After forming and patterning the field oxide film 23 covering the breakdown voltage structure region 22 arranged in the peripheral portion surrounding the active region where the MOS structure is formed in the semiconductor chip, gate oxidation is performed using the field oxide film as a mask in the active region. Film 10 and gate polysilicon 11 are formed. Next, the gate polysilicon 11 is patterned and self-aligned therewith to form a p-type base region 12 by ion implantation and thermal diffusion. An n-type source region 13, an interlayer insulating film (BPSG) 14, a source electrode 15, and a surface protective film 16 such as polyimide are formed (FIG. 3). In the case of an SJ structure with a stripe pattern, a V-shaped groove 17 is formed by wet etching in a cutting region 18 for cutting a semiconductor chip from a wafer. When an alkaline aqueous solution such as TMAH (tetramethylammonium hydroxide) is heated to 80 ° C. and wet-etched, the silicon layer is anisotropically etched and a (111) surface appears. Since the surface protective film 16 such as a polyimide film or the source electrode 15 made of aluminum is not etched, it becomes an etching mask. In this way, the V-shaped groove 17 is formed in the cutting region 18, and the tip (bottom) thereof has a depth that reaches the low specific resistance n-type substrate 1 (FIG. 4A). Phosphorus ions having a dose of 1 × 10 15 cm −2 are implanted into the V-shaped groove 17 to form a high concentration n-type surface layer 19 on the side wall surface of the V-shaped groove 17. Finally, the back surface drain electrode 20 is formed by vapor deposition, and the wafer process is completed (FIG. 4B). Reference numeral 21 denotes a dicing line for cutting a semiconductor chip from the wafer. However, the etching groove formed in the cutting region 18 in the present invention is not limited to the formation of the V-shaped groove as described above. It may be a U-shaped groove having a side wall perpendicular to the substrate surface by anisotropic dry etching by RIE (reactive ion etching). However, when the U-shaped groove is formed by this RIE, the process cost is low because the productivity is low for the single wafer equipment, the equipment price is high, and the gas cost is high compared to the above-mentioned V-shaped groove formation. Is expensive. Compared with wet etching, crystal damage is likely to occur on the side wall, and there is a concern about increase in leakage current, and additional wet etching is required. In an oblique ion implantation for forming an n-type surface layer having a high impurity concentration on the inner surface of the U-shaped groove, an additional process such that at least two ion implantations are necessary in order to reliably implant both sides of the sidewall, Since an additional process cost occurs, it can be said that the formation of the V-shaped groove by wet etching is more preferable.

ゲートオフ状態においてドレイン電極２０に正バイアスを印加すると、ｐ型層５ａとｎ型層２が交互に並んだＳＪ構造５が空乏化する。低バイアスでｐｎ層のＳＪ構造５が完全空乏化する設計になっているので、ｐ型層５ａとｎ型層２が低比抵抗であるにも関わらず高耐圧が得られる。ところで、ストライプ状のｐ型層５ａの表面は一部でソース電極１５に接触しており、また、このストライプ状の平面パターンのｐ型層５ａはチップ最外周部まで伸びている。従って、図９の半導体チップの周辺部の斜視断面図（ａ）および平面図（ｂ）に示すように、ｐ型層５ａは完全空乏化する前段階においてはソース電位を維持する。チップ外周部の切断面に対策を施さない場合、前記図５で説明したように、ドレイン電極２０に正バイアスを加えるとチップ外周部の切断面に露出したｐ型層５ａとドレイン電極２０間に大きな漏れ電流が流れる。これはウエハから半導体チップをダイシングにより切り出した後のチップ側壁の切断面は表面保護膜１６で覆われておらず、また、切断による結晶欠陥が残存しているためである。本実施例１のようにチップ外周部の切断領域１８にウェットエッチングによりＶ字溝１７を形成し、イオン注入によりＶ字溝１７の内側の表面層に高濃度ｎ型層１９を形成すれば、空乏層がこの高濃度ｎ型層１９で停止するために表面保護膜１６がＶ字溝１７に無くても、Ｖ字溝１７側壁表面に到達しない。したがって、側壁表面を通じて流れる漏れ電流を回避ことができる。また、ウェットエッチングにより結晶欠陥領域を除去するので、結晶欠陥に起因して発生する漏れ電流を防ぐことができる。   When a positive bias is applied to the drain electrode 20 in the gate-off state, the SJ structure 5 in which the p-type layer 5a and the n-type layer 2 are alternately arranged is depleted. Since the SJ structure 5 of the pn layer is designed to be completely depleted at a low bias, a high breakdown voltage can be obtained even though the p-type layer 5a and the n-type layer 2 have a low specific resistance. By the way, a part of the surface of the striped p-type layer 5a is in contact with the source electrode 15, and the striped planar pattern p-type layer 5a extends to the outermost peripheral portion of the chip. Accordingly, as shown in the perspective sectional view (a) and the plan view (b) of the peripheral portion of the semiconductor chip in FIG. 9, the p-type layer 5a maintains the source potential in the stage before complete depletion. In the case where no measures are taken on the cut surface of the outer periphery of the chip, as described with reference to FIG. 5, when a positive bias is applied to the drain electrode 20, the gap between the p-type layer 5a exposed on the cut surface of the outer periphery of the chip and the drain electrode 20 A large leakage current flows. This is because the cut surface of the chip side wall after the semiconductor chip is cut out from the wafer by dicing is not covered with the surface protective film 16, and crystal defects due to the cutting remain. If the V-shaped groove 17 is formed by wet etching in the cutting region 18 on the outer periphery of the chip as in the first embodiment, and the high concentration n-type layer 19 is formed on the inner surface layer of the V-shaped groove 17 by ion implantation, Since the depletion layer stops at the high-concentration n-type layer 19, even if the surface protection film 16 is not present in the V-shaped groove 17, it does not reach the surface of the V-shaped groove 17. Therefore, the leakage current flowing through the side wall surface can be avoided. In addition, since the crystal defect region is removed by wet etching, a leakage current generated due to the crystal defect can be prevented.

図６はＶ字溝を設けた本発明と設けない場合のＳＪ−ＭＯＳＦＥＴについて、ドレイン−ソース間電圧とドレイン電流（モレ電流）との関係を比較して示すグラフ図である。図６によれば、Ｖ字溝１７の形成により、半導体チップの外周部における漏れ電流が大幅に低減されていることが示されている。一方、図７の要部平面図に示すように、ＳＪ構造として、前述のようにストライプ状ではなく、コラム状パターン（またはセル状パターン）のｐ型層５ｂをウエハ全面に形成した場合は、活性領域においてソース電極１５に接触するｐ型層５ｃとチップ外周付近のｐ型層５ｂは電気的に分離されている。そのため、半導体チップに切り出す際に、コラム状のｐ型層５ｂのところで切断されても、漏れ電流は増大する惧れはないので、実施例１で説明したようなＶ字溝を形成する必要がない。   FIG. 6 is a graph showing the relationship between the drain-source voltage and the drain current (more current) for the SJ-MOSFET without the V-groove and the SJ-MOSFET without the V-groove. FIG. 6 shows that the formation of the V-shaped groove 17 significantly reduces the leakage current at the outer periphery of the semiconductor chip. On the other hand, as shown in the plan view of the main part of FIG. 7, when the p-type layer 5b of the columnar pattern (or cell-like pattern) is formed on the entire surface of the SJ structure instead of the stripe shape as described above, In the active region, the p-type layer 5c in contact with the source electrode 15 and the p-type layer 5b in the vicinity of the chip periphery are electrically separated. Therefore, when cutting into a semiconductor chip, there is no possibility that the leakage current will increase even if it is cut at the columnar p-type layer 5b. Therefore, it is necessary to form a V-shaped groove as described in the first embodiment. Absent.

図８はＳＪ構造のストライプ状パターンに平行に形成されるＶ字溝１７の部分を示す斜視断面図である。
実施例１によれば、ＳＪ構造とＭＯＳ構造の正確なアライメントを不要とするためにウエハ全面にストライプＳＪ構造を形成する製造工程としても、チップ周辺部の切断部に露出するＳＪ構造に起因する漏れ電流の発生を抑えることができる。また副次的効果としてチップサイズに関係なくＳＪ構造のパターンがウエハ全面に形成されるので、チップサイズが決まる前にＳＪ構造を形成したウエハを製造しておくことができる。複雑で工程時間が長くかかるＳＪ構造を有するウエハの形成をあらかじめ完了させておくことが可能である。製造要求が来てからチップ完成までの製造リードタイムを大幅に削減することができ、製品物量に対する要求に迅速に応えられるようになる。 FIG. 8 is a perspective sectional view showing a portion of the V-shaped groove 17 formed in parallel to the stripe pattern having the SJ structure.
According to the first embodiment, the manufacturing process for forming the stripe SJ structure on the entire surface of the wafer in order to eliminate the need for accurate alignment between the SJ structure and the MOS structure is caused by the SJ structure exposed at the cut portion around the chip. Generation of leakage current can be suppressed. Further, as a secondary effect, a pattern having an SJ structure is formed on the entire surface of the wafer regardless of the chip size. Therefore, a wafer having the SJ structure can be manufactured before the chip size is determined. It is possible to complete in advance the formation of a wafer having an SJ structure that is complicated and takes a long process time. The manufacturing lead time from when the manufacturing request comes to the completion of the chip can be greatly reduced, and the demand for the product quantity can be quickly met.

本発明の６００Ｖ−ＳＪ−ＭＯＳＦＥＴの実施例にかかる主要な製造工程を順に示す要部断面図（その１）である。FIG. 6 is a cross-sectional view (No. 1) of main parts sequentially illustrating main manufacturing steps according to an example of the 600V-SJ-MOSFET of the present invention. 本発明の６００Ｖ−ＳＪ−ＭＯＳＦＥＴの実施例にかかる主要な製造工程を順に示す要部断面図（その２）である。FIG. 6 is a cross-sectional view (No. 2) showing the main manufacturing steps in order according to the embodiment of the 600V-SJ-MOSFET of the present invention. 本発明の６００Ｖ−ＳＪ−ＭＯＳＦＥＴの実施例にかかる主要な製造工程を順に示す要部断面図（その３）である。FIG. 6 is a sectional view (No. 3) showing essential part of the main manufacturing steps according to an embodiment of the 600V-SJ-MOSFET of the present invention in order. 本発明の６００Ｖ−ＳＪ−ＭＯＳＦＥＴの実施例にかかる主要な製造工程を順に示す要部断面図（その４）である。FIG. 10 is a sectional view (No. 4) showing essential part of the main manufacturing steps in order according to the example of the 600V-SJ-MOSFET of the present invention. 従来のストライプ状ＳＪ構造を有するＳＪ−ＭＯＳＦＥＴの周辺部の斜視断面図である。It is a perspective sectional view of the periphery of an SJ-MOSFET having a conventional striped SJ structure. 本発明と従来のＳＪ−ＭＯＳＦＥＴの漏れ電流分布を比較するグラフ図である。It is a graph which compares the leakage current distribution of this invention and the conventional SJ-MOSFET. 従来のセル状ＳＪ構造を有するＳＪ−ＭＯＳＦＥＴの周辺部の平面図である。。It is a top view of the peripheral part of SJ-MOSFET which has the conventional cellular SJ structure. . 本発明にかかるストライプ状ＳＪ構造を有するＳＪ−ＭＯＳＦＥＴのストライプ状ＳＪ構造に平行な切断領域の部分の斜視断面図である。It is a perspective sectional view of a portion of a cutting region parallel to the stripe SJ structure of the SJ-MOSFET having the stripe SJ structure according to the present invention. 本発明にかかるストライプ状ＳＪ構造を有するＳＪ−ＭＯＳＦＥＴの切断領域近傍の斜視断面図である。It is a perspective sectional view of the cutting region vicinity of SJ-MOSFET which has a striped SJ structure concerning the present invention.

符号の説明Explanation of symbols

１ 高不純物濃度ｎ型半導体基板
２ ｎ型層
３ ウエハ
４ 酸化膜
５ ＳＪ構造
５ａ ｐ型層
６ トレンチ
１０ ゲート酸化膜
１１ ゲートポリシリコン
１２ ｐ型ベース領域
１３ ｎ型ソース領域
１４ 層間絶縁膜
１５ ソース電極
１６ 表面保護膜
１７ Ｖ字溝
１８ 切断領域
１９ ｎ型表面層
２０ ドレイン電極
２１ ダイシングライン
２２ 耐圧構造領域
２３ フィールド酸化膜。 1 high impurity concentration n-type semiconductor substrate 2 n-type layer 3 wafer 4 oxide film 5 SJ structure 5a p-type layer 6 trench 10 gate oxide film 11 gate polysilicon 12 p-type base region 13 n-type source region 14 interlayer insulating film 15 source Electrode 16 Surface protective film 17 V-shaped groove 18 Cutting region 19 N-type surface layer 20 Drain electrode 21 Dicing line 22 Withstand voltage structure region 23 Field oxide film

Claims (9)

第一導電型の半導体基板の主面上に設けられ、該主面に垂直方向であって薄層状の第一導電型層および第二導電型層が、前記主面に平行な方向では、ストライプ状平面形状であって交互に繰り返し隣接すると共に、前記半導体基板の全面に亘って等間隔で配置されている超接合構造と、該超接合構造の表面に半導体装置の縦横寸法をピッチ間隔として配置される該半導体装置の格子状パターンが前記超接合構造のストライプ状平面形状に平行および直交する配置を有し、該半導体装置が、前記超接合構造のストライプ状平面形状に直交するように表面層に配置されるストライプ状のＭＯＳ構造領域と該ＭＯＳ構造領域を取り巻く耐圧構造領域と最外周に格子状に配置される切断領域と該切断領域に沿って配置されるエッチング溝とを備え、該エッチング溝が前記超接合構造の表面から前記半導体基板に達する深さと、該エッチング溝の内面を覆う第一導電型表面層を備えることを特徴とする半導体ウエハ。 A first conductive type layer and a second conductive type layer which are provided on the main surface of the first conductivity type semiconductor substrate and are perpendicular to the main surface and are parallel to the main surface. A super-junction structure that is alternately planarly adjacent to each other and arranged at equal intervals over the entire surface of the semiconductor substrate, and the vertical and horizontal dimensions of the semiconductor device are arranged at pitch intervals on the surface of the super-junction structure. A surface layer so that the lattice pattern of the semiconductor device is arranged parallel and perpendicular to the stripe-like planar shape of the superjunction structure, and the semiconductor device is perpendicular to the stripe-like planar shape of the superjunction structure A stripe-shaped MOS structure region disposed in the region, a breakdown voltage structure region surrounding the MOS structure region, a cutting region disposed in a grid pattern on the outermost periphery, and an etching groove disposed along the cutting region, Semiconductor wafers, characterized in that it comprises a depth etching grooves reaches the semiconductor substrate from the surface of the super junction structure, a first conductivity type surface layer covering the inner surface of the etched groove. 前記エッチング溝の長手方向に直角方向の切断面がＶ字形であることを特徴とする請求項１記載の半導体ウエハ。 2. The semiconductor wafer according to claim 1, wherein a cut surface perpendicular to the longitudinal direction of the etching groove is V-shaped. 前記エッチング溝の長手方向に直角方向の切断面がＵ字形であることを特徴とする請求項１記載の半導体ウエハ。 2. The semiconductor wafer according to claim 1, wherein a cut surface perpendicular to the longitudinal direction of the etching groove is U-shaped. 第一導電型の半導体基板の主面上に設けられ、該主面に垂直方向であって薄層状の第一導電型層および第二導電型層が、前記主面に平行な方向では、ストライプ状平面形状であって交互に等間隔で繰り返し隣接する超接合構造と、該超接合構造の前記ストライプ状平面形状に直交するように表面層に配置されるストライプ状のＭＯＳ構造領域と該ＭＯＳ構造領域を取り巻く耐圧構造領域と最外周に配置される切断領域と該切断領域に沿って配置されるエッチング溝とを備え、該エッチング溝が前記超接合構造の表面から前記半導体基板に達する深さと、該エッチング溝の内面を覆う第一導電型表面層を備えることを特徴とする半導体装置。 A first conductive type layer and a second conductive type layer which are provided on the main surface of the first conductivity type semiconductor substrate and are perpendicular to the main surface and are parallel to the main surface. A superjunction structure having a planar shape and alternately adjacent to each other at regular intervals, and a stripe-like MOS structure region disposed on a surface layer so as to be orthogonal to the stripe-like planar shape of the superjunction structure and the MOS structure A pressure-resistant structure region surrounding the region, a cutting region disposed on the outermost periphery, and an etching groove disposed along the cutting region, and a depth at which the etching groove reaches the semiconductor substrate from the surface of the superjunction structure; A semiconductor device comprising a first conductivity type surface layer covering an inner surface of the etching groove. 前記エッチング溝の長手方向に直角方向の切断面がＶ字形であることを特徴とする請求項４記載の半導体装置。 5. The semiconductor device according to claim 4, wherein a cut surface perpendicular to the longitudinal direction of the etching groove is V-shaped. 前記エッチング溝の長手方向に直角方向の切断面がＵ字形であることを特徴とする請求項４記載の半導体装置。 5. The semiconductor device according to claim 4, wherein a cut surface perpendicular to the longitudinal direction of the etching groove is U-shaped. 前記超接合構造と、該超接合構造のストライプ状平面形状に平行または直交するストライプ状のＭＯＳ構造領域と、該ＭＯＳ構造領域を取り巻く耐圧構造領域と、最外周に配置される切断領域とを形成した後、該切断領域に沿ってエッチングによりエッチング溝を形成し、このエッチング溝内の表面層に第一導電型のイオンを注入して第一導電型表面層を形成することを特徴とする請求項１または４記載の半導体装置の製造方法。 Forming the super-junction structure, a stripe-shaped MOS structure region parallel to or perpendicular to the stripe-like planar shape of the super-junction structure, a breakdown voltage structure region surrounding the MOS structure region, and a cutting region disposed on the outermost periphery Then, an etching groove is formed by etching along the cut region, and a first conductivity type surface layer is formed by implanting ions of the first conductivity type into the surface layer in the etching groove. Item 5. A method for manufacturing a semiconductor device according to Item 1 or 4. 前記エッチングが加熱アルカリ水溶液をを用いたウェットエッチングであることを特徴とする請求項７記載の半導体装置の製造方法。 8. The method of manufacturing a semiconductor device according to claim 7, wherein the etching is wet etching using a heated alkaline aqueous solution. 前記エッチングがＲＩＥエッチングによる異方性エッチングであることを特徴とする請求項７記載の半導体装置の製造方法。
8. The method of manufacturing a semiconductor device according to claim 7, wherein the etching is anisotropic etching by RIE etching.
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