JP2010028003A - Wiring substrate - Google Patents

Wiring substrate Download PDF

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Publication number
JP2010028003A
JP2010028003A JP2008190578A JP2008190578A JP2010028003A JP 2010028003 A JP2010028003 A JP 2010028003A JP 2008190578 A JP2008190578 A JP 2008190578A JP 2008190578 A JP2008190578 A JP 2008190578A JP 2010028003 A JP2010028003 A JP 2010028003A
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Japan
Prior art keywords
underfill material
semiconductor element
substrate
wiring board
reinforcing plate
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JP2008190578A
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Japanese (ja)
Inventor
Shinichi Kato
真一 加藤
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Panasonic Corp
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Panasonic Corp
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Priority to JP2008190578A priority Critical patent/JP2010028003A/en
Publication of JP2010028003A publication Critical patent/JP2010028003A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring substrate for reliably blocking the overflow of a surplus underfill material. <P>SOLUTION: The wiring substrate 1 is a flexible substrate where a semiconductor element 2 is mounted on a substrate 10 with the underfill material U interposed therebetween. An FPC reinforcing plate 20 which is a sheet shape member with a notched part 21 formed by notching a range for mounting the semiconductor element 2 is arranged on the substrate 10. The FPC reinforcing plate 20 is a resin-made plate material. The FPC reinforcing plate 20 with the notched part 21 is arranged on the substrate 10, thereby not only blocking the surplus underfill material U but forming a fillet F even up to a high position on the outer peripheral side surface of the semiconductor element 2. Consequently, cracking is prevented even when thermal stress is added to the semiconductor element 2 in hardening the underfill material U. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半田付けされた電子部品と基板本体との間にアンダーフィル材が充填される配線基板に関する。   The present invention relates to a wiring board in which an underfill material is filled between a soldered electronic component and a board body.

配線基板に電子部品を固定するときに、半田付けされた電子部品と配線基板との隙間に接着部材であるアンダーフィル材を流し込み、アンダーフィル材を硬化させることで、電子部品と配線基板との接着を強固にする。例えば、特許文献１に記載の配線基板では、流し込むアンダーフィル材の余剰分が電子部品の周囲のプリント配線基板上に流出しないように、ダム用ランドと、ダム用ランド上に形成された半田ダムとからなるダムが、電子部品を取り囲むように形成されたものである。余剰のアンダーフィル材を堰き止めるダムを設けたことで、電子部品の高密度実装を可能とするものである。
特開２００６−１４０３２７号公報 When fixing an electronic component to the wiring board, an underfill material, which is an adhesive member, is poured into the gap between the soldered electronic component and the wiring board, and the underfill material is cured, so that the electronic component and the wiring board are cured. Strengthen adhesion. For example, in the wiring board described in Patent Document 1, a dam land and a solder dam formed on the dam land so that an excessive amount of the underfill material to be poured does not flow out onto the printed wiring board around the electronic component. The dam is formed so as to surround the electronic component. By providing a dam that blocks the excess underfill material, high-density mounting of electronic components is possible.
JP 2006-140327 A

しかし、特許文献１に記載の配線基板では、アンダーフィル材を堰き止めるダムとして頂部が表面張力により略球面となる半田を用いているので、流れ出した余剰のアンダーフィル材の量が多い場合には、堰き止められることで嵩高くなったアンダーフィル材が半田ダムの頂部まで達すると、半田ダムを乗り越えてしまうおそれがある。   However, in the wiring board described in Patent Document 1, since the dam that dams up the underfill material uses solder whose top portion becomes a substantially spherical surface due to surface tension, the amount of excess underfill material that has flowed out is large. When the underfill material that has become bulky due to damming reaches the top of the solder dam, the solder dam may be overcome.

そこで本発明は、余剰のアンダーフィル材の流出を確実に堰き止めることができる配線基板を提供することを目的とする。   Therefore, an object of the present invention is to provide a wiring board that can reliably block outflow of excess underfill material.

本発明の配線基板は、電子部品がアンダーフィル材を介在させて基板本体上に実装される配線基板において、前記電子部品が搭載される範囲を切り欠いた切欠部が形成されたシート状部材が前記基板本体上に設けられていることを特徴とする。   The wiring board according to the present invention is a wiring board in which an electronic component is mounted on a substrate body with an underfill material interposed, and a sheet-like member in which a cutout portion is formed by cutting out a range where the electronic component is mounted. It is provided on the substrate body.

本発明の配線基板は、電子部品が搭載される範囲が切り欠かれた切欠部が形成されたシート状部材を備えているので、余剰のアンダーフィル材が内周壁面の高さ以上にならない限り溢れ出ることはない。従って、本発明の配線基板は、余剰のアンダーフィル材の流出を確実に堰き止めることができる。   Since the wiring board of the present invention includes the sheet-like member in which the cutout portion in which the electronic component is mounted is cut out, as long as the excess underfill material does not exceed the height of the inner peripheral wall surface. It will not overflow. Therefore, the wiring board of the present invention can reliably block outflow of excess underfill material.

本願の第１の発明は、電子部品がアンダーフィル材を介在させて基板本体上に実装される配線基板において、電子部品が搭載される範囲を切り欠いた切欠部が形成されたシート状部材が基板本体上に設けられていることを特徴としたものである。   According to a first aspect of the present invention, there is provided a wiring board in which an electronic component is mounted on a substrate body with an underfill material interposed, and a sheet-like member in which a cutout portion is formed by cutting out a range where the electronic component is mounted. It is provided on the substrate body.

本発明の配線基板は、基板本体上にシート状部材が設けられている。このシート状部材には、電子部品が搭載される範囲が切り欠かれた切欠部が形成されている。電子部品の下から流れ出る余剰のアンダーフィル材は、切り欠かれることで立壁面となった切欠部の内周壁面に達することで堰き止められ、徐々に嵩高くなる。しかし、内周壁面の開口部分は半田を盛り上げることで形成した半田ダムと異なり球面状ではないため、余剰のアンダーフィル材が内周壁面の高さ以上にならない限り溢れ出ることはない。   In the wiring board of the present invention, a sheet-like member is provided on the board body. The sheet-like member is formed with a cutout portion in which a range in which an electronic component is mounted is cut out. The surplus underfill material that flows out from under the electronic component reaches the inner peripheral wall surface of the notch portion that has become a standing wall surface by being cut out, and gradually becomes bulky. However, since the opening portion of the inner peripheral wall surface is not spherical, unlike the solder dam formed by raising the solder, it does not overflow unless the excess underfill material exceeds the height of the inner peripheral wall surface.

本願の第２の発明は、第１の発明において、シート状部材は、樹脂製板材であることを特徴としたものである。   According to a second invention of the present application, in the first invention, the sheet-like member is a resin plate material.

本願の第２の発明においては、シート状部材を樹脂製板材とすることで、厚みが厚いシート状部材を容易に準備することができ、切欠部の形成も容易である。   In 2nd invention of this application, a sheet-like member can be easily prepared by making a sheet-like member into a resin-made board | plate material, and formation of a notch part is also easy.

本願の第３の発明は、第１または第２の発明において、基板本体は、可撓性を有するフレキシブル基板であることを特徴としたものである。   According to a third invention of the present application, in the first or second invention, the substrate body is a flexible substrate having flexibility.

第３の発明においては、基板本体が可撓性を有するフレキシブル基板である場合には、基板本体上にシート状部材を設けることで、厚みが厚くなるので撓みに対する強度を増加させることができる。特に、シート状部材が樹脂製板材である場合には、より強度が増加する。   In the third invention, when the substrate main body is a flexible flexible substrate, by providing a sheet-like member on the substrate main body, the thickness is increased, so that the strength against bending can be increased. In particular, when the sheet-like member is a resin plate material, the strength is further increased.

（実施の形態）
本発明の実施の形態に係る配線基板を図面に基づいて説明する。図１は、本発明の実施の形態に係る配線基板に半導体素子を搭載した状態の断面図である。図２は、図１に示す配線基板の平面図である。図３は、半導体素子の一部断面図である。 (Embodiment)
A wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a state in which a semiconductor element is mounted on a wiring board according to an embodiment of the present invention. FIG. 2 is a plan view of the wiring board shown in FIG. FIG. 3 is a partial cross-sectional view of the semiconductor element.

配線基板１は、ＦＰＣ（Flexible Printed Circuits）とも呼ばれる可撓性を有するフレキシブル基板である。この配線基板１は、表示制御用のドライバである半導体素子２を搭載して表示装置（図示せず）に実装される。配線基板１は、基板本体１０と、ＦＰＣ補強板２０とを備えている。   The wiring board 1 is a flexible flexible board called FPC (Flexible Printed Circuits). The wiring substrate 1 is mounted on a display device (not shown) with a semiconductor element 2 serving as a display control driver mounted thereon. The wiring board 1 includes a board body 10 and an FPC reinforcing plate 20.

基板本体１０は、ベースフィルム１１を中心に、第１，２銅箔配線１２，１３と、表裏両面の第１，２カバーフィルム１４，１５と、スルーホール電極１６とを備えた２層配線基板である。なお、本実施の形態では、半導体素子２のみが一方の面側に搭載されているが、他方の面側にも他の電子部品を搭載することができる。   The substrate body 10 is a two-layer wiring board including first and second copper foil wirings 12 and 13, first and second cover films 14 and 15 on both front and back surfaces, and a through-hole electrode 16 with a base film 11 as the center. It is. In the present embodiment, only the semiconductor element 2 is mounted on one surface side, but other electronic components can also be mounted on the other surface side.

ベースフィルム１１は、ポリイミドで形成されている。   The base film 11 is made of polyimide.

第１，２銅箔配線１２，１３は、金属細線で形成された配線パターンである。第１，２銅箔配線１２，１３は、半導体素子２とスルーホール電極１６により導通接続されている。   The first and second copper foil wirings 12 and 13 are wiring patterns formed of thin metal wires. The first and second copper foil wirings 12 and 13 are conductively connected to the semiconductor element 2 through the through-hole electrode 16.

第１，２カバーフィルム１４，１５は、ポリイミドで形成され、第１，２銅箔配線１２，１３を保護するために設けられている。この第１カバーフィルム１４が切り欠かれることで露出したスルーホール電極１６の一端側が、半導体素子２の外部端子と接続する接続端子となっている。   The first and second cover films 14 and 15 are made of polyimide and are provided to protect the first and second copper foil wirings 12 and 13. One end side of the through-hole electrode 16 exposed by cutting out the first cover film 14 serves as a connection terminal connected to the external terminal of the semiconductor element 2.

スルーホール電極１６は、半導体素子２の外部端子であるＣｕポストの位置に合わせて、縦列および横列に配置されている。最外周に位置するスルーホール電極１６と、一つ内側に位置するスルーホール電極１６とは、第１銅箔配線１２と接続している。残りの中央部に位置するスルーホール電極１６は、第２銅箔配線１３（図２では図示せず）と接続している。   The through-hole electrodes 16 are arranged in columns and rows in accordance with the positions of Cu posts that are external terminals of the semiconductor element 2. The through-hole electrode 16 positioned on the outermost periphery and the through-hole electrode 16 positioned on the inner side are connected to the first copper foil wiring 12. The remaining through-hole electrode 16 located in the center is connected to the second copper foil wiring 13 (not shown in FIG. 2).

次に、この配線基板１に搭載される半導体素子２を図３に基づいて説明する。   Next, the semiconductor element 2 mounted on the wiring board 1 will be described with reference to FIG.

図３に示すように、半導体素子２は、５ｍｍ×５ｍｍの矩形状のＣＳＰ（Chip Size Package）で形成されたＬＳＩ（Large Scale Integration）である。半導体素子２は、Ｓｉチップ２ａに層間絶縁膜２ｂとアルミ配線２ｃとが積層されることで回路が構成されている。表面保護用のパッシベーション膜２ｄが最外層の層間絶縁膜２ｂにＡｌパッド２ｅを除く領域に設けられている。Ａｌパッド２ｅは、ポリイミド膜２ｆの開口部分から再配線されたＣｕ配線２ｇにより半田ボールＢと接続するＣｕポスト２ｈに接続されている。そして、これらは、エポキシ樹脂で形成された樹脂封止部２ｉにより封止されていることで保護されている。   As shown in FIG. 3, the semiconductor element 2 is an LSI (Large Scale Integration) formed of a 5 mm × 5 mm rectangular CSP (Chip Size Package). The semiconductor element 2 has a circuit formed by stacking an interlayer insulating film 2b and an aluminum wiring 2c on a Si chip 2a. A passivation film 2d for protecting the surface is provided on the outermost interlayer insulating film 2b in a region excluding the Al pad 2e. The Al pad 2e is connected to a Cu post 2h that is connected to the solder ball B by a Cu wiring 2g re-wired from the opening of the polyimide film 2f. These are protected by being sealed by a resin sealing portion 2i formed of an epoxy resin.

次に、基板本体１０上に配置されるＦＰＣ補強板２０について図１および図２に基づいて説明する。   Next, the FPC reinforcement board 20 arrange | positioned on the board | substrate body 10 is demonstrated based on FIG. 1 and FIG.

ＦＰＣ補強板２０は、ＰＥＴ（polyethylene terephthalate）製で厚みが約０．２５ｍｍの板材である。このＦＰＣ補強板２０は、半導体素子２を搭載するために切り欠かれた第１カバーフィルム１４の開口と同じ範囲を切り欠いた切欠部２１が設けられている。この切欠部２１は、ＰＥＴ製の板材を打ち抜き加工することで容易に形成することができる。ＦＰＣ補強板２０は、基板本体１０に接着剤を介在させて貼り付けられている。このＦＰＣ補強板２０は、作業者が手作業により貼り付け可能なものである。なお、本実施の形態では、１枚のＦＰＣ補強板２０を基板本体１０に貼り付けているが、２枚以上貼り付けることも可能である。その場合にはより多くのアンダーフィル材Ｕを堰き止めることができる。   The FPC reinforcing plate 20 is a plate material made of PET (polyethylene terephthalate) and having a thickness of about 0.25 mm. The FPC reinforcing plate 20 is provided with a cutout portion 21 cut out in the same range as the opening of the first cover film 14 cutout for mounting the semiconductor element 2. The notch 21 can be easily formed by punching a PET plate material. The FPC reinforcing plate 20 is attached to the substrate body 10 with an adhesive interposed therebetween. The FPC reinforcing plate 20 can be attached manually by an operator. In the present embodiment, one FPC reinforcing plate 20 is attached to the substrate body 10, but two or more sheets can be attached. In that case, more underfill material U can be dammed up.

以上のように構成された本発明の実施の形態に係る配線基板１に電子部品の一例である半導体素子２を搭載するときの状態を図面に基づいて説明する。   A state when the semiconductor element 2 which is an example of the electronic component is mounted on the wiring board 1 according to the embodiment of the present invention configured as described above will be described with reference to the drawings.

配線基板１を準備する。配線基板１には基板本体１０にＦＰＣ補強板２０が貼り付けられているものとする。   A wiring board 1 is prepared. It is assumed that an FPC reinforcing plate 20 is attached to the board body 10 on the wiring board 1.

基板本体１０のスルーホール電極１６上にバンプである半田ボールＢを配置する。次に、半導体素子２を半田ボールＢ上にＣｕポスト２ｈの位置を合わせて載置する。そして加熱により半田ボールＢが溶融してスルーホール電極１６とＣｕポスト２ｈとを接続する。   Solder balls B, which are bumps, are arranged on the through-hole electrodes 16 of the substrate body 10. Next, the semiconductor element 2 is placed on the solder ball B with the position of the Cu post 2h aligned. Then, the solder ball B is melted by heating to connect the through-hole electrode 16 and the Cu post 2h.

半導体素子２と基板本体１０との間に熱硬化性のアンダーフィル材Ｕを流し込む。流し込まれたアンダーフィル材Ｕは半導体素子２下の全面に行き渡ると共に、余剰のアンダーフィル材ＵがＦＰＣ補強板２０の切欠部２１で囲まれた範囲に広がる。   A thermosetting underfill material U is poured between the semiconductor element 2 and the substrate body 10. The poured underfill material U spreads over the entire surface under the semiconductor element 2, and the excess underfill material U spreads in a range surrounded by the notch 21 of the FPC reinforcing plate 20.

そして、余剰のアンダーフィル材Ｕは、打ち抜き加工することで立壁面となった切欠部２１の内周面に堰き止められ、徐々に嵩高くなる。そしてアンダーフィル材Ｕは、切欠部２１の内周壁面２１ａの頂部まで達すると共に、山の裾野が広がるようなフィレットＦが半導体素子２の外周側面にできる。余剰のアンダーフィル材Ｕを堰き止めるＦＰＣ補強板２０が設けられていることで、半導体素子２の樹脂封止部２ｉより高くＳｉチップ２ａに至る高さまでフィレットＦを形成することができる。   And the excess underfill material U is dammed to the inner peripheral surface of the notch part 21 which became a standing wall surface by punching, and becomes gradually bulky. The underfill material U reaches the top of the inner peripheral wall surface 21 a of the notch 21, and a fillet F that spreads the bottom of the mountain can be formed on the outer peripheral side surface of the semiconductor element 2. By providing the FPC reinforcing plate 20 that dams up the excess underfill material U, the fillet F can be formed to a height higher than the resin sealing portion 2i of the semiconductor element 2 and reaching the Si chip 2a.

切欠部２１の内周壁面２１ａの開口部分は、半田のように球面状ではないため、余剰のアンダーフィル材Ｕが内周壁面２１ａの高さ以上にならない限り溢れ出ることはない。   Since the opening part of the inner peripheral wall surface 21a of the notch part 21 is not spherical like solder, it does not overflow unless the excess underfill material U exceeds the height of the inner peripheral wall surface 21a.

アンダーフィル材Ｕの充填が完了するとアンダーフィル材Ｕを熱硬化させる。この加熱により半導体素子２にストレスが加わる。このストレスは、パッシベーション膜２ｄのクラックとなることがある。しかし、ＦＰＣ補強板２０の切欠部２１によってＳｉチップ２ａに至る高さまでのフィレットＦが形成されているため、このストレスをフィレットＦが緩和することで、パッシベーション膜２ｄへのクラックを防止することができる。   When the filling of the underfill material U is completed, the underfill material U is thermoset. Stress is applied to the semiconductor element 2 by this heating. This stress may cause a crack in the passivation film 2d. However, since the fillet F up to the height reaching the Si chip 2a is formed by the cutout portion 21 of the FPC reinforcing plate 20, the fillet F can relieve this stress, thereby preventing cracks in the passivation film 2d. it can.

また、ＦＰＣ補強板２０を基板本体１０上に貼り付けることで、配線基板１の厚みが厚くなるので撓みに対する強度を増加させることができる。   Moreover, since the thickness of the wiring board 1 becomes thick by sticking the FPC reinforcing plate 20 on the board body 10, the strength against bending can be increased.

このように、半導体素子２が搭載される範囲を切り欠いた切欠部２１が形成されたシート状部材であるＦＰＣ補強板２０が基板本体１０上に設けられていることで、余剰のアンダーフィル材Ｕの流出を防止すると共に、フィレットＦを半導体素子２の外周側面の高い位置まで形成することができる。   Thus, the surplus underfill material is provided by providing the FPC reinforcing plate 20 which is a sheet-like member in which the cutout portion 21 is formed by cutting out a range in which the semiconductor element 2 is mounted on the substrate body 10. While preventing the outflow of U, the fillet F can be formed to a high position on the outer peripheral side surface of the semiconductor element 2.

以上、本発明の実施の形態について説明してきたが、本発明は前記実施の形態に限定されるものではない。例えば、本実施の形態では、電子部品として表示制御用のドライバである半導体素子２を例に説明したが、他の電子部品でも同様の効果を得ることができる。   As mentioned above, although embodiment of this invention has been described, this invention is not limited to the said embodiment. For example, in the present embodiment, the semiconductor element 2 which is a display control driver is described as an example of the electronic component, but the same effect can be obtained with other electronic components.

また、シート状部材として樹脂製のＦＰＣ補強板２０を基板本体１０に貼り付けているが、基板本体１０の作製時に第１カバーフィルム１４上に１枚以上のポリイミド製の補強板（カバーフィルム）を多数重ねることでＦＰＣ補強板としてもよい。この場合には、アンダーフィル材の流出を抑止しつつ、基板本体１０の可撓性を維持することができる。   In addition, a resin-made FPC reinforcing plate 20 is attached to the substrate body 10 as a sheet-like member, but at least one polyimide reinforcing plate (cover film) is formed on the first cover film 14 when the substrate body 10 is manufactured. It is good also as a FPC reinforcement board by stacking many. In this case, the flexibility of the substrate body 10 can be maintained while preventing the underfill material from flowing out.

本発明は、余剰のアンダーフィル材の流出を確実に堰き止めることができるので、半田付けされた電子部品と基板本体との間にアンダーフィル材が充填される配線基板に好適である。   The present invention can reliably block outflow of excess underfill material, and is therefore suitable for a wiring board in which an underfill material is filled between a soldered electronic component and a substrate body.

本発明の実施の形態に係る配線基板に半導体素子を搭載した状態の断面図Sectional drawing of the state which mounted the semiconductor element on the wiring board which concerns on embodiment of this invention 図１に示す配線基板の平面図Plan view of the wiring board shown in FIG. 半導体素子を示す一部断面図Partial sectional view showing a semiconductor element

符号の説明Explanation of symbols

１ 配線基板
２ 半導体素子
２ａ Ｓｉチップ
２ｂ 層間絶縁膜
２ｃ アルミ配線
２ｄ パッシベーション膜
２ｅ Ａｌパッド
２ｆ ポリイミド膜
２ｇ Ｃｕ配線
２ｈ Ｃｕポスト
２ｉ 樹脂封止部
１０ 基板本体
１１ ベースフィルム
１２ 第１銅箔配線
１３ 第２銅箔配線
１４ 第１カバーフィルム
１５ 第２カバーフィルム
１６ スルーホール電極
２０ ＦＰＣ補強板
２１ 切欠部
２１ａ 内周壁面 DESCRIPTION OF SYMBOLS 1 Wiring board 2 Semiconductor element 2a Si chip 2b Interlayer insulation film 2c Aluminum wiring 2d Passivation film 2e Al pad 2f Polyimide film 2g Cu wiring 2h Cu post 2i Resin sealing part 10 Substrate body 11 Base film 12 1st copper foil wiring 13 1st 2 Copper foil wiring 14 1st cover film 15 2nd cover film 16 Through-hole electrode 20 FPC reinforcement board 21 Notch part 21a Inner peripheral wall surface

Claims (3)

電子部品がアンダーフィル材を介在させて基板本体上に実装される配線基板において、
前記電子部品が搭載される範囲を切り欠いた切欠部が形成されたシート状部材が前記基板本体上に設けられていることを特徴とする配線基板。 In wiring boards where electronic components are mounted on the board body with an underfill material interposed,
A wiring board, wherein a sheet-like member having a cutout portion formed by cutting out a range in which the electronic component is mounted is provided on the substrate body. 前記シート状部材は、樹脂製板材である請求項１記載の配線基板。 The wiring board according to claim 1, wherein the sheet-like member is a resin plate material. 前記基板本体は、可撓性を有するフレキシブル基板である請求項１または２記載の配線基板。 The wiring substrate according to claim 1, wherein the substrate body is a flexible flexible substrate.
JP2008190578A 2008-07-24 2008-07-24 Wiring substrate Pending JP2010028003A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008190578A JP2010028003A (en) 2008-07-24 2008-07-24 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008190578A JP2010028003A (en) 2008-07-24 2008-07-24 Wiring substrate

Publications (1)

Publication Number Publication Date
JP2010028003A true JP2010028003A (en) 2010-02-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008190578A Pending JP2010028003A (en) 2008-07-24 2008-07-24 Wiring substrate

Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113225899A (en) * 2021-04-28 2021-08-06 广州立景创新科技有限公司 Electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113225899A (en) * 2021-04-28 2021-08-06 广州立景创新科技有限公司 Electronic device

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