JP2010027801A - Cof tape, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a COF tape which does not thicken cross-sections of wiring and an Au bump made when bonded to a semiconductor chip by Au-Sn eutectic bonding, and accordingly, does not narrow a space between wirings. <P>SOLUTION: The COF tape has a wiring pattern 2 made of copper by a subtractive method on one surface of an insulating tape base 1, and the wiring 3 formed by etching is sectioned in a suitable trapezoid shape to secure necessary size precision of a top width T of the wiring. The number of etching factors Ef of the wiring pattern 2 in the subtractive method is 2 to 4, the top width T of the wiring 3 of the wiring pattern 2 is 2 to 6 μm, and a wiring pitch is ≤30 μm. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a COF (Chip On Film) tape in which a copper wiring pattern is formed on one surface of an insulating tape substrate by a subtractive method and a method for manufacturing the same.

  Generally, a COF tape, which is one of electronic component materials on which a semiconductor chip is mounted, is configured by forming a copper wiring pattern on one surface of an insulating tape base material such as polyimide by a subtractive method. When an electronic component is assembled using this COF tape, the semiconductor chip electrode bumps are directly connected to the wiring of the copper wiring pattern formed on one surface of the insulating tape substrate, and the semiconductor chip is mounted. Is called. Since most of the electrode bumps of the semiconductor chip are Au bumps, the bonding between the wiring and the electrode bumps described above is Au / Sn, which has a higher bonding temperature than solder and can be stably bonded at a relatively low temperature. Eutectic bonding is used. Correspondingly, the surface of the wiring of the COF tape is usually subjected to Sn plating.

  On the other hand, with the reduction in size and weight, higher functionality, and higher density of electronic components on which semiconductor chips are mounted, the wiring patterns of COF tapes are being made finer.

  There are mainly two methods for making this fine wiring.

  One of them is (1) a subtractive method in which a wiring pattern is formed by etching using an etching solution. In this method, since it is inevitable that the cross-sectional shape of the wiring becomes trapezoidal due to side etching, which is a phenomenon peculiar to etching, etching is always performed in consideration of an etching factor (Ef) representing the degree of side etching. In the etching considering Ef, in order to ensure the miniaturization of the wiring and the required dimensional accuracy, the greatest countermeasure is to reduce the thickness of the copper provided for forming the wiring. For this reason, in the subtractive method, the thickness of copper is reduced as much as possible. FIG. 4 shows an example of a COF tape in which a copper wiring pattern 2 is formed on one side of an insulating tape substrate 1 made of polyimide by a subtractive method. According to this figure, it can be seen that in the subtractive method, the cross-sectional shape of the wiring 3 of the wiring pattern 2 becomes trapezoidal by side etching. The COF tape has a two-layer structure having no adhesive between the wiring 3 and the insulating tape substrate 1. Here, the etching factor (Ef) will be described with reference to FIG. 4. Ef is a value representing the degree of side etching, and Ef = (2 × wiring height H) ÷ (wiring bottom width B) -It is calculated | required from the formula of the top width T of wiring. Therefore, if the wiring height (that is, the copper thickness) H is constant, the side etching rate decreases as the value of Ef increases.

  The other is (2) a semi-additive method in which a wiring pattern is formed by plating or the like. In this method, it is not necessary to consider Ef, and by using the mask together, the cross-sectional shape of the wiring can be made into a rectangular shape with the side surfaces cut vertically, so that the miniaturization of the wiring and the required dimensional accuracy can be achieved. It is easy to secure.

  However, in the case of the former (1) subtractive method, the etching rate is very fast by shower etching in which an etching solution is jetted from a nozzle. Therefore, in diffusion-controlled etching using a normal etching solution, the insulating tape substrate When the dimensions such as the thickness, copper thickness, and wiring pitch become small values close to the limit, it becomes extremely difficult to control the etching due to the manufacturing method. As a result, it becomes difficult to ensure the dimensional accuracy of the wiring formed by etching. Specifically, for example, when the thickness of the insulating tape substrate is 40 μm, the thickness of copper is 12 μm to 8 μm, and the wiring pitch is 30 μm or less, the above-mentioned difficult problems are likely to occur, and the wiring is chipped or thinned. Or the thickness of the wiring is significantly reduced. The value of the wiring pitch of 30 μm seems to be a limit value that can ensure the dimensional accuracy of the wiring by mask design. As a result, for example, when etching becomes excessive, the cross-sectional shape of the wiring that should be trapezoidal becomes a triangular shape, and it becomes difficult to ensure the top width of the wiring with the required dimensional accuracy. In this respect, the latter (2) semi-additive method makes it easy to make the wiring finer and ensure the required dimensional accuracy in terms of the manufacturing method.

  However, in the case of the latter (2) semi-additive method, Au / Sn eutectic bonding is used for bonding the wiring and Au bump described above. In this Au / Sn eutectic bonding, a heating tool is used. When the bonding part is pressurized and heated, Sn of Sn plating previously applied to the wiring surface melts and reacts with the Au bump Au at the eutectic temperature to form an Au / Sn eutectic alloy layer at the bonding interface To do. At the same time, Sn that does not contribute to the formation of the Au / Sn eutectic alloy layer forms a fillet on the side surfaces of the wiring and Au bump after reflow. While this fillet contributes to stabilization of the bonding between the wiring and the Au bump, it results in thickening the cross section of the wiring and the Au bump. In other words, in the case of the semi-additive method, the fact that the cross-sectional shape of the wiring is a rectangular shape adversely affects the result, and the fillet formed on the side surface of the wiring thickens the cross-section of the wiring, thereby reducing the wiring spacing. Since it becomes narrow, the problem of a short circuit arises. The same problem occurs with Au bumps. In addition, the semi-additive method generally has a high process cost and has problems in terms of productivity and yield. FIG. 5 shows an example in which Au / Sn eutectic bonding is performed using the COF tape shown in FIG. 4 manufactured by the subtractive method, but the wiring 3 and Au bump 4 having a trapezoidal cross section. The formation state of the Au / Sn eutectic alloy layer 5 and the fillet 6 formed when Au / Sn eutectic bonding is performed is shown. 7 is a semiconductor chip. According to FIG. 5, it can be seen that the fillet 6 formed on the side surface of the wiring 3 results in thickening the cross sections of the wiring 3 and the Au bump 4. In the case of the semi-additive method, the thickness is further increased, and the wiring interval and Au bump interval become so narrow that they become problems.

  FIG. 2 shows the cross-sectional shape of the wiring pattern formed by the semi-additive method and the subtractive method, (a) shows the cross-sectional shape of the wiring pattern formed by the semi-additive method, and (b) shows the subtractive method. The cross-sectional shape of the wiring of the wiring pattern formed by the method is shown when it is excessively etched. In addition, (c) shows the cross-sectional shape of the wiring of the wiring pattern which concerns on embodiment of this invention mentioned later. Both are schematic views. Also in this FIG. 2, 1 shows an insulating tape base material, 3 shows copper wiring.

  As a related prior art, the method described in Patent Document 1 targets a TAB (Tape Automated Bonding) tape in which a copper wiring pattern is formed on one side or both sides of an insulating tape substrate by a subtractive method. The thin TAB tape wiring pattern is to be made into a fine wiring by using thin copper. The point is to use a thin copper foil with a thickness of 5 μm or more and 10 μm or less, whereby the bottom width of the wiring of the wiring pattern is 10 μm or more and 20 μm or less, and the wiring interval (space) on the bottom side of the wiring is 10 μm or more and 20 μm or less. A method of forming a desired wiring pattern is proposed.

JP 2007-68803 A

  As described above, when the wiring pattern is finely formed on the COF tape by the subtractive method, the dimensions of the insulating tape base material, the copper thickness, the wiring pitch, etc. are small values close to the limits. Then, because of the manufacturing method, it becomes difficult to control the etching, and it becomes difficult to ensure the dimensional accuracy of the wiring. As a result, for example, if etching is excessive, the cross-sectional shape of the wiring that should be trapezoidal becomes a triangular shape, and it becomes difficult to ensure the top width of the wiring with the required dimensional accuracy. Further, when the wiring and the Au bump are joined, the top of the wiring may bite into the Au bump, and the cross section of the Au bump may be thickened, which may cause a short circuit problem.

  At the same time, the wiring having a triangular cross section is not stable when pressed against the Au bump, and the wiring may fall. Furthermore, when the cross-sectional shape of the wiring is triangular, the surface area of the wiring is small, so that it is difficult to form a fillet at the time of Au / Sn eutectic bonding, and there is a possibility that the bonding strength between the wiring and the Au bump is lowered. There is sex.

  In addition, when the wiring pattern of the COF tape is made fine by the semi-additive method, there is no problem of side etching, so that fine wiring is easy, but the cross-sectional shape of the wiring has a vertical side surface. The fundamental problem is the cut rectangular shape, and this causes the formation of fillets during Au / Sn eutectic bonding to result in thickening of the cross sections of the wiring and Au bumps, respectively. . As a result, the wiring interval becomes narrow, which causes a short circuit problem and decreases the reliability of the electronic component. From this point, if it is limited to the COF tape, there is a problem in the method of forming the fine wiring pattern by the semi-additive method, and it cannot be said that it is a preferable method.

  In short, the method described in Patent Document 1 promotes the miniaturization of a wiring pattern using a thin copper foil having a thickness of 5 μm to 10 μm. In this method, for miniaturization, the bottom width of the wiring and the wiring interval (space) on the bottom side of the wiring are not only ensured with a desired dimensional accuracy, but the top width of the wiring is not ensured with a necessary dimensional accuracy. . Further, the present invention is not intended for the COF tape, and does not matter the reliability of bonding between the wiring and the electrode bump of the semiconductor chip.

  Therefore, the object of the present invention is based on the premise that the wiring pattern is miniaturized by the subtractive method, and the cross-sectional shape of the wiring formed by etching is made an optimal trapezoidal shape without making it a triangular shape. Therefore, the top width of the wiring is ensured to the required dimensional accuracy, and at the same time, the trapezoidal shape effect does not increase the cross section of the wiring and the Au bump at the time of bonding to the semiconductor chip by Au / Sn eutectic bonding, And it is providing the COF tape which can improve the reliability of joining with a semiconductor chip, and its manufacturing method, without narrowing wiring space | interval by this.

  In order to achieve the above object, the invention of claim 1 is a COF tape in which a copper wiring pattern is formed on one surface of an insulating tape base material by a subtractive method, and an etching factor in the subtractive method is 2 or more and 4 or less. And a top width of the wiring of the wiring pattern is 2 μm or more and 6 μm or less, and a wiring pitch is 30 μm or less.

  The invention according to claim 2 provides the COF tape according to claim 1, wherein the copper has a thickness of 3 μm to 12 μm.

  A third aspect of the present invention provides the COF tape according to the first or second aspect, wherein a wiring interval (space) on the bottom side of the wiring of the wiring pattern is 15 μm or less.

  According to the COF tape of claims 1 to 3, a fine wiring pattern having a desired dimensional accuracy in which an etching factor is 2 or more and 4 or less, a top width of wiring is 2 μm or more and 6 μm or less, and a wiring pitch is 30 μm or less. By forming such a fine wiring pattern, it is possible to improve the reliability of bonding with the Au bump, particularly by setting the top width of the wiring to 2 μm or more and 6 μm or less. By setting the wiring pitch to 30 μm or less, it is possible to meet the demand for fine wiring patterns required for liquid crystal televisions, for example.

  The invention of claim 4 is a method of manufacturing a COF tape in which a copper wiring pattern is formed on one surface of an insulating tape base material by a subtractive method, and the etching solution used in the subtractive method has a viscosity and By using an etching solution containing an additive for reducing the specific gravity, the etching factor in the subtractive method is 2 or more and 4 or less, the top width of the wiring of the wiring pattern is 2 μm or more and 6 μm or less, and the wiring pitch is 30 μm or less. A method for producing a COF tape is provided.

  The invention according to claim 5 provides the method for producing a COF tape according to claim 4, wherein the copper has a thickness of 3 μm or more and 12 μm or less.

  The invention according to claim 6 provides the method for producing a COF tape according to claim 4 or 5, wherein a wiring interval (space) on the bottom side of the wiring of the wiring pattern is 15 μm or less.

  According to the method for producing a COF tape of claims 4 to 6, by using a specific etching solution containing an additive that lowers the viscosity and specific gravity of the etching solution, the etching factor is set to an optimum range of 2 or more and 4 or less. Etching makes it possible to easily form a fine wiring pattern having a desired dimensional accuracy with a wiring top width of 2 μm or more and 6 μm or less and a wiring pitch of 30 μm or less, and by forming such a fine wiring pattern, When the top width of the wiring is 2 μm or more and 6 μm or less, the reliability of bonding with the Au bump can be improved, and when the wiring pitch is 30 μm or less, wiring required for, for example, a liquid crystal television or the like It is possible to easily manufacture a COF tape that can respond to the fine wiring of patterns.

  Here, in the present invention, the reason why the top width of the wiring is 2 μm or more and 6 μm or less is that if the top width of the wiring is less than 2 μm, the surface area of the wiring becomes small due to the surface shape. At this time, it is difficult to form a fillet, and the bonding strength between the wiring and the Au bumps cannot be ensured. If the top width of the wiring exceeds 6 μm, the etching factor (Ef) becomes relatively large when the wiring pitch is 30 μm or less with a constant copper thickness, and stable etching cannot be performed. This is because the yield of the product decreases.

  In the present invention, the reason why the wiring pitch is set to 30 μm or less is to meet the demand for finer wiring patterns required for liquid crystal televisions, for example. Note that the cross-sectional shape of the wiring when the wiring pitch is 30 μm is an ideal shape with a wiring width of 15 μm and a wiring interval of 15 μm in the case of the semi-additive method. Etching needs to be taken into consideration. As a result, when the top width of the wiring is 2 μm or more and 6 μm or less, the trapezoidal shape in which the wiring interval on the bottom side is 15 μm is an ideal shape.

  According to the COF tape of the present invention and the manufacturing method thereof, it is premised on the miniaturization of the wiring pattern by the subtractive method, and the optimal cross-sectional shape of the wiring formed by etching is not triangular. The trapezoidal shape ensures the top width of the wiring with the required dimensional accuracy. At the same time, due to the trapezoidal shape effect, the cross-section of the wiring and the Au bumps is bonded to the semiconductor chip by Au / Sn eutectic bonding. The reliability of bonding to the semiconductor chip can be improved without increasing the thickness and without reducing the wiring interval.

  A preferred embodiment of the present invention will be described below in detail with reference to the accompanying drawings.

  First, in the present invention, in order to ensure a desired dimensional accuracy in which the wiring top width is 2 μm or more and 6 μm or less in the range where the wiring pitch of the wiring pattern formed by etching is 30 μm or less, the thickness is several μm or less. Consider whether you must use copper. The thickness of this copper varies depending on the etching factor (Ef), but Ef itself has its upper and lower limits. That is, if Ef is too small, it is difficult to make fine wiring itself. On the other hand, if Ef is too large, stable etching cannot be performed due to problems such as deterioration of the etching solution, and the yield of the product is deteriorated. Moreover, manufacturing becomes difficult. As a result, the range of Ef that is effective and preferable for implementation can be set to 2 or more and 4 or less. FIG. 1 shows that the wiring pitch is 30 μm or less, particularly the practically usable wiring pitch of 10 μm or more and 30 μm or less is the proper range, and the top width of the wiring is 2 μm or more and 6 μm or less is the proper range. By changing, the thickness of copper that can be used in relation to Ef was experimentally observed.

  FIG. 1A shows a case where Ef = 1.0, and the usable copper thickness used for the experiment is 3 μm and 5 μm with respect to the appropriate range of the above-described wiring pitch and wiring top width. It can be seen that copper having a thickness of 8 μm cannot be used. However, the copper thicknesses of 3 μm and 5 μm are extremely thin values and are not practical because the application range is extremely limited.

  FIG. 1B shows a case where Ef = 2.0, and the usable copper thickness used in the experiment is 3 μm and 5 μm with respect to the appropriate range of the above-described wiring pitch and wiring top width. 8 μm, and it can be seen that copper having a thickness of 12 μm cannot be substantially used.

  FIG. 1C shows a case where Ef = 3.0, and the usable copper thickness used in the experiment is 3 μm and 5 μm with respect to the appropriate range of the above-described wiring pitch and wiring top width. 8 μm and 12 μm, and any thickness of copper can be used.

  FIG. 1D shows a case where Ef = 4.0, and the usable copper thickness used in the experiment is 3 μm and 5 μm with respect to the appropriate ranges of the wiring pitch and the top width of the wiring. 8 μm and 12 μm, and any thickness of copper can be used.

  FIG. 1E shows a case where Ef = 5.0, and the usable copper thickness used in the experiment is 3 μm and 5 μm with respect to the appropriate range of the above-described wiring pitch and wiring top width. 8 μm and 12 μm, and any thickness of copper can be used. However, since Ef = 5.0 is too large, as described above, stable etching cannot be performed due to problems such as deterioration of the etching solution, the yield of the product is deteriorated, and the manufacturing becomes substantially difficult to be employed.

  As a result of the experiment, the effective range of Ef for implementation with respect to the appropriate range of the above-described wiring pitch and wiring top width is 2 or more and 4 or less, and the copper thickness usable in this range is 3 μm. It is 12 μm or less. In particular, the preferred copper thickness for practical use is 8 μm or more and 12 μm or less.

  Next, FIG. 2C schematically shows the cross-sectional shape of the wiring of the wiring pattern of the COF tape according to one embodiment of the present invention. In FIG. 2, the COF tape is obtained by forming a copper wiring pattern 2 on one side of an insulating tape substrate 1 made of polyimide by a subtractive method, and the etching factor in the subtractive method is 2 or more and 4 or less. The top width of the wiring 3 of the wiring pattern 2 is 2 μm or more and 6 μm or less, and the wiring pitch is 30 μm or less. The wiring 3 has a copper thickness of 3 μm or more and 12 μm or less, and a wiring interval (space) on the bottom side of the wiring 3 is 15 μm or less. In this embodiment, the COF tape has a two-layer structure having no adhesive between the wiring 3 and the insulating tape substrate 1, but may have a three-layer structure having an adhesive between the two.

  Next, the manufacturing method of the above-described COF tape will be described. An etching solution containing an additive that lowers the viscosity and specific gravity of the etching solution is used as the etching solution used in the subtractive method, and the etching factor in the subtractive method is 2 or more. Etching regulated to be 4 or less is performed. Thereby, a fine wiring pattern having the top width and wiring pitch of the wiring described above can be easily formed. In the etching using the etching solution containing the above-described additive, the etching using the normal etching solution is called diffusion-controlled etching, whereas it can be called reaction-controlled etching. In this reaction-controlled etching, the concentration control of the additive and the temperature control of the etching solution are very important, and the etching factor can be controlled to some extent by appropriately performing these. This facilitates the etching operation and can solve the problem of excessive etching. As shown in FIG. 2C, the cross-sectional shape of the wiring pattern formed by this method is formed with a desired dimensional accuracy such that the top width of the wiring is 2 μm to 6 μm and the wiring pitch is 30 μm or less. Ideal trapezoidal shape.

  For reference, FIG. 3A shows a joining state when the wiring 3 of the wiring pattern and the Au bump 4 of the semiconductor chip 7 are joined using the COF tape of FIG. 2C.

  For comparison, FIG. 3B shows a bonding state when bonding the wiring 3 of the wiring pattern and the Au bump 4 of the semiconductor chip 7 using a conventional COF tape formed by a semi-additive method. .

Example 1
A 38 μm thick Kapton EN made by Sumitomo Metal Mining Co., Ltd. was used as the insulating tape base material. After copper was thinly formed by sputtering, copper plating was performed to form a copper layer having a thickness of 8 μm. The resist was applied and exposed and developed using a photomask, and the copper layer was etched using the developed photoresist as an etching mask. Etching is performed using a reaction-controlled etching solution containing an additive that lowers the viscosity and specific gravity of the etching solution, and the etching nozzle pressure is 1.2 kgf / cm ² or more, and the etching is performed for 60 seconds or less. Etching was performed in time. In addition, as said additive, a low concentration oxidizing agent can be used, for example. By this method, various etchings were performed with different etching factors to form copper wiring patterns. Etching factors were performed in three ways: Ef = 2.0, 3.0, and 4.0.

  As a result, when the wiring pitch is 30 μm or less and the top width of the wiring exceeds 6 μm, the etching factor has to be relatively increased, and etching becomes difficult, and the wiring is chipped, thinned, thickened, etc. It was confirmed that the dimensional accuracy deteriorates and the product yield also deteriorates, such as an increase in defects.

  On the other hand, when the top width of the wiring was 2 μm or more and 6 μm or less, there was no problem and the product yield was good.

  Next, Sn plating is applied to the surface of the wiring of the wiring pattern to a thickness of 0.7 μm, and after manufacturing the COF tape, bonding with the Au bump of the semiconductor chip is performed using a tool heated to 450 ° C. went. As a result, when the top width of the wiring is less than 2 μm, the surface area of the wiring is reduced, so that a fillet is not sufficiently formed during Au / Sn eutectic bonding, and the bonding strength between the wiring and the Au bump is reduced. It was confirmed that there was a problem in the reliability of bonding.

  On the other hand, when the top width of the wiring is 2 μm or more and 6 μm or less, the fillet is formed, but the cross section of the wiring and the Au bump is not thick enough to cause a problem. Was confirmed.

  In addition, in an attempt, another etching solution containing a special agent (ADEKA Adeka Kermica TFE-3000, Electronic Materials 2006.10.October, P119 to P123) is used, and the etching factor is increased to increase the cross-sectional shape of the wiring. When it was formed in a trapezoidal shape close to a rectangular shape, it was confirmed that when the top width of the wiring exceeds 6 μm, the formation of fillets is already a problem, that is, the cross section of the wiring and the Au bump becomes thick enough to cause a problem. It was done. For this reason as well, the top width of the wiring needs to be 6 μm or less.

(Example 2)
A COF tape was manufactured by etching in the same manner as in Example 1 except that the thickness of copper was 12 μm. Similarly, Au / Sn eutectic bonding was performed. Also in this case, the same result as in Example 1 was confirmed.

It is explanatory drawing which looked at the copper thickness which can be used in relation to Ef by experiment by changing the value of Ef with respect to the appropriate range of wiring pitch and wiring top width, (a) is Ef = 1. When 0, (b) is Ef = 2.0, (c) is Ef = 3.0, (d) is Ef = 4.0, (e) is Ef = 5.0 It is explanatory drawing in each case. It is a schematic explanatory drawing which shows the cross-sectional shape of the wiring of a wiring pattern, (a) is the cross-sectional shape of the wiring of the wiring pattern formed by the semi-additive method, (b) is the wiring of the wiring pattern formed by the subtractive method FIG. 4C is an explanatory view showing a cross-sectional shape of a wiring pattern according to an embodiment of the present invention. FIG. It is explanatory drawing which shows the joining condition at the time of joining the wiring of a wiring pattern, and Au bump of a semiconductor chip, (a) is related with embodiment of this invention, (b) is related with the conventional semiadditive method It is. It is explanatory drawing which shows an example of the conventional COF tape manufactured by the subtractive method. It is explanatory drawing which shows each formation condition of the Au * Sn eutectic alloy layer and the fillet at the time of performing Au * Sn eutectic bonding using the conventional COF tape.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulation tape base material 2 Wiring pattern 3 Wiring 4 Au bump 5 Au * Sn eutectic alloy layer 6 Fillet 7 Semiconductor chip

Claims (6)

  A COF tape in which a copper wiring pattern is formed on one surface of an insulating tape substrate by a subtractive method, the etching factor in the subtractive method is 2 or more and 4 or less, and the wiring top width of the wiring pattern is A COF tape characterized by being 2 μm or more and 6 μm or less and a wiring pitch of 30 μm or less.   2. The COF tape according to claim 1, wherein the copper has a thickness of 3 μm to 12 μm.   The COF tape according to claim 1 or 2, wherein a wiring interval (space) on a bottom side of the wiring of the wiring pattern is 15 µm or less.   A method of manufacturing a COF tape in which a copper wiring pattern is formed on one surface of an insulating tape substrate by a subtractive method, and includes an additive for reducing the viscosity and specific gravity of the etchant as an etchant used in the subtractive method By using an etching solution, a COF tape having an etching factor of 2 to 4 in the subtractive method, a top width of wiring of the wiring pattern of 2 μm to 6 μm, and a wiring pitch of 30 μm or less is manufactured. A method for producing a COF tape characterized by the above.   The method for producing a COF tape according to claim 4, wherein the copper has a thickness of 3 μm or more and 12 μm or less.   The method for producing a COF tape according to claim 4 or 5, wherein a wiring interval (space) on the bottom side of the wiring of the wiring pattern is 15 µm or less.

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