JP2010021366A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce resistance value of a wiring pattern having damascene structure and a bent portion. <P>SOLUTION: A semiconductor device includes a substrate including an active element and multilayer wiring structure which is formed above the substrate and which includes a wiring layer and an interlayer dielectric. The wiring layer has the wiring pattern of the damascene structure formed in the interlayer dielectric, the wiring pattern includes a plurality of extension portions with first wiring width extending in respective directions and a plurality of bent portions connecting two of the plurality of extension portions, wherein at least one of the plurality of bent portions has second wiring width larger than √2 time as large as the first wiring width. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a multilayer wiring structure.

  In today's semiconductor integrated circuit devices, an enormous number of semiconductor elements are formed on a common substrate, and a multilayer wiring structure is used to interconnect them.

In a multilayer wiring structure, an interlayer insulating film in which a wiring pattern constituting a wiring layer is embedded is laminated.
In such a multilayer wiring structure, the lower wiring layer and the upper wiring layer are connected to each other by a via contact formed in the interlayer insulating film.

  Particularly in recent ultra-miniaturized and ultra-high-speed semiconductor devices, a low dielectric constant film (so-called low-k film) is used as an interlayer insulating film in order to alleviate the problem of signal delay (RC delay) in a multilayer wiring structure. At the same time, a low resistance copper (Cu) pattern is used as a wiring pattern.

In such a multilayer wiring structure in which the Cu wiring pattern is embedded in the low dielectric constant interlayer insulating film, patterning by dry etching of the Cu layer is difficult, so a wiring groove or a via hole is previously formed in the interlayer insulating film. The damascene method or dual damascene method is used. In the damascene method or dual damascene method, the wiring trench or via hole formed in this way is filled with a Cu layer, and then the excess Cu layer on the interlayer insulating film is removed by chemical mechanical polishing (CMP).
JP-A-6-349947 JP 2006-319040 A Japanese Patent Laid-Open No. 4-284737

  In today's miniaturized semiconductor devices, the multilayer wiring structure is also miniaturized, and accordingly, the wiring width of the wiring pattern formed on the interlayer insulating film in the multilayer wiring structure is reduced.

  FIG. 1 is a diagram showing the relationship between the wiring width and resistivity of a Cu wiring pattern formed by the damascene method. However, in FIG. 1, the thickness of the Cu wiring pattern is kept constant at 250 nm.

  Referring to FIG. 1, it can be seen that the resistivity of the Cu wiring pattern increases rapidly when the wiring width is 1000 nm or less, particularly 100 nm or less. This is because the bulk resistivity of Cu does not change as shown in FIG. 1, but the influence of the surface increases due to the reduction of the wiring width, and the Cu crystal grains in the Cu pattern constituting the Cu wiring increase. It is considered that the size also decreases as the wiring width decreases, and as a result, the surface scattering component and the grain boundary scattering component of the resistivity increase.

  Incidentally, in general, the wiring pattern in the multilayer wiring structure has few linear patterns A extending linearly over a long distance as shown in FIG. 2, and a plurality of extending portions B1 extending in each direction are repeatedly bent. And a large number of bent patterns B each having a plurality of bent portions B2 connecting two of the plurality of extending portions.

  The inventor of the present invention investigated the relationship between the resistivity of the wiring pattern and the number of bent portions included in the wiring pattern for the Cu wiring pattern formed by the damascene method in the research that is the basis of the present invention. As shown in FIG. 3, it has been found that the relationship in which the wiring resistivity increases substantially linearly with the number of bent portions is established. The relationship shown in FIG. 3 is a result of a Cu wiring pattern having a constant wiring width of 0.17 μm, a thickness of 0.15 μm, and a total extension of 1.5 mm.

  In the damascene structure, a wiring pattern previously formed in an interlayer insulating film is filled and a wiring pattern is formed by an electrolytic plating method or the like. The relationship in FIG. For example, the growth of Cu crystals in a pair of extending portions B1 adjacent to the bent portion B2 interferes with the effect of interfering with the growth of Cu crystals, and the particle size of metal crystals such as Cu constituting the wiring pattern is small. For this reason, it is suggested that the grain boundary scattering component explained in FIG. 1 is increased. Such a problem is not caused by the surface of a Cu wiring pattern having a wiring width larger than 1000 nm, but is considered to be a serious problem in a wiring pattern having a wiring width of 1000 nm or less, particularly 100 nm or less.

  FIG. 4 shows the relationship between the number of bent portions and the average grain boundary distance d obtained for the Cu wiring pattern having a width of 0.17 μm described in FIG. Here, as shown in FIGS. 5A and 5B, the average grain boundary interval d is a value of Cu crystal along the current path indicated by the arrow in the Cu wiring pattern 2 having a damascene structure formed in the insulating film 1. The average interval between the grain boundary GB and the next grain boundary GB is shown. 5A is a plan view and FIG. 5B is a cross-sectional view.

  Referring to FIG. 4, it can be seen that as the number of bent portions increases, the average grain boundary distance d decreases, and the grain size of the Cu crystals in the Cu wiring pattern 2 decreases. This indicates that a decrease in the Cu particle size occurs at the bent portion B2 in FIG. When the grain size of the Cu crystal decreases, the grain boundary scattering component described with reference to FIG. 1 increases and the resistivity of the Cu wiring pattern 2 increases.

  According to one aspect, a semiconductor device includes a substrate including an active element, and a multilayer wiring structure formed above the substrate and including a wiring layer and an interlayer insulating film, and the wiring layer is formed in the interlayer insulating film. A wiring pattern having a damascene structure formed on the plurality of extending portions extending in each direction with a first wiring width, and two of the plurality of extending portions, respectively. , And at least one of the plurality of bent portions has a second wiring width larger than √2 times the first wiring width.

  According to the present invention, by locally increasing the wiring width of the bent portion, the resistivity can be reduced at the bent portion, and the resistivity of the entire wiring pattern can be reduced.

[First Embodiment]
FIG. 6 is a plan view showing the Cu wiring pattern 10 according to the first embodiment of the present invention, and FIG. 7 is an enlarged plan view of a part of the Cu wiring pattern 10 of FIG. However, in FIGS. 6 and 7, the same reference numerals are assigned to the portions corresponding to the portions described above, and the description thereof is omitted. In the figure, arrows and e- indicate electron flow.

  Referring to FIGS. 6 and 7, the Cu wiring pattern 10 according to the present embodiment is also formed by repeating the extending portion B1 and the bent portion B2 similarly to the Cu wiring pattern of FIG. 2, and extends in the respective directions. A plurality of extending portions B1 and a plurality of bent portions B2 each connecting two of the plurality of extending portions are provided. Contacts C1 and C2 are formed at both ends of the Cu wiring pattern 10.

  In the present embodiment, the width W2 of the bent portion B2 is set to be larger than the width W1 of the extending portion, and in particular, set to be not less than √2 times the width W1. As a result, each of the bent portions B2 is formed with a wide square portion having one side W2.

  FIG. 8 is a sectional view taken along lines A-A ′ and B-B ′ of the Cu wiring pattern 10 of FIG.

  Referring to FIG. 8, both the extending portion B1 and the bent portion B2 are refractory metals such as Ta, Ti, W or the like in the wiring trench 11T formed in the interlayer insulating film 11 at the same depth. It includes a Cu pattern 10Cu formed by a damascene method through a barrier metal film 10BM made of nitride.

  Referring to the enlarged view of FIG. 7 again, in this embodiment, the bent portion B2 shown in FIG. 9 has a width W2 equal to the width W1 of the extended portion B1 as compared with the conventional wiring pattern. By setting the width W2 of the portion B2 to be equal to or larger than the width Wc of the diagonal region where the width of the electron passage region is maximum in the bent portion B2, an increase in resistivity in the bent portion B2 is avoided. Since the width Wc is Wc = √2 × W1 using the width W1, in this embodiment, the width W2 of the bent portion B2 is set to be more than √2 times the width W1 of the extended portion B1. Set.

  That is, according to this embodiment, the width of the entrance and the exit of the electron flow that flows into the bent portion B2 from the extending portion B1 and flows out to the next extending portion B1 is set to the bent portion in the conventional configuration of FIG. By setting it to be equal to or greater than the maximum width Wc of the portion B2, it is possible to avoid an increase in the wiring resistance of the entire wiring pattern accompanying an increase in the resistivity at the bent portion B2.

  10 shows the Cu wiring pattern 10 of FIGS. 6 and 7, wherein the total extension is set to 1.5 mm, the wiring width W1 of the extending portion B1 is set to 0.17 μm, and the wiring width W2 of the bent portion B2 is set to 0.23 μm. The wiring resistivity when the number of the bent portions B2 is changed between 500 and 3300 is set to the wiring resistivity when the wiring width of the bent portion B2 remains W1 as in the conventional case (FIG. 9). It is a figure shown in comparison with resistivity. In the experiment of FIG. 10, the distance L between the closest bent portions B2 shown in FIG. 7 is in the range of 0.45 μm to 3.0 μm.

  Referring to FIG. 10, it can be seen that, in the pattern of the present invention, the resistivity is surely reduced as compared with the conventional wiring pattern, and the change rate of the resistivity with respect to the number of bent portions is also reduced.

  That is, according to the present embodiment, it is possible to reduce the wiring resistance in a damascene multilayer wiring structure having a Cu wiring pattern.

  6 to 7, the wide portion formed in the bent portion B2 is not limited to a square, and may be square or circular as shown in FIGS. When the wide portion is square, the length of the short side thereof corresponds to the width W2, which is set to be not less than √2 times the width W1. Furthermore, as shown in FIG. 13, the wide part may be formed close to one side of the extending part B1. Further, as shown in FIG. 14, the wide portion may have a shape other than a square or a square.

  In the Cu wiring pattern of this embodiment, the wide portions in FIGS. 6 and 7 are preferably formed in all the bent portions, but may be omitted when it is difficult to form such wide portions. Is possible.

  In addition, when the configuration of the present embodiment is applied to a power wiring pattern, it is possible to effectively suppress electromigration that tends to occur in such a bent portion.

  The present invention is not limited to the Cu wiring pattern, and is also effective when the wiring groove is filled with copper, silver, gold, nickel, or an alloy thereof by electrolytic plating to form a wiring pattern.

  The present invention is effective in the case of a wiring width of 1000 nm or less, particularly a wiring width of 100 nm or less, in which the effect of the grain boundary scattering component becomes remarkable from the relationship of FIG.

[Second Embodiment]
Next, a method of manufacturing a semiconductor device according to the second embodiment using the Cu wiring pattern of the first embodiment for a multilayer wiring structure will be described with reference to FIGS.

  Referring to FIG. 15A, an element region 303 is defined by an element isolation region 302 on a silicon substrate 301. In the element region 303, a gate electrode is formed on the silicon substrate 301 via a gate insulating film 303I. 303G is formed. In the element region 303, a source diffusion region 303S and a drain diffusion region 303D are formed on both sides of the gate electrode 303G in the silicon substrate 301. The gate electrode 303G has a sidewall insulating film and is covered with an insulating film 304.

  An interlayer insulating film 310 is formed on the insulating film 304 via an etching stopper film 306 such as SiC or SiN. In the interlayer insulating film 310, Cu is formed in a wiring trench and a barrier metal film 311B. A wiring pattern 311 is embedded. The Cu wiring pattern 311 has a W (tungsten) plug 305 formed through a barrier metal film 305A in a contact hole 304V that penetrates the etching stopper film 306 and the insulating film 304 and exposes the drain diffusion region 303D. Thus, it is electrically connected to the diffusion region 303D.

  Next, as shown in FIG. 15B, interlayer insulating films 321 and 323 are alternately stacked on the structure of FIG. 15A via etching stopper films 320 and 322 made of SiC or SiN, and as shown in FIG. 15C. In addition, a wiring trench 325H is formed in the interlayer insulating film 323 so as to expose the etching stopper film 322. Further, a via hole 324H is formed in the etching stopper film 322 in the wiring groove 325H so as to expose the etching stopper film 320 covering the Cu wiring pattern 311B.

  Further, in the step of FIG. 15C, the exposed etching stopper films 322 and 320 at the bottom of the wiring groove 325H and the bottom of the via hole 324H are removed by etching, and the interlayer insulating film 321 and the bottom of the via hole 324H are removed at the bottom of the wiring groove 325H. Then, the Cu wiring pattern 311 is exposed.

  Further, the wiring trench 325H and the via hole 324H are filled with a Cu layer through a barrier metal film 325B, and an excess Cu layer on the interlayer insulating film 323 is combined with the barrier metal film 325 below the interlayer insulating film 323. Then, the Cu wiring pattern 325 and the Cu via plug 324 shown in FIG. 15D are continuously formed so as to fill the wiring groove 325H and the via hole 324H. .

  Also in the present embodiment, in the Cu wiring patterns 311 and 325, by forming the wide portions described in FIGS. 6 and 7 in the respective bent portions, even if there are a large number of bent portions in the wiring pattern, An increase in resistance value due to such a bent portion can be suppressed, and the operation speed of the semiconductor device is improved.

  In addition, when the configuration of the previous embodiment is applied to a power wiring pattern, it is possible to effectively suppress electromigration that tends to occur in such a bent portion.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A substrate including active elements;
A multilayer wiring structure formed above the substrate and including a wiring layer and an interlayer insulating film;
With
The wiring layer has a damascene wiring pattern formed in the interlayer insulating film,
The wiring pattern includes a plurality of extending portions extending in the respective directions with a first wiring width, and a plurality of bent portions respectively connecting two of the plurality of extending portions,
At least one of the plurality of bent portions has a second wiring width larger than √2 times the first wiring width.
(Appendix 2)
The semiconductor device according to claim 1, wherein the bent portion is a square portion having a side length of the second wiring width in the wiring pattern.
(Appendix 3)
The semiconductor device according to claim 1, wherein the bent portion is a circular portion having a diameter of the second wiring width in the wiring pattern.
(Appendix 4)
4. The semiconductor device according to claim 1, wherein all of the plurality of bent portions have the second wiring width.
(Appendix 5)
The semiconductor device according to claim 1, wherein the first wiring width is 1000 nm or less.
(Appendix 6)
The semiconductor device according to claim 1, wherein the first wiring width is 100 nm or less.
(Appendix 7)
The semiconductor device according to claim 1, wherein the wiring pattern is a power wiring pattern.

It is a figure which shows the relationship between the resistivity of Cu wiring, and wiring width. It is a figure which shows the example of the wiring pattern used in the multilayer wiring structure of a semiconductor device. It is a figure which shows the relationship between the resistivity of Cu wiring pattern, and the number of bending parts. It is a figure which shows the relationship between the average grain-boundary space | interval of Cu wiring pattern, and the number of bending parts. It is the top view and sectional drawing explaining an average grain boundary space | interval. It is a top view which shows the whole structure of Cu wiring pattern by the 1st Embodiment of this invention. It is a top view which shows a part of FIG. It is sectional drawing which shows a part of FIG. It is a figure which shows a comparative example. It is a figure explaining the effect of a 1st embodiment. It is a figure which shows one modification of 1st Embodiment. It is a figure which shows another modification of 1st Embodiment. It is a figure which shows the other modification of 1st Embodiment. It is a figure which shows the other modification of 1st Embodiment. FIG. 10 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the second embodiment; FIG. 11 is a diagram (part 2) illustrating a manufacturing process of the semiconductor device according to the second embodiment; FIG. 11 is a diagram (No. 3) for illustrating a manufacturing step of the semiconductor device according to the second embodiment; FIG. 14 is a diagram (No. 4) for illustrating a manufacturing step of the semiconductor device according to the second embodiment;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,11 Interlayer insulating film 2,10 Cu wiring pattern 10Cu Cu pattern 10BM Barrier metal film 11T, 310T, 323 Wiring groove 301 Silicon substrate 302 Element isolation region 303 Element region 303S Source diffusion region 303D Drain diffusion region 303G Gate electrode 303I Gate insulating film 304 Insulating film 304V Contact hole 306, 320, 322 Etching stopper film 310, 321, 323 Interlayer insulating film 311, 325 Cu wiring pattern 311B Barrier metal film 324H Via hole 324 Via plug B1 Extension part B2 Bending part C1, C2 Contact GB Grain boundary W1, W2, Wc Wiring width

Claims (5)

A substrate including active elements;
A multilayer wiring structure formed above the substrate and including a wiring layer and an interlayer insulating film;
With
The wiring layer has a damascene wiring pattern formed in the interlayer insulating film,
The wiring pattern includes a plurality of extending portions extending in the respective directions with a first wiring width, and a plurality of bent portions respectively connecting two of the plurality of extending portions,
At least one of the plurality of bent portions has a second wiring width larger than √2 times the first wiring width.   2. The semiconductor device according to claim 1, wherein the bent portion is a square portion having a side length of the second wiring width in the wiring pattern.   The semiconductor device according to claim 1, wherein the bent portion is a circular portion having a diameter of the second wiring width in the wiring pattern.   The semiconductor device according to claim 1, wherein all of the plurality of bent portions have the second wiring width.   The semiconductor device according to claim 1, wherein the first wiring width is 1000 nm or less.

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