JP2010019900A - Method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of driving a plasma display panel improving a dark contrast. <P>SOLUTION: A plasma display panel in which discharging cells are formed on respective intersection parts between a plurality of row electrode pairs bearing display lines and a plurality of column electrodes is driven as follow. That is, in an addressing step of each of a leading subfield in a unit display period in an image signal and a subsequent subfield succeeding the leading subfield, a writing address which sets each discharging cell selectively to the state of lighting mode is executed. Therein, in the addressing step of the leading subfield, scanning pulses are successively applied to one side row electrodes of respective row electrode pairs and a base pulse having a peak potential of the same polarity as the scanning pulse is applied to the other column electrodes of the respective row electrode pairs respectively, and thereby, the writing addressing discharging for setting the discharging cells selectively into the state of lighting mode is generated. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for driving a plasma display panel.

  At present, an AC type (AC discharge type) plasma display panel (hereinafter referred to as PDP) has been commercialized as a thin display device. In the PDP, two substrates, that is, a front transparent substrate and a rear substrate are arranged to face each other with a predetermined gap. On the inner surface of the front transparent substrate (surface facing the rear substrate) as a display surface, a plurality of row electrode pairs that are paired with each other and extend in the horizontal direction of the screen are formed. Furthermore, a dielectric layer covering each row electrode pair is formed on the inner surface of the front transparent substrate. On the other hand, on the back substrate side, a plurality of column electrodes extending in the vertical direction of the screen are formed so as to cross the row electrode pairs. When viewed from the display surface side, discharge cells corresponding to the pixels are formed at the intersections between the row electrode pairs and the column electrodes.

  In order to obtain halftone display luminance corresponding to the input video signal, gradation driving using the subfield method is performed on such a PDP.

  In gradation driving based on the subfield method, display driving is performed on a video signal for one field in each of a plurality of subfields to which the number of times (or periods) of light emission is assigned. In each subfield, an address process and a sustain process are executed sequentially. In the address process, a selective discharge is selectively generated between the row electrode and the column electrode in each discharge cell in accordance with the input video signal to form (or erase) a predetermined amount of wall charges. In the sustain process, only the discharge cells in which a predetermined amount of wall charges are formed are repeatedly discharged, and the light emission state associated with the discharge is maintained. Further, a reset process is executed prior to the address process in at least the first subfield. In such a reset process, the amount of wall charges remaining in all the discharge cells is initialized by causing a reset discharge between the paired row electrodes in all the discharge cells.

  Here, the reset discharge is a relatively strong discharge and has nothing to do with the content of the image to be displayed, so there is a problem that the light emission accompanying this discharge reduces the contrast of the image. . At this time, it is possible to suppress a decrease in contrast by weakening the reset discharge, but if the applied voltage is lowered to cause weak reset discharge, a discharge delay occurs, and all discharge cells are weakened. It is difficult to stably generate the reset discharge.

  Therefore, by attaching a magnesium oxide crystal that is excited by electron beam irradiation and emits cathodoluminescence light having a peak within a wavelength range of 200 to 300 nm to the surface of the dielectric layer covering the row electrode pair, the discharge delay time is reduced. A shortened PDP and a driving method thereof have been proposed (see, for example, Patent Document 1). According to such a PDP, since a weak reset discharge can be stably generated, it is possible to improve image contrast, particularly so-called dark contrast when displaying a dark image.

However, even if the reset discharge is weakened, it is difficult to further increase the dark contrast because the light emission associated with the discharge remains unchanged from all the discharge cells.
JP 2008-70442 A

An object of the present invention is to provide a method of driving a plasma display panel that can increase dark contrast.

  The method for driving a plasma display panel according to claim 1, wherein the first substrate and the second substrate are arranged to face each other, the plurality of row electrode pairs formed on the first substrate, and the plurality of columns formed on the second substrate. A discharge cell is formed at an intersection with an electrode, and a magnesium oxide crystal that emits cathode luminescence having a peak in a wavelength range of 200 to 300 nm when excited by an electron beam on the second substrate of the discharge cell. Driving a plasma display panel in which a phosphor layer including a secondary electron emission material including a body and a phosphor material is formed is driven by a plurality of subfields for each unit display period of a video signal. In the first subfield in the unit display period, a write address row for selectively setting each of the discharge cells to a lighting mode state. And a discharge light emission process for discharging only the discharge cells in the lighting mode, and in the subsequent subfield provided immediately after the first subfield, the write address process and the line A sustain process in which only a discharge cell in the lighting mode state is sustained by applying a sustain pulse to the electrode pair, and in the write address process of the first subfield, each of the row electrode pairs The discharge is performed by sequentially applying a scan pulse to one row electrode and applying a base pulse having a peak potential having the same polarity as the peak potential of the scan pulse to the other row electrode of each row electrode pair. A discharge for selectively setting the cell to the state of the lighting mode is generated.

  The driving method of the plasma display panel according to claim 11 is such that the first substrate and the second substrate are arranged to face each other, a plurality of row electrode pairs formed on the first substrate and a plurality of pairs formed on the second substrate. A discharge cell is formed at the intersection with the column electrode, and a plasma display panel in which a phosphor layer containing a phosphor material is formed on the second substrate of the discharge cell is provided for each unit display period of the video signal. A method of driving a plasma display panel in which gradation driving is performed using a plurality of subfields, wherein each of the discharge cells in each of the first subfield in the unit display period and the subsequent subfield provided immediately after the first subfield. A write address process for selectively setting the lighting mode to the lighting mode, and applying the sustain pulse to the row electrode pair A sustain process in which only the discharge cells in the state are subjected to a sustain discharge, and in the write address process of the subsequent subfield, a scan pulse is sequentially applied to one row electrode of each of the row electrode pairs. , Causing discharge for selectively setting the discharge cells to the lighting mode state, and sequentially scanning the other row electrode of each of the row electrode pairs in the write address process of the first subfield. An auxiliary scanning pulse having the same polarity as the peak potential of the pulse is applied, and the peak potential of the auxiliary scanning pulse is set to the same polarity side with respect to the potential applied to the one row electrode when the auxiliary scanning pulse is applied. .

  According to a thirteenth aspect of the present invention, there is provided a method for driving a plasma display panel, wherein a first substrate and a second substrate are arranged to face each other, a plurality of row electrode pairs formed on the first substrate and a plurality formed on the second substrate. A discharge cell is formed at the intersection with the column electrode, and oxidation is performed on the second substrate of the discharge cell to emit cathode luminescence having a peak in the wavelength range of 200 to 300 nm when excited by an electron beam. A plasma display panel in which a phosphor display layer including a secondary electron emission material including a magnesium crystal and a phosphor material is formed and driven in gray scale by a plurality of subfields for each unit display period of a video signal Each of the first subfield and the subsequent subfield provided immediately after the first subfield in the unit display period. Is a sustain process for sustaining only the discharge cells in the lighting mode by applying a sustain pulse to the row electrode pair, and a write address process for selectively setting each of the discharge cells to the lighting mode. In the write address step of the first subfield, a negative wall charge adjustment pulse is applied to one row electrode of the row electrode pair immediately before the first scan pulse is applied. However, a ground potential or negative wall charge adjustment pulse is applied to the other row electrode, and the sustain pulse is applied to the one row electrode in the sustain process of each of the first subfield and the subsequent subfield. However, the sustain discharge is performed only on the discharge cells in the lighting mode by setting the other row electrode to the ground potential. After crimping, a negative wall charge adjustment pulse is applied to the one row electrode.

  A plasma display panel in which discharge cells are formed at each intersection of a plurality of row electrode pairs and a plurality of column electrodes that carry display lines is driven as follows. That is, in the address process of each of the first subfield in the unit display period in the video signal and the subsequent subfield subsequent to this first subfield, the write address for selectively setting each discharge cell to the lighting mode state is executed. . Here, for the discharge cells set in the lighting mode state in the address process of the subsequent subfield, each of the leading and subsequent subfields is set in the lighting mode state in the address process of the leading subfield. As a result, a sustain discharge is continuously generated. Therefore, charged particles are supplied into each discharge cell along with the sustain discharge, so that subsequent discharge can occur even if charged particles are not supplied by reset discharge. It becomes.

  Further, in the address process of the first subfield, a scan pulse is sequentially applied to one row electrode of each row electrode pair, and a base pulse having a peak potential of the same polarity as the scan pulse is applied to the other row of each row electrode pair. By applying each to the electrodes, a write address discharge for selectively setting the discharge cells to the lighting mode is generated. According to such driving, it is possible to prevent erroneous discharge that is induced by the write address discharge and is generated between the row electrodes X and Y in the discharge cell. Therefore, in the address process of the next subsequent subfield, Address discharge is generated stably.

  Therefore, according to the present invention, it is possible to drive the PDP without causing erroneous discharge even if the reset discharge is eliminated to improve the dark contrast.

  FIG. 1 is a diagram showing a schematic configuration of a plasma display apparatus for driving a plasma display panel according to a driving method according to the present invention.

  As shown in FIG. 1, the plasma display device includes a PDP 50 as a plasma display panel, an X electrode driver 51, a Y electrode driver 53, an address driver 55, and a drive control unit 56.

The PDP 50 includes column electrodes D _{1 to} D _m arranged to extend in the vertical direction (vertical direction) of the two-dimensional display screen, and row electrodes X ₁ to X _m arranged to extend in the horizontal direction (horizontal direction). X _n and row electrodes _Y 1 to Y _n are formed. In this case, row electrode pairs (Y ₁ , X ₁ ), (Y ₂ , X ₂ ), (Y ₃ , X ₃ ),..., (Y _n , X _n ) that are paired with each other adjacent to each other. Are responsible for the first display line to the nth display line in the PDP 50, respectively. Each intersection of each display line and the column electrodes D ₁ to D _m, respectively (region surrounded by one-dot chain line in FIG. 1), the discharge cells PC serving as pixels are formed. That is, as shown in FIG. 1, the PDP 50 includes discharge cells PC _{1,1 to} PC _{1, m} belonging to the first display line, discharge cells PC _{2,1 to} PC _{2, m} belonging to the second display line,. ..., each of the discharge cells PCn _{, 1 to} PCn _{, m} belonging to the nth display line is arranged in a matrix.

  FIG. 2 is a front view schematically showing the internal structure of the PDP 50 as viewed from the display surface side.

  In FIG. 2, the crossing portions of three column electrodes D adjacent to each other and two display lines adjacent to each other are extracted and shown. 3 is a view showing a cross section of the PDP 50 taken along the line VV of FIG. 2, and FIG. 4 is a view showing a cross section of the PDP 50 taken along the line WW of FIG.

  As shown in FIG. 2, each row electrode X has a bus electrode Xb extending in the horizontal direction of the two-dimensional display screen and a T provided in contact with a position corresponding to each discharge cell PC on the bus electrode Xb. And a transparent electrode Xa having a letter shape. Each row electrode Y includes a bus electrode Yb extending in the horizontal direction of the two-dimensional display screen, and a T-shaped transparent electrode Ya provided in contact with a position corresponding to each discharge cell PC on the bus electrode Yb. Is composed of. The transparent electrodes Xa and Ya are made of a transparent conductive film such as ITO, and the bus electrodes Xb and Yb are made of a metal film, for example. As shown in FIG. 3, the row electrode X composed of the transparent electrode Xa and the bus electrode Xb and the row electrode Y composed of the transparent electrode Ya and the bus electrode Yb are arranged on the back side of the front transparent substrate 10 whose front side is the display surface of the PDP 50. Is formed. At this time, the transparent electrodes Xa and Ya in each row electrode pair (X, Y) extend to the paired row electrode side, and the top sides of the wide portions pass through the discharge gap g having a predetermined width. Facing each other. Further, on the back side of the front transparent substrate 10, a horizontal extension of the two-dimensional display screen extends between the row electrode pair (X, Y) and the row electrode pair (X, Y) adjacent to the row electrode pair. A black or dark light absorbing layer (light shielding layer) 11 is formed. Further, a dielectric layer 12 is formed on the back side of the front transparent substrate 10 so as to cover the row electrode pair (X, Y). As shown in FIG. 3, on the back side of the dielectric layer 12 (the surface opposite to the surface in contact with the row electrode pair), the light absorbing layer 11 and bus electrodes Xb and Yb adjacent to the light absorbing layer 11 are provided. A raised dielectric layer 12A is formed in a portion corresponding to the region where the and are formed.

  A magnesium oxide layer 13 is formed on the surfaces of the dielectric layer 12 and the raised dielectric layer 12A.

  The magnesium oxide layer 13 is excited by electron beam irradiation, and is a magnesium oxide crystal (hereinafter referred to as a secondary electron emission material) that emits CL (cathode luminescence) light having a peak within a wavelength of 200 to 300 nm, particularly 230 to 250 nm. , CL emission MgO crystal). This CL light-emitting MgO crystal is obtained by vapor-phase oxidation of magnesium vapor generated by heating magnesium. For example, a multi-crystal structure in which cubic crystals are fitted to each other, or a cubic single crystal structure is obtained. Have. The average particle diameter of the CL luminescent MgO crystal is 2000 angstroms or more (measurement result by BET method). In order to form a vapor phase magnesium oxide single crystal having a large average particle diameter of 2000 angstroms or more, it is necessary to increase the heating temperature for generating magnesium vapor. For this reason, the length of the flame in which magnesium reacts with oxygen becomes longer, and the temperature difference between the flame and the surroundings becomes larger. Many of them having an energy level corresponding to the peak wavelength (for example, around 235 nm and within 230 to 250 nm) are formed. Compared with a general gas phase oxidation method, the amount of magnesium evaporated per unit time is increased to increase the reaction area between magnesium and oxygen, and the gas generated by reacting with more oxygen is generated. The phase method magnesium oxide single crystal has an energy level corresponding to the above-described peak wavelength of CL emission. The magnesium oxide layer 13 is formed by adhering such CL light-emitting MgO crystal to the surface of the dielectric layer 12 by spraying, electrostatic coating, or the like. Note that the magnesium oxide layer 13 may be formed by forming a thin film magnesium oxide layer on the surface of the dielectric layer 12 by vapor deposition or sputtering, and attaching a CL light emitting MgO crystal thereon.

  On the back substrate 14 arranged in parallel with the front transparent substrate 10, each column electrode D is located at each row electrode pair (X, Y) at a position facing the transparent electrodes Xa and Ya in each row electrode pair (X, Y). Y) and extending in a direction perpendicular to Y). On the back substrate 14, a white column electrode protective layer 15 that covers the column electrode D is further formed. A partition wall 16 is formed on the column electrode protective layer 15. The partition wall 16 includes a horizontal wall 16A extending in the horizontal direction of the two-dimensional display screen at a position corresponding to the bus electrodes Xb and Yb of each row electrode pair (X, Y), and intermediate portions between the column electrodes D adjacent to each other. A ladder wall is formed by the vertical wall 16B extending in the vertical direction of the two-dimensional display screen at the position. Further, a ladder-shaped partition wall 16 as shown in FIG. 2 is formed for each display line of the PDP 50. A gap SL as shown in FIG. 2 exists between the partition walls 16 adjacent to each other. Further, the ladder-shaped partition walls 16 define discharge cells PC each including an independent discharge space S and transparent electrodes Xa and Ya. In the discharge space S, a discharge gas containing xenon gas is enclosed. A phosphor layer 17 is formed on the side surface of the horizontal wall 16A, the side surface of the vertical wall 16B, and the surface of the column electrode protection layer 15 in each discharge cell PC so as to cover all of these surfaces. The phosphor layer 17 is actually composed of three types: a phosphor that emits red light, a phosphor that emits green light, and a phosphor that emits blue light.

  The phosphor layer 17 contains, for example, MgO crystal (including CL light-emitting MgO crystal) as a secondary electron emission material in the form shown in FIG. At this time, the MgO crystal is exposed from the phosphor layer 17 so as to be in contact with the discharge gas at least on the surface of the phosphor layer 17, that is, on the surface in contact with the discharge space S.

  As shown in FIG. 3, the magnesium oxide layer 13 is closed between the discharge space S and the gap SL of each discharge cell PC by contacting the lateral wall 16A. Further, as shown in FIG. 4, since the vertical wall 16B is not in contact with the magnesium oxide layer 13, a gap r exists between them. That is, the discharge spaces S of the discharge cells PC adjacent to each other in the horizontal direction of the two-dimensional display screen communicate with each other through the gap r.

  As described above, in the PDP 50, both the magnesium oxide layer 13 and the phosphor layer 17 contain the CL light-emitting MgO crystal as described above. According to such a structure, the discharge probability in each of the discharge cells PC is dramatically improved. In particular, when a voltage is applied with the column electrode D as a cathode and the row electrode Y as a positive electrode, the column electrode D and the row electrode are applied. A discharge generated between Y (hereinafter referred to as column side cathode discharge) is likely to be generated.

First, the drive control unit 56 converts the input video signal into 8-bit pixel data that represents all the luminance levels in 256 gradations for each pixel, and performs error diffusion processing and dither processing on the pixel data. A multi-gradation process consisting of That is, first, in the error diffusion process, the upper 6 bits of the pixel data is set as display data, the remaining lower 2 bits are set as error data, and the error data in the pixel data corresponding to each peripheral pixel is weighted and added. By reflecting it in the display data, 6-bit error diffusion pixel data is obtained. According to such error diffusion processing, the luminance of the lower 2 bits in the original pixel is pseudo-expressed by the peripheral pixels, and therefore, the display data for 6 bits, which is less than 8 bits, and the pixel data for 8 bits. It is possible to express the same luminance gradation. Next, the drive control unit 56 performs dither processing on the 6-bit error diffusion processing pixel data obtained by the error diffusion processing. In the dither processing, a plurality of adjacent pixels are set as one pixel unit, and dither coefficients each having a different coefficient value are allocated and added to the error diffusion processing pixel data corresponding to each pixel in the one pixel unit. As a result, dither-added pixel data is obtained. According to the addition of the dither coefficients, when viewed in units of pixels as described above, it is possible to express the luminance corresponding to 8 bits even with only the upper 4 bits of the dither addition pixel data. Therefore, the drive control unit 56 converts the upper 4 bits of the dither added pixel data, as shown in FIG. 6, the overall brightness level to multi-gradation pixel data PD _S of four bits representing at 15 gradations . Then, the drive control unit 56 converts the 14-bit pixel drive data GD according to a data conversion table showing a multi-gradation pixel data PD _S in FIG. The drive control unit 56 associates the first to fourteenth bits in the pixel drive data GD with each of the subfields SF1 to SF14 (described later), and uses the bit digit corresponding to the subfield SF as the pixel drive data bit. One display line (m) is supplied to the address driver 55.

  Further, the drive control unit 56 supplies various control signals to drive the PDP 50 having the above structure to the panel driver including the X electrode driver 51, the Y electrode driver 53, and the address driver 55 according to the light emission drive sequence as shown in FIG. To do.

That is, the drive control unit 56 performs the first selective write address process W1 _W and the sustain process in the first subfield SF1 in one field or one frame display period (hereinafter referred to as a unit display period) as shown in FIG. Various control signals to be sequentially executed according to each I are supplied to the panel driver. In SF2 subsequent to such sub-field SF1, and supplies the various control signals for sequentially performing the driving in accordance with a second selective write addressing step W2 _W and sustain process I respectively to the panel driver. Further, in the subfield SF2 succeeding SF3, supplies various control signals for sequentially carrying out driving according to the third selective write address process W3 _W and sustain process I respectively to the panel driver. Then, in the SF4~SF14 each subfield SF3 and later, supplies various control signals for sequentially performing the drive in accordance with the selective erase address process W _D and sustain process I respectively to the panel driver. At this time, only in the last subfield SF14 in the unit display period, the drive control unit 56 supplies various control signals to be sequentially executed in accordance with the erase process E to the panel driver after the sustain process I is executed. To do. In the sustain process I of each of the subfields SF1 to SF14, as shown in FIG. 7, a sustain pulse application frequency ratio corresponding to the luminance weight of each SF is set.

  The panel driver, that is, the X electrode driver 51, the Y electrode driver 53, and the address driver 55, in the subfields SF1 to SF14, according to various control signals supplied from the drive control unit 56, are driven as shown in FIG. A pulse is applied to the column electrode D and the row electrodes X and Y of the PDP 50.

  In FIG. 8, only the operations in SF1 to SF4 and the last subfield SF14 in the subfields SF1 to SF14 shown in FIG. 7 are extracted and shown.

In the first selective write address process W1 _W of the subfield SF1, the address driver 55 sets the column electrodes D _{1 to} D _m to the ground potential (0 volts), and the X electrode driver 51 sets the row electrodes X ₁ to Set _Xn to ground potential (0 volts). Further, during this time, the Y electrode driver 53 applies a wall charge adjustment pulse CP having a negative peak potential with a gradual potential transition at the leading edge with time to the row electrodes Y _{1 to} Y _n . In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in each discharge cell PC, and a part of the wall charge formed therein is erased. Thus, the whole discharge cells PC are set to the state of the off mode, the amount of wall charges within the discharge cell PC, can correctly to rise to selective write address discharge in the first selective write address process W1 _W Adjusted to the amount. Absolute value V _CP of the negative peak potential in the wall charge adjusting pulse CP shown in FIG. 8 is an absolute value V _IP following the voltage of the positive polarity peak electric potential in the sustain pulse IP, which will be described later. After the application of the wall charge adjustment pulse CP, the Y electrode driver 53 applies the base pulse BP ⁻ having the negative polarity peak potential as shown in FIG. 8 to the row electrodes Y _{1 to} Y _n simultaneously. the successively selectively applying the write scan pulse SP _W in the row electrodes Y ₁ to Y _n, each having a peak potential. During this time, the X electrode driver 51 applies a base pulse BPa ⁻ having a negative peak potential to the row electrodes X _{1 to} X _n . Further, during this time, the address driver 55 first converts the pixel drive data bit corresponding to the subfield SF1 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, when a pixel driving data bit having a logic level 1 for setting the discharge cell PC in the lighting mode is supplied, the address driver 55 converts the pixel driving pulse into a pixel data pulse DP having a positive peak potential. On the other hand, a pixel drive data bit of logic level 0 that should cause the discharge cell PC to be set to the extinguishing mode is converted into a pixel data pulse DP of low voltage (0 volts). Then, the address driver 55, one display line such pixel data pulses DP (m in the number) per time, to the column electrodes D ₁ to D _m in synchronization with the application timing of each write scan pulse SP _W. Here, simultaneously with the write scan pulse SP _W, the selective write address discharge between the column electrode D and the row electrodes Y in the discharge cells PC in which the pixel data pulse DP of high voltage is applied to be set to the lighting mode Is born. Note that since no negative voltage (BPa ⁻ , BP ⁻ ) is applied to the row electrodes Y and X, no discharge occurs between the row electrodes Y and X. In response to the selective write address discharge, a positive wall charge is formed in the vicinity of the row electrode Y in the discharge cell PC, and a negative wall charge is formed in the vicinity of the column electrode D. The discharge cell PC is in the lighting mode. Is set to the state. On the other hand, simultaneously with the write scan pulse SP _W, is between the column electrode D and the row electrodes Y of the pixel data pulse DP of low voltage to be set to off-mode (0 volts) is applied the discharge cell PC described above Such selective write address discharge is not caused. Therefore, no wall charges are formed in the discharge cell PC, so that no discharge is generated between the row electrode Y and the column electrode D and between the row electrodes X and Y, that is, the extinction mode is set. Is done.

Next, in the sustain process I of the subfield SF1, the X electrode driver 51 and the address driver 55 respectively set the row electrodes X _{1 to} X _n and the column electrodes D _{1 to} D _m to the ground potential (0 volt) state. together, Y electrode driver 53 applies only to the row electrodes _Y 1 to Y _n, respectively once the sustain pulses IP _L having a positive peak potential. The positive peak potential of the sustain pulse IP _L is equal to or lower than the positive peak potential of the sustain pulse IP applied in the sustain process I of each SF after the subfield SF2, and preferably less than the peak potential. Depending on the application of the sustain pulses IP _L, together with the sustain discharge is generated between the row electrodes X and Y in the discharge cells PC set to the lighting mode, also between the column electrodes D and the row electrodes Y, Column side cathode discharge is caused by the action of the CL light-emitting MgO crystal contained in the magnesium oxide layer 13 and the phosphor layer 17 of the PDP 50. At this time, the light irradiated from the phosphor layer 17 in accordance with the sustain discharge for one time is irradiated to the outside through the front transparent substrate 10, so that one time corresponding to the luminance weight of the subfield SF1 is obtained. Display light is emitted. Then, after the end of the sustain discharge and the column side cathode discharge, the positive wall charge is near the row electrode X in the discharge cell PC, the negative wall charge is near the row electrode Y, and the positive polarity is near the column electrode D. Wall charges are formed respectively. That is, in the sustain process I of SF1, by assigning the number of sustain pulses applied once, that is, an odd number of times, the final sustain pulse in each sustain process I is applied to the row electrode Y side. Immediately after the end of the sustain step I, positive wall charges are formed in the vicinity of the row electrode X, and negative wall charges are formed in the vicinity of the row electrode Y. On the other hand, between the row electrodes X and Y in the discharge cells PC set to off-mode, between the column electrodes D and the row electrodes Y, the discharge be applied sustain pulses IP _L is made it is not caused. After the application of the sustain pulses IP _L, Y electrode driver 53, the wall charge adjusting pulse CP having a negative peak potential of the potential transition is gradual in the front edge over time to the row electrodes Y ₁ to Y _n Apply. Further, during this time, X-electrode driver 51 applies a base pulse BP ⁺ having a positive peak potential to the row electrodes _X 1 to X _n respectively. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in each discharge cell PC, and a part of the wall charge formed therein is erased. Thus, the whole discharge cells PC are set to the state of the off mode, the amount of wall charges within the discharge cell PC is correctly selective write address discharge in the second selective write addressing step W2 _W of the next SF2 Is adjusted to an amount that can cause

Next, in the second selective write addressing step W2 _W of the subfield SF2, Y electrode driver 53, the base pulse BP having a negative peak potential as shown in FIG. 8 ^- the row electrodes _Y 1 to Y _n at the same time applied and while, successively selectively applying the write scan pulse SP _W having a negative peak potential to the row electrodes Y ₁ to Y _n, respectively. During this time, X electrode driver 51 continues the row electrodes _X 1 to X _n respectively even in the base pulse BP ⁺ of the second selective write addressing step W2 _W applied to the row electrodes _X 1 to X _n in the sustain process I of SF1 Apply to. Incidentally, the base pulse BP ^- and the base pulse BP ⁺ is the potentials, so that the voltage between the row electrodes X and Y during the non-application period of the write scan pulse SP _W is lower than the discharge start voltage of the discharge cells PC Is set to an appropriate potential. Further, in the second selective write address process W2 _W, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF2 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, when a pixel driving data bit having a logic level 1 for setting the discharge cell PC in the lighting mode is supplied, the address driver 55 converts the pixel driving pulse into a pixel data pulse DP having a positive peak potential. On the other hand, a pixel drive data bit of logic level 0 that should cause the discharge cell PC to be set to the extinguishing mode is converted into a pixel data pulse DP of low voltage (0 volts). Then, the address driver 55, one display line such pixel data pulses DP (m in the number) per time, to the column electrodes D ₁ to D _m in synchronization with the application timing of each write scan pulse SP _W. At this time, simultaneously with the write scan pulse SP _W, is between the column electrode D and the row electrodes Y in the discharge cells PC in which the pixel data pulse DP of high voltage is applied to be set to the lighting mode selective write address discharge Is born. Further, immediately after the selective write address discharge, a weak discharge is also generated between the row electrodes X and Y in the discharge cell PC. That is, after the write scan pulse SP _W is applied, the row electrodes X and Y between the base pulse BP to ^- but and voltage corresponding to the base pulse BP ⁺ is applied, the voltage discharge of each discharge cell PC Since the voltage is set lower than the start voltage, discharge is not generated in the discharge cell PC only by applying such voltage. However, when the selective write address discharge is caused, is induced in the selective write address discharge, the base pulse BP ^- and the discharge between the row electrodes X and Y only voltage applied based on the base pulse BP ⁺ is occurring It is done. Such a discharge is not generated in the first selective write address process W1 _W in which the base pulse BP ⁺ is not applied to the row electrode X. By this discharge and the selective write address discharge, the discharge cell PC has a positive wall charge in the vicinity of the row electrode Y, a negative wall charge in the vicinity of the row electrode X, and a negative wall charge in the vicinity of the column electrode D. Are formed, that is, the lighting mode is set. On the other hand, simultaneously with the write scanning pulse SP _W, is between the column electrode D and row electrodes Y of the pixel data pulse DP of the low voltage to be set to off-mode (0 volts) is applied the discharge cell PC described above Such selective write address discharge does not occur, and therefore no discharge occurs between the row electrodes X and Y. Therefore, no wall charges are formed in the discharge cell PC, so that the extinguishing mode is set.

Next, in the sustain process I of sub-field SF2, X electrode driver 51 and address driver 55 sets respective row electrodes _X 1 to X _n and row electrodes _D 1 to D _m to a ground potential (0 volt) At the same time, the Y electrode driver 53 applies the sustain pulse IP having a positive peak potential to each of the row electrodes Y _{1 to} Y _n only once. As shown in FIG. 8, the positive polarity peak potential (V _IP ) of the sustain pulse IP is equal to or higher than the positive polarity peak potential of the sustain pulse IP _L applied in the sustain step I of the subfield SF1, preferably the peak potential. The potential is larger and is equal to or greater than the absolute value V _CP of the negative polarity peak potential of the wall charge adjustment pulse CP. In response to the application of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y in the discharge cell PC set in the lighting mode, and the PDP 50 is also generated between the column electrode D and the row electrode Y. Column side cathode discharge is caused by the action of the CL light emitting MgO crystal contained in the magnesium oxide layer 13 and the phosphor layer 17. At this time, the light irradiated from the phosphor layer 17 in accordance with the sustain discharge for one time as described above is irradiated to the outside through the front transparent substrate 10, thereby 1 corresponding to the luminance weight of the subfield SF2. The display light is emitted for the number of times. Then, after the end of the sustain discharge and the column side cathode discharge, the positive wall charge is near the row electrode X in the discharge cell PC, the negative wall charge is near the row electrode Y, and the positive polarity is near the column electrode D. Wall charges are formed respectively. That is, in the sustain process I of SF2, by assigning one, that is, an odd number of sustain pulses, the final sustain pulse in the sustain process I is applied to the row electrode Y side. Immediately after the end of the sustain step I, positive wall charges are formed in the vicinity of the row electrode X, and negative wall charges are formed in the vicinity of the row electrode Y. On the other hand, no discharge occurs between the row electrodes X and Y and between the column electrode D and the row electrode Y in the discharge cell PC set in the extinguishing mode even if the sustain pulse IP is applied. After the application of the sustain pulse IP, the Y electrode driver 53 applies a wall charge adjustment pulse CP having a negative peak potential with a gradual potential transition at the leading edge over time to the row electrodes Y _{1 to} Y _n . To do. Further, during this time, X-electrode driver 51 applies a base pulse BP ⁺ having a positive peak potential to the row electrodes _X 1 to X _n respectively. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in each discharge cell PC, and a part of the wall charge formed therein is erased. Thus, the whole discharge cells PC are set to the state of the off mode, the amount of wall charges within the discharge cell PC is correctly selective write address discharge in the third selective write address process W3 _W of the next SF3 Is adjusted to an amount that can cause

Next, in the third selective write address process W3 _W of the subfield SF3, Y electrode driver 53, the base pulse BP having a negative peak potential as shown in FIG. 8 ^- the row electrodes _Y 1 to Y _n at the same time applied and while, successively selectively applying the write scan pulse SP _W having a negative peak potential to the row electrodes Y ₁ to Y _n, respectively. During this time, X electrode driver 51 continues the row electrodes _X 1 to X _n respectively even in the base pulse BP ⁺ to the third selective write address process W3 _W applied to the row electrodes _X 1 to X _n in the sustain process I of SF2 Apply to. Incidentally, the base pulse BP ^- and the base pulse BP ⁺ is the potentials, so that the voltage between the row electrodes X and Y during the non-application period of the write scan pulse SP _W is lower than the discharge start voltage of the discharge cells PC Is set to an appropriate potential. Further, in the third selective write address process W3 _W, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF3 into the pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, when a pixel driving data bit having a logic level 1 for setting the discharge cell PC in the lighting mode is supplied, the address driver 55 converts the pixel driving pulse into a pixel data pulse DP having a positive peak potential. On the other hand, a pixel drive data bit of logic level 0 that should cause the discharge cell PC to be set to the extinguishing mode is converted into a pixel data pulse DP of low voltage (0 volts). Then, the address driver 55, one display line such pixel data pulses DP (m in the number) per time, to the column electrodes D ₁ to D _m in synchronization with the application timing of each write scan pulse SP _W. At this time, simultaneously with the write scan pulse SP _W, is between the column electrode D and the row electrodes Y in the discharge cells PC in which the pixel data pulse DP of high voltage is applied to be set to the lighting mode selective write address discharge Is born. Further, immediately after the selective write address discharge, a weak discharge is also generated between the row electrodes X and Y in the discharge cell PC. That is, after the write scan pulse SP _W is applied, the row electrodes X and Y between the base pulse BP to ^- but and voltage corresponding to the base pulse BP ⁺ is applied, the voltage discharge of each discharge cell PC Since the voltage is set lower than the start voltage, discharge is not generated in the discharge cell PC only by applying such voltage. However, when the selective write address discharge is caused, is induced in the selective write address discharge, the base pulse BP ^- and the discharge between the row electrodes X and Y only voltage applied based on the base pulse BP ⁺ is occurring It is done. Such a discharge is not generated in the first selective write address process W1 _W in which the base pulse BP ⁺ is not applied to the row electrode X. By this discharge and the selective write address discharge, the discharge cell PC has a positive wall charge in the vicinity of the row electrode Y, a negative wall charge in the vicinity of the row electrode X, and a negative wall charge in the vicinity of the column electrode D. Are formed, that is, the lighting mode is set. On the other hand, simultaneously with the write scan pulse SP _W, is between the column electrode D and the row electrodes Y of the pixel data pulse DP of low voltage to be set to off-mode (0 volts) is applied the discharge cell PC described above Such selective write address discharge does not occur, and therefore no discharge occurs between the row electrodes X and Y. Therefore, no wall charges are formed in the discharge cell PC, so that the extinguishing mode is set.

Next, in the sustain process I of sub-field SF3, X electrode driver 51 and address driver 55 sets respective row electrodes _X 1 to X _n and row electrodes _D 1 to D _m to a ground potential (0 volt) At the same time, the Y electrode driver 53 applies the sustain pulse IP having a positive peak potential to each of the row electrodes Y _{1 to} Y _n only once. As shown in FIG. 8, the positive polarity peak potential (V _IP ) of the sustain pulse IP is from the positive polarity peak potential of the sustain pulse IP _L applied in the sustain step I of the subfield SF1, preferably from the peak potential. It is a large potential and is equal to or greater than the absolute value V _CP of the negative polarity peak potential of the wall charge adjustment pulse CP. In response to the application of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y in the discharge cell PC set in the lighting mode, and the PDP 50 is also generated between the column electrode D and the row electrode Y. Column side cathode discharge is caused by the action of the CL light emitting MgO crystal contained in the magnesium oxide layer 13 and the phosphor layer 17. At this time, the light irradiated from the phosphor layer 17 in accordance with the sustain discharge for one time as described above is irradiated to the outside through the front transparent substrate 10, thereby 1 corresponding to the luminance weight of the subfield SF 3. The display light is emitted for the number of times. After the end of the sustain discharge and the column-side cathode discharge, the positive wall charge is in the vicinity of the row electrode X in the discharge cell PC, the negative wall charge is in the vicinity of the row electrode Y, and the positive electrode is in the vicinity of the column electrode D. Sex wall charges are formed respectively. On the other hand, no discharge occurs between the row electrodes X and Y and between the column electrode D and the row electrode Y in the discharge cell PC set in the extinguishing mode even if the sustain pulse IP is applied. After the application of the sustain pulse IP, the Y electrode driver 53 applies a wall charge adjustment pulse CP having a negative peak potential with a gradual potential transition at the leading edge over time to the row electrodes Y _{1 to} Y _n . To do. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in each discharge cell PC, and a part of the wall charge formed therein is erased. Thus, the amount of wall charges in all the discharge cells PC is adjusted to an amount capable of rise to selective erase address discharge correctly in the selective erase address process W _D of the next SF4. This erasing discharge is weaker than the erasing discharge generated in response to the wall charge adjustment pulse CP and the base pulse BP ⁺ in each of the subfields SF1 and SF2. Therefore, even after the erasing discharge, each discharge cell PC is in the state immediately before, that is, the discharge cell PC in the lighting mode is in the lighting mode, and the discharge cell PC in the lighting mode is in the extinguishing mode. To do.

Next, in subfields SF4~SF14 each selective erase address process W _O, Y electrode driver 53, while applying the base pulse BP ⁺ to the row electrodes _Y 1 to Y _n, each having a positive peak potential, FIG. an erase scan pulse SP _D with a negative peak potential of the as shown in 8 successively alternatively applied to the row electrodes Y ₁ to Y _n, respectively. The peak potential of the base pulse BP ⁺ is set to a potential that can prevent erroneous discharge between the row electrodes X and Y over the execution period of the selective erasure address process W _O. Further, the X electrode driver 51 sets each of the row electrodes X _{1 to} X _n to the ground potential (0 volt) during the execution period of the selective erase address process W _O. Further, in the selective erase address process W _D, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF to the pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, when a logic level 1 pixel drive data bit that should cause the discharge cell PC to transition from the lighting mode to the extinguishing mode is supplied, the address driver 55 converts this into a pixel data pulse DP having a positive peak potential. To do. On the other hand, when a pixel drive data bit having a logic level 0 for maintaining the current state of the discharge cell PC is supplied, it is converted into a pixel data pulse DP having a low voltage (0 volts). The address driver 55 applies the pixel data pulse DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each erasing scan pulse SP _D by one display line (m). At this time, simultaneously with the erase scanning pulse SP _D, selective erase address discharge between the column electrode D and the row electrodes Y in the discharge cells PC in which the pixel data pulse DP of high voltage is applied is caused. By this selective erasure address discharge, the discharge cell PC is in a state in which positive wall charges are formed in the vicinity of the row electrodes Y and X and negative wall charges are formed in the vicinity of the column electrodes D, that is, the extinction mode. Set to On the other hand, simultaneously with the erase scanning pulse SP _D, as mentioned above selective erase address discharge between the column electrode D and the row electrodes Y in the discharge cells PC in which the pixel data pulse DP is applied a low voltage (0 volts) occurs Not. Therefore, this discharge cell PC maintains the state (lighting mode, extinguishing mode) until just before that.

Next, in the sustain process I of each of the subfields SF4 to SF14, the number of times that the X electrode driver 51 and the Y electrode driver 53 correspond to the luminance weight of the subfield alternately with the row electrodes X and Y as shown in FIG. (even number) fraction by repeatedly applying a sustain pulse IP having a peak potential of positive polarity to the row electrodes _X 1 to X _n and _Y 1 to Y _n, respectively. The number of sustain pulses IP applied in the sustain process I of each of the subfields SF4 to SF14 is, for example, as shown in FIG.
SF4: 6
SF5: 8
SF6: 10
SF7: 12
SF8: 16
SF9: 22
SF10: 26
SF11: 30
SF12: 36
SF13: 40
SF14: 46
It is.

Further, the positive polarity peak potential (V _IP ) of the sustain pulse IP is equal to or higher than the positive polarity peak potential of the sustain pulse IP _L applied in the sustain process I of the subfield SF1, preferably higher than the peak potential. Further, the absolute value V _CP of the negative polarity peak potential of the wall charge adjusting pulse CP is not less than. Each time the sustain pulse IP is applied, a sustain discharge is generated between the row electrodes X and Y in the discharge cell PC set in the lighting mode. At this time, the light emitted from the phosphor layer 17 along with the sustain discharge repeatedly generated by the number of times corresponding to the luminance weight of the subfield SF is irradiated to the outside through the front transparent substrate 10. Display light emission indicating the luminance level corresponding to the luminance weight of each subfield is performed. In the vicinity of the row electrode Y in the discharge cell PC in which the sustain discharge is generated in response to the sustain pulse IP finally applied in the sustain step I of each of the subfields SF2 to SF14, negative wall charges, the row electrode X, and the column Positive wall charges are formed in the vicinity of each electrode D. After the application of the final sustain pulse IP, the Y electrode driver 53 applies a wall charge adjustment pulse CP having a negative peak potential with a gradual potential transition at the leading edge over time as shown in FIG. _{1 to} Y _n are applied. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in the discharge cell PC in which the sustain discharge is generated as described above, and a part of the wall charge formed in the discharge cell PC is erased. . Thus, the amount of wall charges within the discharge cell PC is adjusted to an amount capable of rise to selective erase address discharge correctly in the next selective erase address process W _D.
This erasing discharge is weaker than the erasing discharge generated in response to the wall charge adjustment pulse CP and the base pulse BP ⁺ in each of the subfields SF1 and SF2. Therefore, even after the erasing discharge, each discharge cell PC is in the state immediately before, that is, the discharge cell PC in the lighting mode is in the lighting mode, and the discharge cell PC in the extinguishing mode is in the extinguishing mode. To do.

After the sustain process I of the last sub-field SF14 finished, Y electrode driver 53 applies an erase pulse EP having a negative peak potential to all the row electrodes Y ₁ to Y _n. In response to the application of the erase pulse EP, an erase discharge is generated only in the discharge cells PC in the lighting mode state. The discharge cells PC that are in the lighting mode state by the erasing discharge are changed to the extinguishing mode state.

  By executing the driving as described above according to the pixel driving data GD as shown in FIG. 6, one of the 15 light emission driving patterns as shown in FIG. 6 is performed for each discharge cell PC. As a result, the luminance level for each discharge cell PC represented by the input video signal is expressed by 15 gradations (first to 15th gradations).

  That is, in FIG. 6, first, no discharge is generated within the unit display period of one field or one frame at the first gradation representing the lowest luminance. Thereby, in the first gradation, a so-called black display corresponding to the luminance level 0 is expressed.

  Next, in the second gradation representing the brightness higher by one level than the first gradation, as shown in FIG. 6, the discharge cell PC is set to the lighting mode only by SF1 among the subfields SF1 to SF14. This selective write address discharge is caused to occur, and the discharge cell PC set in this lighting mode is subjected to sustain discharge only once in the sustain process I of SF1 (indicated by a double circle). Thereby, in the second gradation, a luminance level “1” corresponding to one sustain discharge generated only in SF1 among SF1 to SF14 is expressed.

  Next, in the third gradation representing the brightness higher by one level than the second gradation, selective writing for setting the discharge cell PC to the lighting mode only by SF1 and SF2 in the subfields SF1 to SF14. An address discharge is generated, and the discharge cell PC set in this lighting mode is subjected to a sustain discharge only once in the sustain process I of each of SF1 and SF2 (indicated by a double circle). Thereby, in the third gradation, the luminance level “2” corresponding to the total number “2” of one sustain discharge generated in SF1 and SF2 of SF1 to SF14 is expressed.

  Next, in the fourth gradation that represents one level higher than the third gradation, selective writing for setting the discharge cells PC to the lighting mode in each of SF1 to SF3 of the subfields SF1 to SF14. An address discharge is generated, and the discharge cell PC set in the lighting mode is subjected to a sustain discharge only once in the sustain process I of each of SF1 to SF3 (indicated by a double circle). Further, in the fourth gradation, a selective erase address discharge for causing the discharge cell PC to transition from the lighting mode to the extinguishing mode is caused in the subfield SF4 (indicated by a black circle). Thereby, in the fourth gradation, the luminance level “3” corresponding to the total number “3” of one sustain discharge generated in SF1 to SF3 of SF1 to SF14 is expressed.

  Next, in the fifth gradation that represents one level higher than the fourth gradation, selective writing for setting the discharge cells PC in the lighting mode in each of SF1 to SF3 of the subfields SF1 to SF14. An address discharge is generated, and the discharge cell PC set in the lighting mode is subjected to a sustain discharge only once in the sustain process I of each of SF1 to SF3 (indicated by a double circle). Further, at the fifth gradation, a selective erasure address discharge for causing the discharge cell PC to transition from the lighting mode to the extinguishing mode is caused in the subfield SF5 (indicated by a black circle). As a result, in the fourth gradation, the sustain discharge for six times generated in the sustain process I of SF4 is added to the total number “3” of the sustain discharge for one time generated in SF1 to SF3 of SF1 to SF14. A luminance level “9” corresponding to the total number “9” (indicated by white circles) is expressed.

  Similarly, in each of the sixth to fourteenth gradations expressing higher luminance than the fifth gradation, selection for setting the discharge cell PC in the lighting mode in each of the subfields SF1 to SF14 SF1 to SF3. The write address discharge is generated, and the discharge cells PC set in the lighting mode are subjected to sustain discharge only once in the sustain process I of each of SF1 to SF3 (indicated by double circles). Further, in each of the sixth to fourteenth gradations, a selective erase address for transitioning the discharge cell PC from the lighting mode to the extinguishing mode in one SF corresponding to each gradation in each of the subfields SF6 to SF14. Discharge occurs (indicated by black circles). As a result, in each of the sixth to fourteenth gradations, the total number of sustain discharges for one time generated in SF1 to SF3 among SF1 to SF14 is “3”, and SFs indicated by white circles in FIG. The luminance level corresponding to the total number of sustain discharges generated in the sustain process I is expressed.

  In the 15th gradation corresponding to the highest luminance, a selective write address discharge for setting the discharge cells PC in the lighting mode is caused in each of the subfields SF1 to SF14 in the subfields SF1 to SF14. The set discharge cells PC are subjected to sustain discharge only once in the sustain process I of SF1 to SF3 (indicated by double circles). At this time, at the 15th gradation, no selective erasure address discharge is caused in the SFs after the subfield SF4. Therefore, in the fifteenth gradation, the total number of sustain discharges for one time generated in SF1 to SF3 among SF1 to SF14 is “3”, and the sustain discharges generated in the sustain process I of each of SF4 to SF14 are included. A luminance level “255” corresponding to the total number “255” including the number of times is expressed.

  In other words, the luminance range of “0” to “255” indicated by the input video signal can be expressed by the 15th to 15th gradations by using the 15 light emission drive patterns as shown in FIG. It becomes.

  Here, in the driving shown in FIGS. 6 to 8, a relatively strong discharge for forming a large amount of charged particles in all the discharge cells PC, that is, a reset discharge (or priming discharge) is generated at all. Absent. This is possible because each of the magnesium oxide layer 13 and the phosphor layer 17 in each discharge cell PC employs a structure including the CL light-emitting MgO crystal as described above. That is, by using the emission action of the initial electrons and secondary electrons by the CL light-emitting MgO crystal, various discharges can be performed without causing a discharge delay without generating a large amount of charged particles by reset discharge (or priming discharge). It has become possible to make sure that

  Therefore, in the first gradation representing the lowest luminance level, no discharge accompanied by various types of visible light emission including reset discharge (or priming discharge) occurs, so that a jet black display is expressed. Therefore, it is possible to perform display with further enhanced dark contrast of the image as compared with the conventional plasma display device.

  Since the amount of charged particles is reduced by omitting the reset discharge, the selective write address discharge in the subfields SF2 and SF3 may not be stably generated. Therefore, as shown in FIG. 6, when the selective write address discharge is caused in the subfield SF2 (indicated by a double circle), the selective write address discharge is always caused in the SF1 (indicated by a double circle). ) Then, charged particles are generated in the discharge cell PC along with the selective write address discharge and the sustain discharge in SF1, and the selective write address discharge in SF2 is stably and reliably generated by the action of the charged particles. It comes to be.

  In short, when the PDP 50 adopting the structure in which each of the magnesium oxide layer 13 and the phosphor layer 17 includes a CL light-emitting MgO crystal is driven without reset discharge, the selective write address discharge is caused in SF2. The selective write address discharge is always caused even in SF1.

In the drive shown in FIG. 8, the positive polarity peak potential of the sustain pulse IP _L applied in the sustain stroke I of the subfield SF1 is preferably equal to or lower than the positive polarity peak potential of the sustain pulse IP applied in the sustain stroke I after SF2. Is less than the peak potential. That is, in the sustain process I of SF1, by lowering the peak potential of the sustain pulse, the discharge cell PC in which the selective write address discharge is not generated in the first selective write address process W1 _W process, that is, the extinguishing mode is set. This prevents the sustain discharge that is erroneously generated in the set discharge cell PC. Thus, when the drive for expressing the first gray scale shown in FIG. 6, that is, the drive for expressing the black display, is performed, the black luminance level 0 excluding the discharge accompanied by the visible light emission can be expressed. Is possible.

Further, in the drive shown in FIG. 8, the absolute value V _CP of the negative polarity peak potential of the wall charge adjustment pulse CP applied in each of the subfields SF1 to SF14 is set to the sustain pulse IP applied in the sustain process I after SF2. It is the absolute value V _IP following the potential of the positive polarity peak electric potential. That is, by setting the absolute value V _CP of the negative polarity peak potential of the wall charge adjustment pulse CP to be low, the luminance level at the time of light emission associated with the discharge caused by the wall charge adjustment pulse CP is not visible. It is reduced to the brightness level. This makes it possible to express the black luminance level 0 excluding the discharge accompanied by visible light emission, particularly when the driving for expressing the first gradation shown in FIG. 6 is performed.

Incidentally, in the driving shown in FIG. 8, in the first selective writing addressing process W1 _W stroke subfield SF1, selected document that is caused between the column electrode D and the row electrode Y in response to the application of the write scan pulse SP _W There is a possibility that an erroneous discharge is caused between the row electrodes X and Y by being induced by the embedded address discharge. Then, the amount of negative wall charges formed in the vicinity of the row electrode X and the amount of positive wall charges formed in the vicinity of the row electrode Y become excessive, and the second selective write address process W2 _W process of SF2 thereafter. This increases the possibility that correct selective write address discharge will not occur.

Therefore, in the driving shown in FIG. 8, in the first selective write address process W1 _W stroke of SF1, base pulse BP having a negative polarity to the row electrodes Y ₁ to Y _n ^- is over during being applied, X electrodes driver 51, the base pulse BP ^- and so as to apply to the whole row electrodes _X 1 to X _n ^- base pulse BPa of the same polarity (negative polarity). Thus, since the erroneous discharge is suppressed to be occur induced in the selective write address discharge between the row electrodes X and Y, a selective write address discharge in the second selective write addressing step W2 _W stroke SF2 It is possible to cause it to occur stably.

At this time, a negative base pulse (BP ⁻ ) is applied to the row electrode Y in the selective write address process (W 1 _W ), and a base pulse (BPa ⁻ ) having the same polarity as this base pulse is applied to the row electrode X. Thus, the technique for preventing erroneous discharge between the row electrodes X and Y can be similarly applied not only to the driving shown in FIGS. 6 to 8 but also to the driving shown in FIGS. 9 to 11. .

That is, when performing such driving, the drive control unit 56 first converts the input video signal into 8-bit pixel data representing all luminance levels in 256 gradations for each pixel, and this pixel data. Is subjected to multi-gradation processing consisting of error diffusion processing and dither processing as described above. As a result, the drive control unit 56 represents the luminance level for each pixel represented by the input video signal, and represents the entire luminance range in 16 levels (first to 16th gradations) as shown in FIG. converting the multi-gradation pixel data PD _S of bits. Then, the drive control unit 56 converts the multi-grayscale pixel data PD _S such in accordance with the data conversion table 14-bit pixel drive data GD shown in FIG. The drive control unit 56 associates the first to fourteenth bits in the pixel drive data GD with each of the subfields SF1 to SF14, and uses the bit digit corresponding to the subfield SF as one pixel drive data bit for one display line. (M) are supplied to the address driver 55 one by one.

Further, the drive control unit 56 supplies various control signals for driving the PDP 50 according to the light emission drive sequence as shown in FIG. 10 to the panel driver including the X electrode driver 51, the Y electrode driver 53, and the address driver 55. That is, the drive control unit 56 performs the first reset process R1, the first selective write address process W1 _W, and the minute light emission process LL in the first subfield SF1 within the display period of one field (one frame) as shown in FIG. Various control signals to be sequentially driven according to each are supplied to the panel driver. In SF2 subsequent to such sub-field SF1, and supplies the second reset step R2, a second selective write addressing step W2 _W and various control signals for sequentially performing the drive in accordance with the sustain stage I each panel driver. Also, In the subfield SF3~SF14 each supplies various control signals for sequentially performing the drive in accordance with the selective erase address process W _D and sustain process I respectively to the panel driver. Only in the last subfield SF14 within one field display period, after the sustain process I is executed, the drive control unit 56 supplies various control signals to be sequentially executed in accordance with the erase process E to the panel driver. To do.

  The panel drivers, that is, the X electrode driver 51, the Y electrode driver 53, and the address driver 55 generate various drive pulses as shown in FIG. 11 in accordance with the various control signals supplied from the drive control unit 56 to generate a column of the PDP 50. Supply to electrode D and row electrodes X and Y.

In FIG. 11, only the operations in SF1 to SF3 and the last subfield SF14 in the subfields SF1 to SF14 shown in FIG. 10 are extracted and shown. First, in the first half of the first reset step R1 of the subfield SF1, the Y electrode driver 53 has a waveform having a gentle potential transition at the leading edge over time as compared to a sustain pulse IP described later. Reset pulse RP1 _Y1 is applied to all the row electrodes Y _{1 to} Y _n . The peak potential of the reset pulse RP1 _Y1 is higher than the peak potential of the sustain pulse and lower than the peak potential of a reset pulse RP2 _Y1 described later. During this time, the address driver 55 sets the column electrodes D _{1 to} D _m to the ground potential (0 volt) state, and the X electrode driver 51 has the same polarity as the reset pulse RP _{1 Y 1} , and A reset pulse RP1 _X having a peak potential capable of preventing surface discharge between the row electrodes X and Y accompanying the application of the reset pulse RP1 _Y1 is applied to all the row electrodes X _{1 to} X _n . If no surface discharge occurs between the row electrodes X and Y, the X electrode driver 51 applies all the row electrodes X _{1 to} X _n to the ground potential (0 volt) instead of applying the reset pulse RP1 _X. You may make it set to. Here, in the first half of the first reset step R1, a weak first reset discharge occurs between the row electrode Y and the column electrode D in each of all the pixel cells PC in response to the application of the reset pulse RP1 _Y1 as described above. Is born. That is, in the first half of the first reset process R1, by applying a voltage between both electrodes so that the row electrode Y is on the anode side and the column electrode D is on the cathode side, the row electrode Y is directed toward the column electrode D. The column-side cathode discharge through which current flows is generated as the first reset discharge. In response to the first reset discharge, negative wall charges are formed in the vicinity of the row electrodes Y in all the pixel cells PC, and positive wall charges are formed in the vicinity of the column electrodes D.

Next, in the second half of the first reset step R1 of the subfield SF1, the Y electrode driver 53 generates a negative reset pulse RP1 _Y2 whose potential transition at the leading edge with time elapses. applied to all the row electrodes _Y 1 to Y _n. The negative peak potential in the reset pulse RP1 _Y2 is set to a higher potential, that is close to 0 volt potential than the peak potential of the negative polarity writing scan pulse SP _W, which will be described later. That is, when the peak potential of the reset pulse RP _Y2 thus lower than the peak potential of the write scan pulse SP _W, the occurrence strong discharge between the row electrodes Y and column electrodes D, are formed near the column electrode D This is because the wall charges are largely erased, and the address discharge in the first selective write address process W1 _W becomes unstable. During this time, X electrode driver 51, all of the row electrodes _X 1 to X _n is set to the ground potential (0 volt). Note that the peak potential of the reset pulse RP1 _Y2 is reliably determined between the row electrodes X and Y in consideration of wall charges formed in the vicinity of the row electrodes X and Y according to the first reset discharge. 2 The lowest potential that can cause a reset discharge. Here, in the second half of the first reset step R1, a second reset discharge is generated between the row electrodes X and Y in all the pixel cells PC in response to the application of the reset pulse RP1 _Y2 as described above. Due to the second reset discharge, the wall charges formed in the vicinity of the row electrodes X and Y in each pixel cell PC are erased, and all the pixel cells PC are initialized to the extinguishing mode. Further, in response to the application of the reset pulse RP1 _Y2, a weak discharge is generated between the row electrodes Y and the column electrodes D in all the pixel cells PC. By this weak discharge, a part of the positive wall charges formed in the vicinity of the column electrode D is erased, and an amount capable of causing the selective write address discharge correctly in the first selective write address process W1 _W described later. Adjusted to

Next, in the first selective write address process W1 _W of the subfield SF1, the Y electrode driver 53 simultaneously applies a base pulse BP ⁻ having a negative peak potential as shown in FIG. 11 to the row electrodes Y _{1 to} Y _n . while applying, successively selectively applying the write scan pulse SP _W having a negative peak potential to the row electrodes Y ₁ to Y _n, respectively. During this time, the X electrode driver 51 applies a base pulse BPa ⁻ having a negative peak potential to the row electrodes X _{1 to} X _n . Further, during this time, the address driver 55 first converts the pixel drive data bit corresponding to the subfield SF1 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, when a pixel driving data bit having a logic level 1 for setting the discharge cell PC in the lighting mode is supplied, the address driver 55 converts the pixel driving pulse into a pixel data pulse DP having a positive peak potential. On the other hand, a pixel drive data bit of logic level 0 that should cause the discharge cell PC to be set to the extinguishing mode is converted into a pixel data pulse DP of low voltage (0 volts). Then, the address driver 55, one display line such pixel data pulses DP (m in the number) per time, to the column electrodes D ₁ to D _m in synchronization with the application timing of each write scan pulse SP _W. Here, simultaneously with the write scan pulse SP _W, the selective write address discharge between the column electrode D and the row electrodes Y in the discharge cells PC in which the pixel data pulse DP of high voltage is applied to be set to the lighting mode Is born. Note that since no negative voltage (BPa ⁻ , BP ⁻ ) is applied to the row electrodes Y and X, no discharge occurs between the row electrodes Y and X. In response to the selective write address discharge, a positive wall charge is formed in the vicinity of the row electrode Y in the discharge cell PC, and a negative wall charge is formed in the vicinity of the column electrode D. The discharge cell PC is in the lighting mode. Is set to the state. On the other hand, simultaneously with the write scan pulse SP _W, is between the column electrode D and the row electrodes Y of the pixel data pulse DP of low voltage to be set to off-mode (0 volts) is applied the discharge cell PC described above Such selective write address discharge is not caused. Therefore, no wall charges are formed in the discharge cell PC, so that no discharge is generated between the row electrode Y and the column electrode D and between the row electrodes X and Y, that is, the extinction mode is set. Is done.

Next, in the minute light emission process LL of the subfield SF1, the Y electrode driver 53 simultaneously applies minute light emission pulses LP having a predetermined positive peak potential as shown in FIG. 11 to the row electrodes Y _{1 to} Y _n . In response to the application of the minute light emission pulse LP, a discharge (hereinafter referred to as a minute light emission discharge) is generated between the column electrode D and the row electrode Y in the discharge cell PC set in the lighting mode. That is, in the minute light emission process LL, although a discharge is generated between the row electrode Y and the column electrode D in the discharge cell PC, a potential that does not cause a discharge between the row electrodes X and Y is applied to the row electrode Y. By applying this, a minute light emission discharge is caused only between the column electrode D and the row electrode Y in the discharge cell PC set in the lighting mode. At this time, the peak potential of the minute light emission pulse LP is lower than the peak potential of the sustain pulse IP applied in the sustain process I after the subfield SF2 described later. Further, as shown in FIG. 11, the rate of change with time in the rising edge of the potential of the minute light emission pulse LP is higher than the rate of change in the rising edge of the reset pulse (RP1 _Y1 , RP2 _Y1 ). That is, the first reset discharge generated in the first reset process R1 and the second reset process R2 by making the potential transition at the leading edge of the minute emission pulse LP steeper than the potential transition at the leading edge of the reset pulse. It causes a stronger discharge. Here, the discharge is a column-side cathode discharge as described above, and is a discharge generated by a minute light emission pulse LP whose pulse voltage is lower than that of the sustain pulse IP. Therefore, the discharge is generated between the row electrodes X and Y. The emission luminance associated with the discharge is lower than the sustain discharge (described later). That is, in the minute light emission process LL, although the discharge is accompanied by light emission having a higher luminance level than the first reset discharge, the discharge has a lower luminance level associated with the discharge than the sustain discharge, that is, a minute amount that can be used for display. A discharge accompanied by light emission is generated as a minute light emission discharge. At this time, in the first selective write address process W1 _W, selective write address discharge between the column electrode D and the row electrodes Y in the discharge cell PC is caused to be performed immediately before the minute light emission process LL. Therefore, in the subfield SF1, the luminance corresponding to the gradation that is one level higher than the luminance level 0 is expressed by the light emission accompanying the selective write address discharge and the light emission accompanying the minute light emission discharge. . After the minute light emission discharge, a negative wall charge is formed in the vicinity of the row electrode Y, and a positive wall charge is formed in the vicinity of the column electrode D.

Next, in the first half of the second reset process R2 of the subfield SF2, the Y electrode driver 53 has a positive polarity having a waveform in which the potential transition at the leading edge with the passage of time is gentler than a sustain pulse described later. applying a reset pulse _{RP2 Y1} to all the row electrodes _Y 1 to Y _n. Note that the peak potential of the reset pulse RP2 _Y1 is higher than the peak potential of the reset pulse RP1 _Y1 . During this time, the address driver 55 sets the column electrodes D _{1 to} D _m to the ground potential (0 volt) state, and the X electrode driver 51 sets the distance between the row electrodes X and Y accompanying the application of the reset pulse RP2 _Y1. A positive reset pulse RP2 _X having a peak potential capable of preventing surface discharge at ₁ is applied to each of all the row electrodes X _{1 to} X _n . If no surface discharge occurs between the row electrodes X and Y, the X electrode driver 51 supplies all the row electrodes X _{1 to} X _n to the ground potential (0 volts) instead of applying the reset pulse RP2 _X. ) May be set. In response to the application of the reset pulse RP2 _Y1 , between the row electrode Y and the column electrode D in the discharge cell PC in which the column side cathode discharge has not occurred in the minute light emission process LL in each of the discharge cells PC. A first reset discharge that is weaker than the column-side cathode discharge in the minute light emission process LL is generated. That is, in the first half of the second reset process R2, by applying a voltage between both electrodes so that the row electrode Y is on the anode side and the column electrode D is on the cathode side, the row electrode Y is directed toward the column electrode D. The column-side cathode discharge through which current flows is generated as the first reset discharge. On the other hand, in the discharge cell PC in which a minute light emission discharge has already occurred in the minute light emission process LL, no discharge is generated even if the reset pulse RP2 _Y1 is applied. Therefore, immediately after the end of the first half of the second reset step R2, negative wall charges are formed in the vicinity of the row electrodes Y in all the discharge cells PC, and positive wall charges are formed in the vicinity of the column electrodes D. Become.

Next, in the second half of the second reset step R2 of the subfield SF2, the Y electrode driver 53 applies a negative polarity reset pulse RP2 _Y2 having a gentle potential transition at the leading edge with the passage of time to the row electrodes Y ₁ to Y ₂ . It is applied to the Y _n. Furthermore, in the second half of the second resetting step R2, X electrode driver 51 applies a base pulse BP ⁺ having a positive polarity peak potential to the row electrodes _X 1 to X _n respectively. At this time, in response to the application of the negative polarity reset pulse RP2 _Y2 and the positive polarity base pulse BP ^+, a second reset discharge is generated between the row electrodes X and Y in all the discharge cells PC. The peak potentials of the reset pulse RP2 _Y2 and the base pulse BP ⁺ are determined between the row electrodes X and Y in consideration of wall charges formed in the vicinity of the row electrodes X and Y by the first reset discharge. This is the lowest potential that can surely cause the second reset discharge. Also, the negative peak potential in the reset pulse RP2 _Y2 is set higher potential, the potential close to that is 0 volts than the peak potential of negative polarity write scan pulse SP _W. That is, when the peak potential of the reset pulse RP2 _Y2 would be lower than the peak potential of the write scan pulse SP _W, the occurrence strong discharge between the row electrodes Y and column electrodes D, are formed near the column electrode D wall charges erases greatly, because the address discharge in the second selective write addressing step W2 _W becomes unstable. Here, the wall charges formed in the vicinity of the row electrodes X and Y in each discharge cell PC are erased by the second reset discharge generated in the second half of the second reset process R2, and all the discharge cells are erased. The PC is initialized to the off mode. Further, in response to the application of the reset pulse RP2 _Y2, a weak discharge is generated between the row electrode Y and the column electrode D in all the discharge cells PC, and the discharge is formed in the vicinity of the column electrode D. some of the positive wall charges are erased, is adjusted to an amount that can correctly to rise to selective write address discharge in the second selective write addressing step W2 _W.

Next, in the second selective write addressing step W2 _W of the subfield SF2, Y electrode driver 53, the base pulse BP having a negative peak potential as shown in FIG. 11 ^- the row electrodes _Y 1 to Y _n at the same time applied and while, successively selectively applying the write scan pulse SP _W having a negative peak potential to the row electrodes Y ₁ to Y _n, respectively. X electrode driver 51 continues the row electrodes _X 1 to X _n be the base pulse BP ⁺ applied to the row electrodes _X 1 to X _n in the second half portion in the second selective write addressing step W2 _W of the second reset step R2 Apply to each. Incidentally, the base pulse BP ^- and the base pulse BP ⁺ is the potentials, so that the voltage between the row electrodes X and Y during the non-application period of the write scan pulse SP _W is lower than the discharge start voltage of the discharge cells PC Is set to an appropriate potential. Further, in the second selective write address process W2 _W, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF2 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, when a pixel driving data bit having a logic level 1 for setting the discharge cell PC in the lighting mode is supplied, the address driver 55 converts the pixel driving pulse into a pixel data pulse DP having a positive peak potential. On the other hand, a pixel drive data bit of logic level 0 that should cause the discharge cell PC to be set to the extinguishing mode is converted into a pixel data pulse DP of low voltage (0 volts). Then, the address driver 55, one display line such pixel data pulses DP (m in the number) per time, to the column electrodes D ₁ to D _m in synchronization with the application timing of each write scan pulse SP _W. At this time, simultaneously with the write scan pulse SP _W, is between the column electrode D and the row electrodes Y in the discharge cells PC in which the pixel data pulse DP of high voltage is applied to be set to the lighting mode selective write address discharge Is born. Further, immediately after the selective write address discharge, a weak discharge is also generated between the row electrodes X and Y in the discharge cell PC. That is, after the write scan pulse SP _W is applied, the row electrodes X and Y between the base pulse BP to ^- but and voltage corresponding to the base pulse BP ⁺ is applied, the voltage discharge of each discharge cell PC Since the voltage is set lower than the start voltage, discharge is not generated in the discharge cell PC only by applying such voltage. However, when the selective write address discharge is caused, is induced to the selective write address discharge, the base pulse BP ^- and the discharge between the row electrodes X and Y only voltage applied based on the base pulse BP ⁺ is occurring It is done. Such a discharge is not generated in the first selective write address process W1 _W in which the base pulse BP ⁺ is not applied to the row electrode X. By this discharge and the selective write address discharge, the discharge cell PC has a positive wall charge in the vicinity of the row electrode Y, a negative wall charge in the vicinity of the row electrode X, and a negative wall charge in the vicinity of the column electrode D. Are formed, that is, the lighting mode is set. On the other hand, simultaneously with the write scan pulse SP _W, is between the column electrode D and the row electrodes Y of the pixel data pulse DP of low voltage to be set to off-mode (0 volts) is applied the discharge cell PC described above Such selective write address discharge does not occur, and therefore no discharge occurs between the row electrodes X and Y. Therefore, this discharge cell PC maintains the state immediately before that, that is, the extinguished mode state initialized in the second reset step R2.

Next, in the sustain process I of the subfield SF2, the Y electrode driver 53 generates a sustain pulse IP having a positive peak potential for one pulse and applies it to each of the row electrodes Y _{1 to} Y _n simultaneously. During this time, the X electrode driver 51 sets the row electrodes X _{1 to} X _n to the ground potential (0 volt) state, and the address driver 55 sets the column electrodes D _{1 to} D _m to the ground potential (0 volt) state. Set. In response to the application of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y in the discharge cell PC set in the lighting mode as described above. The light emitted from the phosphor layer 17 in accordance with the sustain discharge is emitted to the outside through the front transparent substrate 10, whereby one display light emission corresponding to the luminance weight of the subfield SF2 is performed. . Further, in response to the application of the sustain pulse IP, a discharge is also generated between the row electrode Y and the column electrode D in the discharge cell PC set in the lighting mode. By this discharge and the sustain discharge, negative wall charges are formed in the vicinity of the row electrode Y in the discharge cell PC, and positive wall charges are formed in the vicinity of the row electrode X and the column electrode D, respectively. After the application of the sustain pulse IP, the Y electrode driver 53 applies a wall charge adjustment pulse CP having a negative peak potential with a gradual potential transition at the leading edge as time elapses as shown in FIG. It applied to the Y ₁ to Y _n. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in the discharge cell PC in which the sustain discharge is generated as described above, and a part of the wall charge formed in the discharge cell PC is erased. . Thus, the amount of wall charges in the discharge cell PC is adjusted to an amount capable of rise to selective erase address discharge correctly in the next selective erase address process W _D.

Next, in subfields SF3~SF14 each selective erase address process W _O, Y electrode driver 53, while applying the base pulse BP ⁺ having a positive polarity peak potential to the row electrodes _Y 1 to Y _n, respectively, FIG. 11 successively alternatively applying the erase scan pulse SP _D with a negative peak potential of the as shown in the row electrodes Y ₁ to Y _n, respectively. The peak potential of the base pulse BP ⁺ is set to a potential that can prevent erroneous discharge between the row electrodes X and Y over the execution period of the selective erasure address process W _O. Further, the X electrode driver 51 sets each of the row electrodes X _{1 to} X _n to the ground potential (0 volt) during the execution period of the selective erase address process W _O. Further, in the selective erase address process W _D, the address driver 55 first converts a pixel drive data bit corresponding to the subfield SF to the pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, when a logic level 1 pixel drive data bit that should cause the discharge cell PC to transition from the lighting mode to the extinguishing mode is supplied, the address driver 55 converts this into a pixel data pulse DP having a positive peak potential. To do. On the other hand, when a pixel drive data bit having a logic level 0 for maintaining the current state of the discharge cell PC is supplied, it is converted into a pixel data pulse DP having a low voltage (0 volts). The address driver 55 applies the pixel data pulse DP to the column electrodes D _{1 to} D _m in synchronization with the application timing of each erasing scan pulse SP _D by one display line (m). At this time, simultaneously with the erase scanning pulse SP _D, selective erase address discharge between the column electrode D and the row electrodes Y in the discharge cells PC in which the pixel data pulse DP of high voltage is applied is caused. By this selective erasure address discharge, the discharge cell PC is in a state in which positive wall charges are formed in the vicinity of the row electrodes Y and X and negative wall charges are formed in the vicinity of the column electrodes D, that is, the extinction mode. Set to On the other hand, simultaneously with the erase scanning pulse SP _D, as mentioned above selective erase address discharge between the column electrode D and the row electrodes Y in the discharge cells PC in which the pixel data pulse DP is applied a low voltage (0 volts) occurs Not. Therefore, this discharge cell PC maintains the state (lighting mode, extinguishing mode) until just before that.

Next, in the sustain process I of each of the subfields SF3 to SF14, the X electrode driver 51 and the Y electrode driver 53 alternately correspond to the luminance weights of the subfields as shown in FIG. repeated even number times) min, applies a sustain pulse IP having a peak potential of positive polarity to the row electrodes _X 1 to X _n and _Y 1 to Y _n, respectively. Each time the sustain pulse IP is applied, a sustain discharge is generated between the row electrodes X and Y in the discharge cell PC set in the lighting mode. The light emitted from the phosphor layer 17 in accordance with the sustain discharge is emitted to the outside through the front transparent substrate 10, so that display light emission is performed for the number of times corresponding to the luminance weight of the subfield SF. . At this time, in the vicinity of the row electrode Y in the discharge cell PC in which the sustain discharge is generated in response to the sustain pulse IP finally applied in the sustain step I of each of the subfields SF2 to SF14, Positive wall charges are formed in the vicinity of X and the column electrode D. After the final sustain pulse IP is applied, the Y electrode driver 53 performs a wall charge adjustment pulse CP having a negative peak potential with a gentle potential transition at the leading edge with time as shown in FIG. applied to the electrodes _Y 1 to Y _n. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in the discharge cell PC in which the sustain discharge is generated as described above, and a part of the wall charge formed in the discharge cell PC is erased. . Thus, the amount of wall charges in the discharge cell PC is adjusted to an amount capable of rise to selective erase address discharge correctly in the next selective erase address process W _D.

After the sustain process I of the last sub-field SF14 finished, Y electrode driver 53 applies an erase pulse EP having a negative peak potential to all the row electrodes Y ₁ to Y _n. In response to the application of the erase pulse EP, an erase discharge is generated only in the discharge cells PC in the lighting mode state. The discharge cells PC that are in the lighting mode state by the erasing discharge are changed to the extinguishing mode state.

  By executing the drive as described above according to the pixel drive data GD as shown in FIG. 9, one of the 16 light emission drive patterns as shown in FIG. 9 is performed for each discharge cell PC. As a result, the luminance level for each discharge cell PC represented by the input video signal is expressed by 16 levels of gradation (first to 16th gradations).

  First, in the first gradation representing the lowest luminance, no discharge accompanied by visible light emission within a unit display period of one field or one frame is generated except for a reset discharge. Thereby, a black display corresponding to the luminance level 0 is expressed in the first gradation.

  Next, in the second gradation that represents one level higher than the first gradation, as shown in FIG. 9, the discharge cell PC is set to the lighting mode only by SF1 among the subfields SF1 to SF14. A selective write address discharge is generated, and the discharge cell PC set in this lighting mode is caused to emit a small amount of light (indicated by □). At this time, the luminance level at the time of light emission accompanying the selective write address discharge and the minute light emission discharge is lower than the luminance level at the time of light emission accompanying one sustain discharge. Therefore, when the luminance level visually recognized by the sustain discharge is “1”, the luminance corresponding to the luminance level “α” lower than the luminance level “1” is expressed in the second gradation.

  Next, in the third gradation representing the brightness higher by one level than the second gradation, the selective write address discharge for setting the discharge cell PC in the lighting mode only with SF2 among the subfields SF1 to SF14. Is generated (indicated by a double circle), and a selective erasure address discharge for causing the discharge cell PC to transition to the extinguishing mode is generated in the next subfield SF3 (indicated by a black circle). Therefore, in the third gradation, light emission associated with one sustain discharge is performed only in the sustain process I of SF2 of the subfields SF1 to SF14, and the luminance corresponding to the luminance level “1” is expressed.

  Next, in the fourth gradation that represents one level higher than the third gradation, first, in the subfield SF1, a selective write address discharge for setting the discharge cell PC in the lighting mode is caused, The discharge cell PC set in this lighting mode is subjected to a minute light emission discharge (indicated by a square). Further, in the fourth gradation, a selective write address discharge for causing the discharge cell PC to be set to the lighting mode is caused only by SF2 of the subfields SF1 to SF14 (indicated by a double circle), and the following In subfield SF3, a selective erasure address discharge for causing discharge cell PC to transition to the extinguishing mode is caused (indicated by a black circle). Therefore, in the fourth gradation, the light emission of the luminance level “α” is performed in the subfield SF1, and the sustain discharge accompanied by the light emission of the luminance level “1” is performed only once in the SF2. The luminance corresponding to “α” + “1” is expressed.

  Further, in each of the fifth to 16th gradations, a selective write address discharge for causing the discharge cells PC to be set in the lighting mode is generated in the subfield SF1, and the discharge cells PC set in this lighting mode are caused to emit a small amount of light. (Indicated by □) Then, a selective erasure address discharge for causing the discharge cell PC to transition to the extinguishing mode is caused only in one subfield corresponding to the gradation (indicated by a black circle). Therefore, in each of the fifth to sixteenth gradations, the minute light emission discharge is generated in the subfield SF1, the sustain discharge for one time is generated in SF2, and then the number corresponding to the gradation is continuous. In each of the subfields (indicated by white circles), the sustain discharge is generated for the number of times assigned to the subfield. Thereby, in each of the fifth to 16th gradations, the brightness corresponding to the brightness level “α” + “the total number of sustain discharges generated in one field (or one frame) display period” is visually recognized.

  As described above, the luminance range “0” to “255” indicated by the input video signal is changed to the 16th to 15th gradations by the 16 light emission driving patterns according to the driving shown in FIG. Can be expressed.

  Further, in the driving shown in FIGS. 9 to 11, in the subfield SF1 having the smallest luminance weight, a minute light emission discharge is generated instead of the sustain discharge as the discharge contributing to the display image. At this time, since the minute light emission discharge is a discharge generated between the column electrode D and the row electrode Y, the luminance level at the time of light emission accompanying the discharge is higher than that of the sustain discharge generated between the row electrodes X and Y. Low. Therefore, in the case where the luminance is expressed by one level higher than that of black display (luminance level 0) by the minute light emission discharge (second gradation), the luminance of luminance level 0 is compared to the case where this is expressed by the sustain discharge. The difference is small. Therefore, the gradation expression capability when expressing a low-luminance image is enhanced.

At this time, also in the driving shown in FIGS. 9 to 11, the negative base pulse BP ⁻ is applied in the first selective write address process W1 _W , as in the case of the driving shown in FIGS. over while applied to the electrode Y, the base pulse of the same polarity base pulse BPa ^- to prevent erroneous discharge between the row electrodes X and Y by applying to the row electrodes X.

In the drive shown in FIG. 11, reset discharge is generated in all the discharge cells PC by applying reset pulses (RP1 _Y1 , RP1 _X ) in the first half of the first reset process R1, but during this time, The application of reset pulses (RP1 _Y1 , RP1 _X ) may be stopped, that is, all the row electrodes X and Y may be set to the ground potential (0 volt). That is, in the first half of the first reset process R1, dark contrast is improved so as not to cause reset discharge.

Here, in the driving shown in FIG. 8, the base pulse BPa to be applied to all the row electrodes X in the first selective write address process W1 _W of SF1 ^- the absolute value of the negative peak potential is small, the row electrodes Y and the column It is impossible to suppress erroneous discharge that is induced by the selective write address discharge generated between the electrodes D and erroneously generated between the row electrodes X and Y. On the other hand, the base pulse BPa ^- If larger setting the absolute value of the negative peak potential of, even in the discharge cells PC write scan pulse SP _W is not applied, in accordance with the application of the pixel data pulse DP of high voltage, An erroneous discharge may occur between the row electrode X and the column electrode D. At this time, display at an appropriate gradation corresponding to the luminance level indicated by the input video signal is not performed. Further, in the discharge cell PC driven by the light emission driving pattern corresponding to the first gradation as shown in FIG. 6, the entire image becomes bright due to the erroneous discharge between the row electrode X and the column electrode D as described above, and the luminance is increased. Level 0 black display cannot be realized. That is, the base pulse BPa ^- setting range of the absolute value of the negative peak potential, i.e. the width of the voltage margin has a relatively narrow.

Therefore, the base pulse BPa ^- the absolute value of the negative peak potential to set the larger than the upper limit value of the setting range of driving the PDP50 employ drive pulse sequence shown in place 12 in FIG. 8 To do.

In the drive pulse sequence shown in FIG. 12, the operation of the other parts except for the application period T _K of the wall charge adjusting pulse CP in the first selective write address process W1 _W of SF1 is the one shown in FIG. 8 Is the same. Therefore, hereinafter, it is described only the operation of the interval _{T K} in the first selective write address process W1 _W of SF1 shown in FIG. 12.

That is, in FIG. 12, in the section _{T K} in the first selective write address process W1 _W of SF1, X electrode driver 51, the row electrodes _{X 1} erroneous discharge preventing pulse GP of the wedge-shaped waveform having a negative peak potential Apply to ~ _Xn . The application of the erroneous discharge preventing pulse GP, just before the start of the write address operation (when the row electrodes Y ₁ to the write scan pulse SP _W is applied), the wall charges remaining in the vicinity of all the row electrodes X A part of is deleted. Thus, the base pulse BPa ^- absolute value of the negative peak potential is larger (but less than or equal to the absolute value of the negative peak potential of the erroneous discharge preventing pulse GP) in be set to the above-described row electrodes X and column An erroneous discharge between the electrodes D is suppressed. That is, by setting the absolute value of the negative polarity peak potential in the base pulse BPa ⁻ to be large, erroneous discharge between the row electrodes X and Y is prevented, and erroneous discharge between the row electrode X and the column electrode D is prevented. It is done. Thus, it is possible to rise to ensure selective write address discharge in the first selective write address process W1 _W.

Also, the base pulse BPa ^- when smaller setting the absolute value of the negative peak potential drives the PDP50 employ drive pulse sequence shown in place 13 in FIG. 12. In the drive pulse sequence shown in FIG. 13, except for section _{T W} of the write scan pulse SP _W is sequentially applied to the row electrodes _Y 1 to Y _n in the first selective write address process W1 _W of SF1 The operation in other parts is the same as that shown in FIG. Therefore, hereinafter, it is described only the operation of the section T _W shown in FIG. 13.

That is, according the first in the section T _W selective write address process W1 _W, Y electrode driver 53, as in the case of FIG. 8 and FIG. 12, the base pulse BP having a negative peak potential of ^- row electrodes Y while applying a ₁ to Y _n, and sequentially selectively applying the write scan pulse SP _W having a negative peak potential to the row electrodes _Y 1 to Y _n, respectively. At this time, as in the case of FIGS. 8 and 12, the address driver 55 sequentially applies the pixel data pulse DP based on the pixel drive data bit corresponding to the subfield SF1 for each one display line (m), to the column electrode D. _{1 to} D _m are applied. During this time, the X electrode driver 51 applies a base pulse BP _b ⁻ having a negative peak potential whose absolute value is smaller than the base pulse BP a ⁻ shown in FIGS. 8 and 12 to the row electrodes X _{1 to} X _n . and while the auxiliary scanning pulse SP _X having a negative peak potential, successively alternatively applied to the row electrodes X ₁ to X _n respectively in synchronization with the application timing of the write scan pulse SP _W, respectively . That is, as shown in FIG. 13, the X electrode driver 51 and the Y electrode driver 53 are connected to the row electrode pairs (Y ₁ , X ₁ ), (Y ₂ , X ₂ ), ( Y ₃ , X ₃ ),..., (Y _n , X _n ) are sequentially selected one after the other and the same polarity with respect to the selected row electrode pair (Y, X) at the same timing We are to apply a write scan pulse SP _W and the auxiliary scanning pulse SP _X.

According to such a drive, be occurring selective write address discharge between the column electrode D and the row electrodes Y in response to the application of the write scan pulse SP _W, during which the voltage between the row electrodes X and Y 0 or Since the voltage is close to 0, no erroneous discharge occurs between the row electrodes X and Y. That is, the base pulse BPa ^- preventing thereby preventing erroneous discharge between the column by small setting the absolute value of the negative peak potential in the electrode D and the row electrodes X, erroneous discharge between the row electrodes X and Y It is done. Thus, it is possible to rise to ensure selective write address discharge in the first selective write address process W1 _W.

Incidentally, in the first selective write address process W1 _W shown in FIG. 13, in response to the application of not only the write scan pulse SP _W auxiliary scan pulse SP _X, selected document between the row electrodes Y and column electrodes D A built-in address discharge is generated, and a discharge is also generated between the row electrode X and the column electrode D. According to the discharge generated between the row electrode X and the column electrode D, a positive wall charge is formed in the row electrode X after the discharge, so that the second selective write address process of the next subfield SF2 is performed. selective write address discharge in W2 _W becomes as is caused stably.

Here, carrying out the drive shown in FIG. 13, by varying the negative peak potential of each write scan pulse SP _W and the auxiliary scanning pulse SP _X together to rise to dare discharge between the row electrodes X and Y Wall charge may be replenished. That is, as shown in FIG. 14, in the first selective write address process W1 _W of SF1, the absolute value V _W of the negative polarity peak potential of the write scan pulse SP _{W is set as} the negative polarity peak potential of the auxiliary scan pulse SP _XH. to smaller than the absolute value of V _X. Thus, in the discharge cell PC to the write scan pulse SP _W and the auxiliary scanning pulse SP _XH is simultaneously applied, in accordance with the pixel data pulse DP of high voltage, selective write between the row electrodes Y and column electrodes D An address discharge is generated, and a discharge is also generated between the row electrodes X and Y. The occurrence and the discharge between the row electrodes X and Y, the write scan pulse SP _W and negative peak potential of the auxiliary scanning pulse SP _XH each compared with the case of substantially identical, more wall charges row electrodes It is formed in the vicinity of each of X and Y. Thus, it is possible to rise to selective write address discharge in the second selective write addressing step W2 _W of the next subfield SF2 further stably.

Furthermore, in such drive, the write scan pulse SP _W and the auxiliary scanning pulse SP _XH Upon varying the negative peak potential of each other, the write scan pulse SP _W having a negative polarity absolute value auxiliary scanning pulse SP _XH peak potential It is lower than that. As a result, the selective write address discharge generated in the first selective write address process W1 _W of SF1 is weakened, so that the luminance expressed in the second gradation shown in FIG. 6 is lowered and the luminance change in the dark image is reduced. It becomes possible to express more smoothly.

Further, only the first selective write address process W1 _W of the leading SF1 among the subfields SF1 to SF14, the row electrodes _X 1 to X _n of the row electrodes _X 1 to X _n and _Y 1 to Y _n Alternatively, the selective write address discharge may be generated between the row electrode X and the column electrode D in the discharge cell PC by applying the scan pulse SP only to one.

  FIG. 15 shows another example of the drive pulse application sequence made in view of the above point.

In the drive pulse sequence shown in FIG. 15, the operation of the other parts except for the interval T _W in the first selective write address process W1 _W of SF1 is the same as that shown in FIG. 12. Therefore, hereinafter, it is described only the operation of the interval _{T W} in the first selective write address process W1 _W of SF1 shown in FIG. 15.

Namely, in FIG. 15, in the section _{T W} in the first selective write address process W1 _W of SF1, X electrode driver 51, the base pulse BP having a negative peak potential of ^- the row electrodes _X 1 to X _n While being applied, a write scan pulse SP _WX having a negative peak potential is sequentially and alternatively applied to each of the row electrodes X _{1 to} X _n . At this time, the address driver 55, as in the case of FIG. 12, one display line of pixel data pulses DP based on the pixel drive data bit corresponding to the subfield SF1 (m pieces) one by the column electrodes D ₁ to D _Apply to _m . Further, this over the interval _{T W,} Y electrode driver 53, as mentioned above the base pulse BP ^- to apply to the row electrodes _Y 1 to Y _n, respectively. At this time, in the discharge cell PC to which the high-voltage pixel data pulse DP is applied simultaneously with the write scan pulse SP _WX , a selective write address discharge is generated between the column electrode D and the row electrode X. A discharge is also generated between the row electrodes X and Y. By these discharges, negative wall charges are formed in the vicinity of the row electrode Y and the column electrode D in the discharge cell PC, and positive wall charges are formed in the row electrode X. The discharge cell PC is in the lighting mode. Set to state. On the other hand, the selective write address discharge as described above is generated between the column electrode D and the row electrode X in the discharge cell PC to which the pixel data pulse DP of a low voltage (0 volt) is applied simultaneously with the write scan pulse SP _WX. Will not occur. Therefore, no wall charges are formed in the discharge cell PC, so that the extinguishing mode is set.

Moreover, carrying out the drive shown in FIG. 15, in the first selective writing addressing process W1 _W of SF1, as shown in FIGS. 16 to 18, stop the application of the wall charge adjusting pulse CP to the row electrodes Y with (ground potential fixing) to the potential of the base pulse BP to be applied to all the row electrodes Y over the interval T _W, the base pulse BP applied to all the row electrodes X ^- may be higher than the. In this case, in the example shown in FIG. 16, over the interval T _W of the first selective write address process W1 _W of SF1, Y electrode driver 53, the base pulse BP ^- base having a negative peak potential of high potential than pulse BPc ^- and applies to all the row electrodes Y. Further, in the example shown in FIG. 17, over the interval _{T W} of the first selective write address process W1 _W of SF1, Y electrode driver 53 is set to ground potential all the row electrodes Y (0 volt). Further, in the example shown in FIG. 18, over the interval _{T W} of the first selective write address process W1 _W of SF1, Y electrode driver 53, the base pulse BP _Y ⁺ having a positive polarity peak electric potential to all the row electrodes Y Apply.

Even when the driving shown in FIGS. 15 to 18 (section T _W of the first selective write address process W1 _W of SF1) is performed, the high-voltage pixel data is the same as when the driving shown in FIG. 14 is performed. In response to the application of the pulse, a selective write address discharge is generated between the row electrode X and the column electrode D in the discharge cell PC, and a discharge is also generated between the row electrodes X and Y. As a result of these discharges, negative wall charges are formed in the vicinity of the row electrode Y and the column electrode D in the discharge cell PC, and positive wall charges are formed in the row electrode X, respectively. Is set to the state. At this time, since the discharge is generated between the row electrodes X and Y together with the selective write address discharge, more wall charges are generated as compared with the case where the drive in which only the selective write address discharge is generated is executed. It is formed in the vicinity of each of the row electrodes X and Y. Thus, it is possible to rise to selective write address discharge in the second selective write addressing step W2 _W of the next subfield SF2 stably.

It is a figure which shows schematic structure of the plasma display apparatus by this invention. It is a front view which shows typically the internal structure of PDP50 seen from the display surface side. It is a figure which shows the cross section on the VV line | wire shown by FIG. It is a figure which shows the cross section on the WW line shown by FIG. 3 is a diagram schematically showing an MgO crystal contained in a phosphor layer 17. FIG. It is a figure which shows the light emission drive pattern for every gradation. It is a figure which shows an example of the light emission drive sequence employ | adopted in the plasma display apparatus shown by FIG. It is a figure which shows the drive pulse application sequence of the various drive pulses applied to PDP50 according to the light emission drive sequence shown by FIG. It is a figure which shows another example of the light emission drive pattern for every gradation. It is a figure which shows another example of the light emission drive sequence employ | adopted in the plasma display apparatus shown by FIG. It is a figure which shows the drive pulse application sequence of the various drive pulses applied to PDP50 according to the light emission drive sequence shown by FIG. It is a figure which shows the modification of the drive pulse application sequence shown by FIG. It is a figure which shows the modification of the drive pulse application sequence shown by FIG. It is a figure which shows the modification of the drive pulse application sequence shown by FIG. It is a figure which shows the modification of the drive pulse application sequence shown by FIG. FIG. 16 is a diagram showing a first modification of the drive pulse application sequence shown in FIG. 15. It is a figure which shows the 2nd modification of the drive pulse application sequence shown by FIG. It is a figure which shows the 3rd modification of the drive pulse application sequence shown by FIG.

Explanation of main part codes

50 PDP
51 X electrode driver 53 Y electrode driver 55 Address driver
56 Drive control circuit

Claims (13)

A first substrate and a second substrate are arranged to face each other, and discharge cells are formed at intersections of a plurality of row electrode pairs formed on the first substrate and a plurality of column electrodes formed on the second substrate. A secondary electron emission material including a magnesium oxide crystal that emits cathode luminescence light having a peak in a wavelength range of 200 to 300 nm when excited by an electron beam on the second substrate of the discharge cell; and a phosphor material A plasma display panel formed with a plurality of subfields for each unit display period of a video signal;
In the first subfield within the unit display period, a write address process for selectively setting each of the discharge cells to a lighting mode state, and a discharge light emitting process for discharging only the discharge cells in the lighting mode state. And run
In the subsequent subfield provided immediately after the first subfield, the write address process and a sustain process for sustaining only the discharge cells in the lighting mode state by applying a sustain pulse to the row electrode pair. And run
In the write address process of the first subfield, a scan pulse is sequentially applied to one row electrode of each of the row electrode pairs, and a base pulse having a peak potential having the same polarity as the peak potential of the scan pulse is A method for driving a plasma display panel, wherein a discharge for selectively setting the discharge cell to the state of the lighting mode is generated by applying the voltage to the other row electrode of each row electrode pair.   Within one unit display period, for the discharge cells set in the lighting mode state in the write address process of the subsequent subfield, the lighting is performed in the write address process of the first subfield. 2. The method of driving a plasma display panel according to claim 1, wherein the mode is set.   2. The plasma display panel according to claim 1, wherein in the discharge light emission process, only the discharge cells in the lighting mode are caused to emit sustain discharge by applying the sustain pulse to the row electrode pair. Driving method.   4. The driving method of the plasma display panel according to claim 3, wherein the number of times of application of the sustain pulse applied in the sustain process in each of the first subfield and the subsequent subfield is an odd number.   Within each of the subfields within the unit display period, the write address process is performed in a subfield arranged ahead of a predetermined one subfield, while the subfield is arranged after the one subfield. 2. The method of claim 1, wherein an erase address process for selectively setting each of the discharge cells to a turn-off mode is performed in a subfield.   4. The method of driving a plasma display panel according to claim 3, wherein a peak potential of the sustain pulse applied in the first subfield is less than a peak potential of the sustain pulse applied in the subsequent subfield. . In the discharge light emission process, immediately after the last sustain pulse is applied to the one row electrode,
A wall charge adjustment pulse having a peak potential which is the same polarity as the peak potential of the scan pulse and whose absolute value is equal to or less than the absolute value of the peak potential of the sustain pulse applied in the subsequent subfield. 4. The method of driving a plasma display panel according to claim 3, wherein the driving is applied to the one row electrode.   In the write address process of the first subfield, a wall charge adjustment pulse having the same polarity as the peak potential of the base pulse is applied to the other row electrode immediately before the first scan pulse is applied. The method for driving a plasma display panel according to claim 1.   In the write address process of the first subfield, each of the row electrode pairs is sequentially and selectively scanned, and simultaneously with the application of the scanning pulse to one of the row electrodes of the row electrode pair that has been scanned. 2. The method of driving a plasma display panel according to claim 1, wherein an auxiliary scan pulse having the same polarity as the peak potential of the scan pulse is applied to the other row electrode of the row electrode pair to be scanned. .   The method of claim 9, wherein the absolute value of the peak potential of the auxiliary scan pulse is larger than the absolute value of the peak potential of the scan pulse. A first substrate and a second substrate are arranged to face each other, and discharge cells are formed at intersections of a plurality of row electrode pairs formed on the first substrate and a plurality of column electrodes formed on the second substrate. Driving a plasma display panel in which a phosphor layer containing a phosphor material is formed on the second substrate of the discharge cell, in which gradation driving is performed by a plurality of subfields for each unit display period of a video signal. A method,
In each of the first subfield in the unit display period and the subsequent subfield provided immediately after the first subfield, a write address process for selectively setting each of the discharge cells to a lighting mode state, and the row electrode Performing a sustain process in which only a discharge cell in the lighting mode state is subjected to a sustain discharge by applying a sustain pulse to the pair;
In the write address process of the subsequent subfield, by sequentially applying a scan pulse to one row electrode of each of the row electrode pairs, the discharge cells are selectively set to the lighting mode state. Causing a discharge,
In the write address step of the first subfield, an auxiliary scan pulse having the same polarity as the peak potential of the scan pulse is sequentially applied to the other row electrode of each row electrode pair,
The method of driving a plasma display panel, wherein the peak potential of the auxiliary scan pulse is set to the same polarity side as the potential applied to the one row electrode when the auxiliary scan pulse is applied.   12. The phosphor layer includes a secondary electron emission material including a magnesium oxide crystal that is excited by an electron beam and emits cathode luminescence having a peak in a wavelength range of 200 to 300 nm. A method for driving a plasma display panel according to claim 1. A first substrate and a second substrate are arranged to face each other, and discharge cells are formed at intersections of a plurality of row electrode pairs formed on the first substrate and a plurality of column electrodes formed on the second substrate. A secondary electron emission material including a magnesium oxide crystal that emits cathode luminescence light having a peak in a wavelength range of 200 to 300 nm when excited by an electron beam on the second substrate of the discharge cell; and a phosphor material A plasma display panel formed with a plurality of subfields for each unit display period of a video signal;
In each of the first subfield in the unit display period and the subsequent subfield provided immediately after the first subfield, a write address process for selectively setting each of the discharge cells to a lighting mode state, and the row electrode Performing a sustain process in which only a discharge cell in the lighting mode state is subjected to a sustain discharge by applying a sustain pulse to the pair;
In the write address process of the first subfield, a ground potential or a negative electrode is applied while applying a negative wall charge adjustment pulse to one row electrode of the row electrode pair immediately before the first scan pulse is applied. Applying a characteristic wall charge adjustment pulse to the other row electrode;
In the sustain process of each of the first sub-field and the subsequent sub-field, the discharge cell is in the lighting mode by applying the sustain pulse to the one row electrode and setting the other row electrode to the ground potential. A plasma display panel driving method comprising: applying a negative wall charge adjusting pulse to the one row electrode after sustaining only the sustain discharge.

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