JP2010016590A - Amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a cascode-connected amplifier which is small and stable over a wide band. <P>SOLUTION: In the cascode-connected amplifier, a high frequency signal is inputted to an input terminal connected to a gate electrode of a first field effect transistor, a source electrode of a second field effect transistor is connected to a drain electrode of the first field effect transistor, and an amplified high frequency signal is outputted from an output terminal connected to a drain electrode of the second field effect transistor, wherein the first field effect transistor is an enhanced field effect transistor, the second field effect transistor is a depletion type field effect transistor, and a gate electrode of the second field effect transistor is grounded without going through a capacitor element. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an amplifier that constitutes a low-noise amplifier that amplifies a high-frequency weak signal received by a wireless device or the like.

  In high-frequency wireless communication such as a cellular phone and a wireless LAN terminal, a received signal is usually weak, so it is necessary to amplify the signal before demodulating it. If noise is mixed at this time, the S / N ratio of the signal deteriorates, and the demodulated signal includes errors and noise. To avoid this, a low noise amplifier is used for the initial amplification of the received signal.

  As a low-noise amplifier, an amplifier circuit in which an enhancement type field effect transistor (hereinafter also simply referred to as an E-type FET) is cascode-connected has been used. FIG. 6 shows a circuit diagram of a conventional cascode-connected amplifier that has been used. By cascode connection, the load of the first transistor 1 to which a signal is input from the input terminal 5 is suppressed to a low impedance, so that the so-called mirror effect is reduced and the high frequency characteristics are improved. In addition, since the static current is shared by the first transistor and the second transistor 2 connected in cascode, the static current is less than that of a normal two-stage amplifier. When the amplifier having this configuration is configured on the same substrate, the two transistors have the same threshold voltage.

  Patent Document 1 discloses a high-frequency power amplifier circuit configured using cascode-connected field effect transistors. The configuration disclosed in Patent Document 1 has a cascode connection between a drain electrode of a depletion type field effect transistor (hereinafter also simply referred to as a D-type FET) and a source electrode of an enhancement type field effect transistor for the purpose of simplifying the circuit configuration. This is a high-frequency amplifier circuit. At this time, a signal is input to the gate electrode of the D-type FET and output from a terminal connected to the drain electrode of the E-type FET. Since the gate electrode of the E-type FET needs to be biased to a positive voltage and needs to be grounded in the frequency band of the input signal, it is grounded via a capacitor. Note that the threshold voltage of the D-type FET is negative, and the threshold voltage of the E-type FET is positive.

JP 2000-101356 A

  However, in the conventional configuration shown in FIG. 6, the bias voltage of the gate electrode of the second cascode-connected second field effect transistor needs to be set higher than that of the source electrode of the first field effect transistor transistor. For this reason, since the bias voltage of the gate electrode of the first field effect transistor transistor is different from the bias voltage of the gate electrode of the second field effect transistor, it is necessary to generate two types of bias voltages by the bias circuits 6a and 6b. Arise. This increases the circuit scale, making it difficult to reduce the size of the high-frequency low-noise amplifier and increasing the cost. This also applies to the configuration disclosed in Patent Document 1. That is, since the source electrode potential of the D-type FET is 0, the optimum gate electrode bias potential in the pHEMT process transistor is usually negative. However, since it is difficult to generate a negative potential, the bias circuit becomes complicated and the chip area increases. Further, since the optimum values of the bias potentials of the gate electrodes of the E-type FET and the D-type FET are different, there are two types of potentials that need to be generated. Therefore, the bias circuit is complicated again in this case.

  In the configuration shown in FIG. 6, the gate electrode of the second transistor needs to be grounded at a high frequency in the frequency band of the received signal to be amplified. For this reason, the gate electrode of the second transistor is usually connected to the ground via a capacitor. In order for the gate electrode to be regarded as ground, this capacitance needs to have a sufficiently small impedance, so that a large area is required. This also makes it difficult to reduce the size of the high-frequency low-noise amplifier and leads to an increase in cost. Furthermore, when the gate electrode of the second transistor is grounded via a capacitor, the characteristic of the cascode connection can be exhibited only under conditions where the impedance of the capacitor is sufficiently small, that is, at a sufficiently high frequency, so that the characteristics are not stable. is there. This also applies to the configuration disclosed in Patent Document 1. In other words, the gate electrode of the E-type FET needs to be grounded at a high frequency, but since the bias potential is not 0 V, it needs to be grounded via a capacitor or the like, so that the ground state can be stably maintained over a wide band. Is difficult.

  In view of the above-described problems, an object of the present invention is to realize a cascode-connected amplifier that is simple in size and stable over a wide band.

  The amplifier of the present invention includes first and second field effect transistors, a high frequency signal is input to an input terminal connected to the gate electrode of the first field effect transistor, and the first field effect transistor includes: The drain electrode is connected to the source electrode of the second field effect transistor, and is a cascode connection type amplifier that outputs an amplified high frequency signal from an output terminal connected to the drain electrode of the second field effect transistor. The first field effect transistor is an enhancement type field effect transistor, the second field effect transistor is a depletion type field effect transistor, and the gate electrode of the second field effect transistor does not pass through a capacitor. It is characterized by being grounded. With this configuration, the amplifier bias circuit can be simplified and the ground state of the gate electrode of the second field effect transistor can be stabilized.

  In the amplifier, the first and second field effect transistors are formed on one main surface side of the same semiconductor substrate, and a gate electrode of the second field effect transistor is a through-hole penetrating the semiconductor substrate. It is preferable that the other main surface of the semiconductor substrate is grounded through a hole. With such a configuration, it is possible to stably ground the second gate electrode even in a high frequency band.

  In the amplifier, it is preferable that a drain-source saturation voltage of the first field effect transistor is less than an absolute value of a threshold voltage of the second field effect transistor. With this configuration, a high amplification factor can be ensured.

  In the amplifier, a bias voltage generating circuit for supplying a bias voltage to the gate electrode of the first field effect transistor is preferably integrated with the amplifier on the same substrate. With this configuration, since the characteristics of the transistor used in the bias circuit are very close to the characteristics of the first field effect transistor, the bias voltage is set so as to cancel the characteristic fluctuation caused by the process fluctuation of the first field effect transistor. Can be generated.

  In the amplifier, the source electrode of the first field effect transistor is preferably grounded via a bonding wire. With this configuration, the input matching of the amplifier can be improved without using an external component such as a chip inductor.

  In the amplifier, it is preferable that the first field effect transistor and the second field effect transistor are pseudo lattice matched high electron mobility transistors. With this configuration, for example, it becomes easy to configure a D-type FET and an E-type FET having excellent characteristics in which the absolute value of the threshold voltage exceeds 1 V on the same substrate.

  According to the present invention, a cascode-connected amplifier that is small and stable over a wide band can be realized.

  The technical idea of the present invention will be described based on specific embodiments. FIG. 1 is a circuit diagram of the amplifier according to this embodiment. Such an amplifier has a first field effect transistor 1 and a second field effect transistor 2, and a cascode connection in which the drain electrode of the first field effect transistor 1 is connected to the source electrode of the second field effect transistor 2. Type low noise amplifier. The high frequency signal is input from the input terminal 5 connected to the gate electrode of the first field effect transistor 1, and the amplified high frequency signal is output from the output terminal 8 connected to the drain electrode of the second field effect transistor. . A capacitor 16 is connected between the gate electrode of the first field effect transistor 1 and the input terminal 5 for DC cut. However, the bias voltage of the gate electrode of the first field effect transistor 1 can be reduced by another method. Capacitor 16 may be omitted if maintained. An input matching circuit for further matching may be connected to the input terminal 5. A DC voltage from the power source is supplied to the drain electrode of the second field effect transistor 2 via the inductor 3. An output matching circuit may be further connected to the output terminal 8. The inductor 3 is not essential to this embodiment, and a DC voltage may be supplied to the drain electrode of the second field effect transistor 2 using another configuration.

  The first field effect transistor 1 is an enhancement type field effect transistor (E type FET), and the second field effect transistor 2 is a depletion type field effect transistor (D type FET). The first field effect transistor 1 and the second field effect transistor 2 are formed on the same main surface side of the same semiconductor substrate in order to reduce the size and simplify the manufacturing process. The method is not particularly limited. It is also possible to form the first field effect transistor 1 and the second field effect transistor 2 on different semiconductor substrates. The threshold voltage Vt1 of the first field effect transistor 1 which is an E-type FET is 0.2V. When the gate-source voltage Vgs1 of the first field effect transistor 1 exceeds Vt1, a current flows between the drain-source. The source electrode is grounded via the inductor 9. The reason for grounding through the inductor is to facilitate input matching with the outside. The gate electrode of the first field effect transistor 1 is biased to about 0.4V, and at this time, the saturation voltage between the drain and the source is about 0.5V. The second field effect transistor 2 which is a depletion type field effect transistor has a threshold voltage Vt2 of -1V. In this case, the drain-source saturation voltage of the first field effect transistor 1 is adjusted to a sufficiently small value that is 1/2 or less of the absolute value of the threshold voltage of the second field effect transistor 2.

  The gate electrode of the second field effect transistor 2 is grounded on the other main surface side of the semiconductor substrate through a through hole 4 penetrating the semiconductor substrate. The through-hole 4 connects one main surface side of the semiconductor substrate to the other main surface side (back surface) opposite to the semiconductor substrate, and the back surface of the semiconductor substrate is at ground potential. That is, the gate electrode of the second field effect transistor is grounded without passing through a capacitor. With this configuration, a stable ground state can be realized in a wide frequency band. The configuration in which the gate electrode of the second field effect transistor 2 is grounded without using a capacitor is not limited to the embodiment shown in FIG. For example, when flip chip mounting is applied, grounding may be performed without passing through the through hole. In any case, by grounding the gate electrode of the second field effect transistor without passing through the capacitor, the ground state on the low frequency side is particularly stabilized. Further, in order to stably ground the gate electrode of the second field effect transistor 2 over a wide band, the distance between the gate electrode of the second field effect transistor 2 and the through hole 4 (shown in FIG. 3). The distance d) is preferably smaller than one tenth of the wavelength at the lower frequency of the cutoff frequency of the first field effect transistor 1 or the second field effect transistor 2. Such a configuration stabilizes the grounding state particularly on the high frequency side.

  As described above, in this embodiment, the saturation voltage between the drain and the source of the first field effect transistor 1 that is an E-type FET is the absolute value of the threshold voltage of the second field effect transistor 2 that is a D-type FET. The bias voltage, the gate width of the field effect transistor, and the process were adjusted so as to be sufficiently smaller. When a current flows through the second field effect transistor 2 that is a D-type FET, the potential of the source electrode becomes smaller than the absolute value of Vt2. If this potential is smaller than the drain-source saturation voltage, the signal amplification factor by the first field effect transistor 1 which is an E-type FET becomes small. In order to avoid such a state, it is more preferable that the saturation voltage between the drain and the source of the first field effect transistor 1 is less than the absolute value of the threshold voltage of the second field effect transistor 2.

  By using the above-described cascode-connected amplifier in which the source electrode of the second field-effect transistor 2 is connected to the drain electrode of the first field-effect transistor 1, a kind of potential that the bias circuit needs to generate is used. As a result, the bias circuit is simplified to reduce the size of the amplifier. In the embodiment shown in FIG. 1, a voltage is supplied from the bias circuit 6a to the gate electrode of the first field effect transistor 1 via the bias output terminal 7a. On the other hand, a bias circuit is not connected to the gate electrode of the second field effect transistor 2. A specific configuration of the bias circuit 6a of FIG. 1 is shown in FIG. The enhancement type field effect transistor 10 in FIG. 2 has the same threshold voltage as that of the first field effect transistor 1. When a voltage is supplied from the outside to the voltage supply terminal Vb, a current flows through the resistor 11, and a voltage corresponding to the current value is generated at the gate electrode of the field effect transistor 10. This voltage is supplied to the gate electrode of the first field effect transistor 1 through the resistor 12. The resistor 12 needs to have a sufficiently large resistance value in order to prevent a high frequency signal from flowing into the bias circuit and to prevent noise generated in the bias circuit from flowing out to the high frequency low noise amplifier. In this embodiment, it is 2 kΩ.

  FIG. 3 shows a first field effect transistor 1 that is an E-type FET, a second field effect transistor 2 that is a D-type FET, a through hole 4, a bias formed on the main surface side of the semiconductor substrate according to the present embodiment. The layout of the field effect transistor 10, resistors 11 and 12, source connection pad 13 connected to the source electrode, input pad 14 serving as an input terminal, output pad 15 serving as an output terminal, and voltage supply terminal Vb in the circuit 6a is shown. . The source electrode of the first field effect transistor 1 is grounded via a bonding wire. The inductor 9 shown in FIG. 1 is realized by the bonding wire connected to the source connection pad 13. This is because the frequency of the high-frequency signal in this embodiment is as high as 5 GHz, and is sufficiently large so that the inductance of the bonding wire can be used. The through hole 4 grounds the gate electrode of the second field effect transistor, and also grounds the source electrode of the field effect transistor 10 in the bias circuit.

  The first field effect transistor and the second field effect transistor include a MOS (Metal Oxide Silicon) FET integrated on a silicon substrate and a pseudo lattice matched high electron mobility transistor (p-HEMT integrated on a GaAs substrate). Field effect transistors such as FET) can be used. In particular, a high frequency low noise amplifier having excellent high frequency characteristics and noise characteristics can be realized by using a pseudo lattice matched high electron mobility transistor.

  FIG. 4 shows the gain and NF of the high frequency low noise amplifier of this embodiment. When the DC power supply voltage is 3 V, a high gain of 10 dB or more is obtained at 5 to 6 GHz, although the bias current is 11 mA and the power consumption is low. Further, at 5 GHz, a high gain of 15 dB or more and a good noise characteristic of about 1.25 dB of noise figure were secured.

  Next, another embodiment according to the present invention is shown in FIG. In such an embodiment, the source electrode of the first field effect transistor 1 is grounded without passing through an inductor. Instead, a matching circuit 17 is connected to the gate electrode of the first field effect transistor 1. When the source electrode is connected via an inductor, the voltage generated in the inductor becomes negative feedback, and the gain is reduced. When it is necessary to increase the gain, it is effective to ground directly without using an inductor. However, in such a configuration, it is preferable to provide an input matching circuit in order to deteriorate the matching state of the input impedance of the gate electrode.

1 is a circuit diagram of an amplifier according to an embodiment of the present invention. It is a circuit diagram of the bias circuit used for the amplifier which concerns on embodiment of this invention. FIG. 3 is a layout diagram of an amplifier according to an embodiment of the present invention. It is the figure which showed the frequency characteristic of the gain and noise factor of the amplifier which concerns on embodiment of this invention. It is a circuit diagram of the amplifier which concerns on other embodiment of this invention. It is a circuit diagram of the conventional high frequency low noise amplifier.

Explanation of symbols

1: First field effect transistor 2: Second field effect transistor 3, 9: Inductor 4, 4a: Through hole
5: Input terminal 6a, 6b: Bias circuit 7a, 7b: Bias output terminal 8: Output terminal 10: Field effect transistor 11, 12: Resistor 13: Source connection pad 13
14: Input pad 15: Output pad

Claims (6)

A first field effect transistor; a high frequency signal is input to an input terminal connected to the gate electrode of the first field effect transistor; and the drain electrode of the first field effect transistor A cascode-connected amplifier to which a source electrode of a second field effect transistor is connected and an amplified high frequency signal is output from an output terminal connected to a drain electrode of the second field effect transistor;
The first field effect transistor is an enhancement type field effect transistor, and the second field effect transistor is a depletion type field effect transistor;
An amplifier, wherein the gate electrode of the second field effect transistor is grounded without passing through a capacitor. The first and second field effect transistors are formed on one main surface side of the same semiconductor substrate,
2. The amplifier according to claim 1, wherein a gate electrode of the second field effect transistor is grounded on the other main surface side of the semiconductor substrate through a through hole penetrating the semiconductor substrate.   3. The amplifier according to claim 1, wherein a drain-source saturation voltage of the first field effect transistor is less than an absolute value of a threshold voltage of the second field effect transistor. amplifier The amplifier according to any one of claims 1 to 3,
An amplifier, wherein a bias voltage generating circuit for supplying a bias voltage to the gate electrode of the first field effect transistor is integrated with the amplifier on the same substrate. 5. The amplifier according to claim 1, wherein a source electrode of the first field effect transistor is grounded via a bonding wire. 6. The amplifier according to claim 1, wherein the first field effect transistor and the second field effect transistor are pseudo lattice matched high electron mobility transistors.

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