JP2010008598A - Video display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an video display device capable of enhancing the pseudo resolution of even a display device having a low-resolution display means. <P>SOLUTION: The video display device for displaying a video includes: a video data acquisition means which acquires video data; a sub-frame image generation means which generates sub-frame image data which is image data for displaying a plurality of sub-frame images to be displayed in one cycle and shifts each sub-frame image in a horizontal direction by one sub-pixel per display to display the sub-frame, from the acquired video data; and a display means which is provided with a screen wherein one pixel comprises arrangement of RGB sub-pixels, and displays a video on the basis of the video data or the sub-frame image data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a video display device, and more particularly to a video display device that improves the resolution in a pseudo manner.

  Currently, display pixels such as LCD, PDP, and organic EL, which are widely used in the market, are configured by combining R (red), G (green), and B (blue) sub-pixels as shown in FIG. The screen is configured by arranging a predetermined number of these pixels in the horizontal and vertical directions. For example, in the case of a full HD standard display panel, 1920 pixels in the horizontal direction and 1080 pixels in the vertical direction are arranged.

  If the number of pixels constituting the screen increases, the resolution can be increased accordingly and the image quality can be improved. Therefore, a video display device having 8.84 million pixels (4096 × 21.6 million pixels) exceeding the Full HD standard has also appeared. However, increasing the resolution (number of pixels) causes problems such as an increase in the cost of the display panel itself and an increase in the number of output terminals of a driver for driving the pixels. Therefore, a technique for increasing the resolution by artificially increasing the screen resolution is disclosed.

  In an image display system using a light reflecting element, a technique for displaying a plurality of subframe images generated from video data by offsetting each subframe image for projection and increasing the resolution in a pseudo manner is disclosed. (For example, refer to Patent Document 1).

Further, although not a technique for artificially increasing the resolution, a technique for displaying a plurality of subframe images during one frame period to improve gradation values and image quality and further reduce power consumption is disclosed. (For example, refer to Patent Document 2-5.)
Here, one frame cycle is a cycle in which frame images constituting video data are displayed.
Special table 2008-503770 JP 2004-326044 A JP 2007-163580 A JP 2007-114496 A JP 2004-191836 A

  If the resolution can be increased in a pseudo manner without increasing the number of pixels, it is effective in terms of the cost of the display device. In addition, as the resolution increases, the aperture ratio of the sub-pixels constituting the pixel also becomes narrower, causing a reduction in luminance. Therefore, if the resolution can be increased in a pseudo manner, the aperture ratio of the sub-pixels must also be decreased. Therefore, a decrease in luminance can be suppressed.

However, the technique disclosed in Patent Document 1 displays a subframe image projected on a screen or the like by offsetting the display, and for a display device that forms a screen with pixels having a predetermined arrangement, Technology is difficult to adapt.
In addition, the invention of Patent Document 2-5 is not intended to increase the resolution in a pseudo manner.

  The present invention has been made in view of the above problems, and provides a video display device capable of increasing the resolution in a pseudo manner even for a display device having a display unit having a low resolution.

  In order to solve the above problems, according to one aspect of the present invention, in a video display device for displaying video, video data acquisition means for acquiring video data, and a plurality of subs configured from the acquired video data Subframe image generating means for generating subframe image data for displaying a frame image, the subframe image data for displaying each subframe image shifted in the horizontal direction by a predetermined subpixel for each display; The display device includes a screen in which pixels are configured by an array of RGB sub-pixels, and displays video based on the video data or sub-frame image data.

In the invention configured as described above, the sub-frame image generation means is a plurality of image data displayed in the same cycle from the video data acquired by the video data acquisition means, and a predetermined sub-pixel for each image data. Sub-frame image data for displaying a sub-frame image configured to be shifted in the horizontal direction by the amount is generated. The display means displays the subframe image based on the generated subframe image data.
For this reason, a sub-frame image that is shifted in the horizontal direction by one sub-pixel for each display is displayed on the display panel, so that the emission center of the pixel changes for each display. Therefore, the resolution can be increased in a pseudo manner on the display panel. Therefore, it is possible to suppress an increase in cost of the driver circuit and the like, and it is possible to suppress a decrease in the aperture ratio of the subpixel due to an increase in resolution.

Preferably, the sub-frame image generation unit generates sub-frame image data for displaying the sub-frame image obtained by shifting the sub-frame image in the horizontal direction by one sub-pixel for each display order.
In the invention configured as described above, since the light emission center of the image is shifted by one subpixel in accordance with the display order of the subframe images, the motion of the video between the frame periods can be interpolated, and the smoother Can express movement.

  Preferably, the sub-frame image generation unit generates three pieces of sub-frame image data from one frame image data constituting the video data.

Preferably, the sub-frame image generation unit generates a plurality of sub-frame image data using a pixel column for each predetermined pixel in the frame image data.
In the invention configured as described above, since the displayed sub-frame image is composed of image data composed of different pixel columns, the motion of the video composed of each sub-frame image can be made smoother. .

  Preferably, the sub-frame image generation unit is a timing controller for controlling the display unit.

Preferably, the sub-frame image generation means is an image quality adjustment circuit for performing image processing on the acquired video data.
In the invention configured as described above, the work area used for performing the processing according to the present invention can be realized by the buffer memory provided in the image quality adjustment circuit, and the cost increase can be suppressed.

  As another aspect of the present invention, the sub-frame image generation means is a timing controller for controlling the display means, and from each frame image data constituting the video data, every three pixels in the frame image data. The sub-frame image data is generated by generating three pieces of sub-frame image data using the pixel array and shifting the sub-frame image by one sub-pixel in the horizontal direction for each display order of the sub-frame images. Is generated.

  As described above, according to the present invention, the resolution can be increased in a pseudo manner even for a display device having a display unit with a low resolution.

Embodiments of the present invention will be described below in the following order with reference to the drawings. In addition, the part which attached | subjected the same code | symbol shows the same or equivalent part, and the description is not repeated.
1. Summary of the invention:
2. First embodiment:
3. Second embodiment:
4). Other embodiments:

1. Summary of the invention:
FIG. 1 is a block diagram illustrating a video display apparatus according to the present invention. The video display device includes a video data acquisition unit that acquires video data, a subframe image generation unit that generates subframe image data from the acquired video data, and an array of RGB subpixels. And display means for displaying video based on video data or subframe image data.
A schematic function of the video display device will be described. When the video data acquisition unit acquires the video data, the subframe image generation unit generates subframe image data from the video data. The display means displays a video based on the generated subframe image.

  FIG. 2 is an image diagram for explaining how a subframe image is generated from video data. The subframe image generation means according to the present invention generates subframe image data from the frame image data constituting the acquired video data. At this time, the subframe image generation means configures the data so that the subframe image displayed during the frame period is displayed by being shifted in the horizontal direction by a predetermined subpixel every time the image is displayed. For this reason, the light emission center of the image is shifted by a predetermined sub-pixel according to the display order of the sub-frame images, so that the motion of the video between the frame periods can be interpolated and a smoother motion can be expressed. .

  FIG. 3 is an image diagram for explaining the relationship between display periods of frame images and subframe images. For example, assume that three sub-frame images are generated from one frame image. Also, the subframe images are named as a first subframe image, a second subframe image, and a third subframe image according to the display order. If the frame period for displaying the frame image is 60 Hz (16.66 msec), the display period of the three sub-frame images generated from the frame image is 20 Hz (5. 55 msec). For this reason, the sub-frame images are displayed on the screen at a cycle of 20 Hz. Of course, the display period of each subframe image does not need to be equal.

  FIG. 4 is an image diagram for explaining a subframe image according to the present invention. In this figure, the interior surrounded by a thick frame is the display position of each sub-frame image. Here, the shift between the sub-frame images is one sub-pixel, but is not limited to this. As shown in FIG. 4, when the display start position of the first subframe image is the first pixel, the display start position of the second subframe image is the horizontal direction by one subpixel compared to the first subframe image. The G sub-pixels in the first pixel row are shifted to. Similarly, the display start position of the third sub-frame image is the B sub-pixel of the first pixel row that is shifted in the horizontal direction by one sub-pixel compared to the display start position of the second sub-frame image. The above-described shift between the subframe images is repeatedly performed at the same period.

  FIG. 5 is an image diagram for explaining the position of the light emission center in each sub-frame image. In this figure, for the sake of convenience, each sub-frame image is displayed with only the first pixel row. When each sub-frame image displayed at a predetermined period is displayed by shifting by one sub-pixel for each display, the display means displays each pixel in a GBR configuration during the display period of the second sub-frame image. To drive. Similarly, in the display period of the third sub-frame image, the display unit drives the sub-pixel configuration array to be BRG. Therefore, when each subframe is displayed, the emission center of the pixel in the display means is G when the first subframe image is displayed, B when the second subframe image is displayed, and the third subframe. R when the image is displayed. As a result, the light emission center is shifted by one subpixel in the horizontal direction for each display of each sub-frame image, so that the viewer visually recognizes as if the resolution of the video has increased in a pseudo manner. It will be.

2. First embodiment:
In the present embodiment, description will be given based on a television receiver as a video display device. FIG. 6 is a block diagram illustrating a configuration of the television receiver. The television receiver 100 includes a tuner unit 11, an AD conversion circuit 12, an input selection circuit 13, a display size conversion circuit 21, an image quality adjustment circuit 22, a display timing control circuit (timing controller) 30, and a display unit. 40. The display unit 40 includes a liquid crystal display panel 41 and a driver circuit 42. In the first embodiment, the video acquisition unit includes a tuner unit 11, an AD conversion circuit 12, and an input selection circuit 13. Further, the sub-frame image generation means is constituted by a display timing control circuit 30. Further, the display means is constituted by the display unit 40.

  A schematic operation of the television receiver 100 will be described. The television broadcast signal received by the tuner unit 11 or the video signal directly input to the AD conversion circuit 12 via the input terminal is analog / digital converted by the AD conversion circuit 12 and output as video data. Further, the input selection circuit 13 supplies either the video data input through the AD conversion circuit 12 or the video data directly input to the input selection circuit 13 to the display size conversion circuit 21 in accordance with a command input from a remote control device or the like. Output. The display size conversion circuit 21 converts the size of the input video data. Further, the image quality adjustment circuit 22 performs predetermined image quality adjustment on the video data. Then, the display timing control circuit 30 generates a timing control signal based on the input video data, and outputs the video data and the timing adjustment signal to the display unit 40. In the display unit 40, the video data is converted from digital to analog based on the input timing control signal by the driver circuit 42, and each pixel of the liquid crystal display panel 41 is driven.

  In the first embodiment, the display timing control circuit 30 realizes a subframe image generation unit according to the present invention. The display timing control circuit 30 generates subframe image data and a timing control signal corresponding to the display timing of the subframe image data based on the video data input from the image quality adjustment circuit 22. The display timing control circuit 30 outputs the generated subframe image data and the timing control signal to the driver circuit 42.

  FIG. 7 is a block diagram illustrating the inside of the display timing control circuit 30. The display timing control circuit 30 includes a buffer memory 31 having a function of temporarily storing input video data, a subframe image generation module 32 having a function of generating subframe image data, and generated subframe image data. Are processed so that the sub-frame image displayed by the sub-frame image data is displayed by being shifted by one sub-pixel, and the timing signal generation module 34 having a function of generating a timing control signal. I have.

  The buffer memory 31 has a function of temporarily storing input image data. The buffer memory 31 includes a volatile memory such as a RAM (Random Access Memory), and temporarily stores input video data. The buffer memory 31 functions as a buffer unit for data output, and also functions as a work area for the subframe image generation module 32, the array conversion module 33, and the timing signal generation module.

  The subframe image generation module 32 generates subframe image data from the video data. The subframe image generation module 32 according to the present embodiment generates three subframe image data from the frame image data constituting the video data. At this time, the sub-frame image generation module 32 generates three sub-frame image data by combining the pixels for every three pixel columns in the frame image data. Since the sub-frame images displayed in the same frame period are composed of image data composed of different pixel columns, the motion of the video composed of each sub-frame image can be made smoother. The number of subframe image data generated by the subframe image generation module 32 within the frame period is not limited to this.

  FIG. 8 is an image diagram for explaining a method by which the subframe image generation module 32 generates subframe image data. In the present embodiment, the sub-frame image generation module 32 generates first to third sub-frame image data using a pixel array for every three pixel arrays with respect to the pixel arrangement of the video data. That is, the first sub-frame image data is composed of the first pixel column, the fourth pixel column,..., The third n-2 pixel column (n: the number of the pixel column in the sub-frame image data) in the original frame image data. The Similarly, the second sub-frame image data is composed of the second pixel column, the fifth pixel column,..., The 3n-1 pixel column in the original frame image data, and the third sub-frame image data is the original. The third pixel column, the sixth pixel column,..., The third n pixel column in the frame image data.

  The array conversion module 33 processes the subframe image data so that the subframe image is displayed by being shifted by one subpixel. In this embodiment, as an example of a technique for displaying a subframe image by shifting it by one subpixel, in the present embodiment, the array conversion module 33 delays the RGB color signals constituting the subframe image data for each display of the subframe image. To perform the process.

FIG. 9 is an image diagram for explaining the first and second subframe image data processed by the array conversion module. The sub-frame image data is composed of RGB color signals for driving the RGB sub-pixels, and the color signal output to the sub-pixels is output in synchronization with the output of the timing signal. Specifically, each color signal (1) constituting the first sub-frame image data supplied to the first pixel column is supplied to the first sub-pixel column in synchronization with the output of the timing signal.
Here, the array conversion module 33 delays the R color signal constituting the second subframe image data by one pixel. For this reason, the G and B color signals (1) are supplied to the G and B sub-pixels constituting the first pixel column, and the R color signal is supplied to the R sub-pixel constituting the second pixel column. (1) is supplied. As a result, one pixel is constituted by the G and B subpixels of the first pixel column and the R subpixel of the second pixel column, so that the second subframe image is changed to the first subframe image. On the other hand, the display is shifted by one subpixel. For the third subframe image, the R and G color signals are delayed by the same method.

  FIG. 10 is a flowchart for explaining a flow of generating subframe image data according to the present invention. Hereinafter, a flow in which the display timing control circuit 30 generates subframe image data will be described with reference to FIG. When video data is input from the image quality adjustment circuit 22 to the input terminal of the display timing control circuit 30, the input video data is stored in the buffer memory 31 (step S110).

  The subframe image generation module 32 generates three subframe image data from the video data stored in the buffer memory 31 (step S120). The subframe image generation module 32 generates the first to third subframe image data from the frame image data by the method shown in FIG. Since three pieces of sub-frame image data are generated from one frame image data, it is only necessary to shift the image for each RGB sub-pixel, and a pseudo resolution increase can be executed by a simple method.

  The array conversion module 33 processes the subframe image data so as to shift the subframe image in the horizontal direction by one subpixel according to the display order of the subframe image (step S130). Since the first subframe image data drives the pixels of the display unit 40 with the subpixel arrangement order being RGB, the arrangement conversion module 33 does not change the arrangement of the first subframe image data. Further, the second subframe image data is driven by the array conversion module 33 in order to drive the pixels of the display unit 40 with the subpixel arrangement order set to GBR. Similarly, the array conversion module 33 processes the third subframe image data so that the third subframe image data is driven as the subpixel array order BRG.

  The processed subframe image data is output to the driver circuit 42 together with the timing control signal (step S140). The timing signal generation module 34 generates a timing control signal so as to correspond to the display timing of each processed sub-frame image data. The generated timing control signal is output to the driver circuit 42 together with the subframe image data.

  Thereafter, the driver circuit 42 performs digital / analog conversion on the input subframe image data to generate a display voltage, and outputs the display voltage based on the timing control signal to drive each pixel of the liquid crystal display panel 41. Let Therefore, the display unit 40 displays a sub-frame image that is shifted in the horizontal direction by one sub-pixel for each image displayed during one frame period, thereby improving the resolution of the display unit 40 in a pseudo manner. it can. Specifically, since the display unit 40 displays three subframe images shifted by one subpixel for each display during one frame period, the horizontal arrangement of the pixel columns is, for example, 640 pixel columns. In this case, the number of pixels in the horizontal direction is pseudo 1920 pixels.

3. Second embodiment:
In the second embodiment, the sub-frame image generation means is realized by the image quality adjustment circuit 22 instead of the display timing control circuit 30. FIG. 11 is a block diagram showing the inside of the image quality adjustment circuit. The image quality adjustment circuit 22 includes an image processing module 23 that performs image processing on the input video data, a buffer memory 31, a subframe image generation module 32, and an array conversion module 33. The configurations and operations of the buffer memory 31, the sub-frame image generation module 32, and the array conversion module 33 that are mounted in the image quality adjustment circuit 22 are the same as those in the first embodiment, and a description thereof will be omitted.

  By realizing the sub-frame image generation means by the image quality adjustment circuit 22, the buffer memory 31 for performing image processing on the video data can be diverted to generate the sub-frame image data. Therefore, the buffer memory 31 is newly added. There is no need to suppress the increase in cost.

  As described above, in the present invention, a plurality of sub-frame image data is generated from video data, and each sub-frame image displayed by this sub-frame image data is displayed while being shifted by one sub-pixel for each display. Thus, the resolution can be increased in a pseudo manner. In addition, since it is not necessary to increase the output terminals of the driver circuit 42 to each sub-pixel, the cost of the driver circuit can be suppressed. Furthermore, since it is not necessary to reduce the pixel size in accordance with the resolution, it is not necessary to reduce the aperture ratio of each sub-pixel, and the resolution can be increased without reducing the luminance of each pixel.

4). Other embodiments:
Although the display unit has been described as a configuration provided with a liquid crystal display panel, it may be a plasma panel or an organic EL panel instead of the liquid crystal display panel.
In addition to the television receiver, the video display device may be a display device that does not include a tuner unit.

Needless to say, the present invention is not limited to the above embodiments. It goes without saying for those skilled in the art,
・ Applying mutually interchangeable members and configurations disclosed in the above embodiments by appropriately changing the combination thereof.− Although not disclosed in the above embodiments, it is a publicly known technique and the above embodiments. The members and configurations that can be mutually replaced with the members and configurations disclosed in the above are appropriately replaced, and the combination is changed and applied. It is an embodiment of the present invention that a person skilled in the art can appropriately replace the members and configurations that can be assumed as substitutes for the members and configurations disclosed in the above-described embodiments, and change the combinations and apply them. It is disclosed as.

1 is a block diagram illustrating a video display device according to the present invention. It is an image figure for demonstrating a mode that a sub-frame image is produced | generated from video data. It is an image figure for demonstrating the relationship of the display period of a frame image and a sub-frame image. It is an image figure for demonstrating the sub-frame image which concerns on this invention. It is an image figure for demonstrating the position of the light emission center in each sub-frame image. FIG. 5 is a block diagram illustrating the configuration of the television receiver. 2 is a block diagram illustrating the inside of a display timing control circuit 30. FIG. It is an image figure explaining the method in which the sub-frame image generation module 32 produces | generates sub-frame image data. It is an image figure for demonstrating the 1st and 2nd sub-frame image data which an arrangement | sequence conversion module processes. It is a flowchart for demonstrating the flow by which the sub-frame image data based on this invention are produced | generated. It is a block diagram which shows the inside of an image quality adjustment circuit. It is a schematic diagram explaining the arrangement | sequence of the conventional pixel and subpixel.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Tuner part, 12 ... AD conversion circuit, 13 ... Input selection circuit, 21 ... Display size conversion circuit, 22 ... Image quality adjustment circuit, 23 ... Image processing module, 30 ... Display timing control circuit, 31 ... Buffer memory, 32 ... Sub-frame image generation module, 33 ... array conversion module, 34 ... timing signal generation module, 40 ... display unit, 41 ... liquid crystal display panel, 42 ... driver circuit, 100 ... television receiver

Claims (7)

In a video display device for displaying video,
Video data acquisition means for acquiring video data;
Sub-frame for displaying a plurality of sub-frame images generated from the acquired video data, wherein each sub-frame image is displayed by being shifted in the horizontal direction by a predetermined sub-pixel for each display. Subframe image generation means for generating image data;
An image display apparatus comprising a screen in which one pixel is configured by an array of RGB sub-pixels, and display means for displaying an image based on the image data or the subframe image data.   The sub-frame image generation means generates the sub-frame image data for displaying the sub-frame image by shifting the sub-frame image in the horizontal direction by one sub-pixel for each display order. The video display device according to claim 1.   3. The sub-frame image generation unit generates three pieces of sub-frame image data from one frame image data constituting video data. 4. Video display device.   The said sub-frame image production | generation means produces | generates several sub-frame image data using the pixel row | line for every predetermined pixel in the said video data, The Claim 1 characterized by the above-mentioned. Video display device.   5. The video display device according to claim 1, wherein the sub-frame image generating unit is a timing controller for controlling a display timing of the display unit.   5. The video display device according to claim 1, wherein the sub-frame image generation unit is an image quality adjustment circuit for performing image processing on the acquired video data. 6. . The sub-frame image generation means is a timing controller for controlling the display means,
From one frame image data constituting the video data, three subframe image data is generated using a pixel row for every three pixels in the frame image data, and the subframe image is displayed for each display order of the subframe images. 2. The video display device according to claim 1, wherein the sub-frame image data for displaying the frame image shifted in the horizontal direction by one sub-pixel is generated.

Images