JP2009543125A - アクティブ・マトリックス・ディスプレイを補償する装置 - Google Patents
アクティブ・マトリックス・ディスプレイを補償する装置 Download PDFInfo
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- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
Description
a)画素駆動回路が、データ線と、電力供給線と、ソース電極とドレイン電極とゲート電極を有する駆動用トランジスタと、ソース電極とドレイン電極とゲート電極を有するスイッチング用トランジスタとを備えており;
b)駆動用トランジスタのソース電極とドレイン電極の一方は、対応する電力供給線に電気的に接続され、そのソース電極とドレイン電極の他方は、対応するOLED発光画素に電気的に接続され;
c)スイッチング用トランジスタのソース電極とドレイン電極の一方は、対応する駆動用トランジスタのゲート電極に電気的に接続され、そのソース電極とドレイン電極の他方は、対応するデータ線に電気的に接続されており;
d)正または負の第1の電圧を電力供給線に印加して駆動用トランジスタに第1の方向の電流を流すことでOLED発光画素が信号電圧に応答して光を出すようにする第1の手段と;
e)第1の電圧とは極性が逆の第2の電圧を電力供給線に印加し、駆動用トランジスタに第1の方向とは逆の第2の方向の電流を、その駆動用トランジスタのゲート電極の電位によってその駆動用トランジスタがオフになるまで流す第2の手段と;
f)データ線上に、駆動用トランジスタのゲート電極上の電位の関数である閾値電圧関連信号を生成させる第3の手段と;
g)その閾値電圧関連信号に応答して信号電圧に対する調節値を計算する第4の手段を備える装置によって達成される。
Vgp/Vgo = Cgo/Cgp (式1)
Vgate = PVDD2 + Vth (式2)
Vout = f(Vゲート) (式3)
Vth = f-1(Vout) - PVDD2 (式4)
Vゲート= PVDD3 - Vth Cgp/Cgo (式5)
ここに、PVDD3は、電力供給線110に印加される第3の電圧(例えばこの例ではゼロ)を表わす。この場合、閾値電圧は、測定された電圧から以下のように計算できる。
Vth = -Cgo (f-1(Vout) - PVDD3)/Cgp (式6)
調節値 = Vth - Vthi (式7)
である。ここにVthiは、トランジスタの初期閾値電圧を表わす。
105 画素駆動回路
110 電力供給線
120 データ線
130 選択線
140 OLED発光画素
145 ドレイン電極
150 グラウンド
155 ソース電極
160 OLED発光画素
165 ゲート電極
170 駆動用トランジスタ
180 スイッチング用トランジスタ
185 ソース電極またはドレイン電極
190 キャパシタ
195 ゲート電極
200 画素駆動回路
210 駆動用トランジスタ
215 ゲート電極
220 キャパシタ
230 キャパシタ
250 OLEDディスプレイ
260 電圧源
265 スイッチ
270 電圧源
280 ディジタル/アナログ変換器
285 スイッチ
290 相関二重サンプリング回路
310 積分器
315 プロセッサ
320 低域フィルタ
325 メモリ
330 相関二重サンプリング・ユニット
340 サンプリング・保持素子
350 アナログ/ディジタル変換器
410 ブロック
420 ブロック
430 ブロック
440 ブロック
450 ブロック
460 ブロック
470 ブロック
480 ブロック
485 判断ブロック
490 ブロック
Claims (8)
- 少なくとも1つのOLED発光画素を有するアクティブ・マトリックスOLEDディスプレイに含まれる1つの画素駆動回路の駆動用トランジスタの閾値電圧(Vth)の変化を補償するために信号電圧に対する調節値を決定する装置であって、
a)上記画素駆動回路が、データ線と、電力供給線と、ソース電極とドレイン電極とゲート電極を有する駆動用トランジスタと、ソース電極とドレイン電極とゲート電極を有するスイッチング用トランジスタとを備えており;
b)上記駆動用トランジスタのソース電極とドレイン電極の一方は、対応する電力供給線に電気的に接続され、そのソース電極とドレイン電極の他方は、対応するOLED発光画素に電気的に接続され;
c)上記スイッチング用トランジスタのソース電極とドレイン電極の一方は、対応する駆動用トランジスタのゲート電極に電気的に接続され、そのソース電極とドレイン電極の他方は、対応するデータ線に電気的に接続されており;
d)正または負の第1の電圧を電力供給線に印加して上記駆動用トランジスタに第1の方向の電流を流すことで上記OLED発光画素が信号電圧に応答して光を出すようにする第1の手段と;
e)第1の電圧とは極性が逆の第2の電圧を上記電力供給線に印加し、上記駆動用トランジスタに第1の方向とは逆の第2の方向の電流を、その駆動用トランジスタのゲート電極の電位によってその駆動用トランジスタがオフになるまで流す第2の手段と;
f)上記データ線上に、上記駆動用トランジスタのゲート電極上の電位の関数である閾値電圧関連信号を生成させる第3の手段と;
g)その閾値電圧関連信号に応答して信号電圧に対する調節値を計算する第4の手段を備える装置。 - 上記OLED発光画素が非反転OLED画素であり、第1の電圧がグラウンド値に対して正である、請求項1に記載の装置。
- 上記OLED発光画素が反転OLED画素であり、第1の電圧がグラウンド値に対して負である、請求項1に記載の装置。
- 上記駆動用トランジスタと上記スイッチング用トランジスタがn型トランジスタである、請求項1に記載の装置。
- 上記駆動用トランジスタと上記スイッチング用トランジスタがp型トランジスタである、請求項1に記載の装置。
- 上記第4の手段が、相関二重サンプリング回路を備える、請求項1に記載の装置。
- 上記第4の手段が、アナログ/ディジタル変換器と、閾値電圧を計算する計算回路を備える、請求項1に記載の装置。
- 上記第4の手段がさらに、信号電圧に対する調節値を、上記画素駆動回路のスイッチング用トランジスタを通じ、動作中のその画素駆動回路の駆動用トランジスタのゲート電極に印加する、請求項1に記載の装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/427,104 US7636074B2 (en) | 2006-06-28 | 2006-06-28 | Active matrix display compensating apparatus |
US11/427,104 | 2006-06-28 | ||
PCT/US2007/014323 WO2008002422A2 (en) | 2006-06-28 | 2007-06-20 | Active matrix display compensating apparatus |
Publications (2)
Publication Number | Publication Date |
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JP2009543125A true JP2009543125A (ja) | 2009-12-03 |
JP5313888B2 JP5313888B2 (ja) | 2013-10-09 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2009518158A Active JP5313888B2 (ja) | 2006-06-28 | 2007-06-20 | アクティブ・マトリックス・ディスプレイを補償する装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7636074B2 (ja) |
EP (1) | EP2033178B1 (ja) |
JP (1) | JP5313888B2 (ja) |
WO (1) | WO2008002422A2 (ja) |
Cited By (1)
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KR101851577B1 (ko) * | 2012-09-17 | 2018-04-24 | 삼성전자주식회사 | 유기 발광 다이오드 디스플레이의 동작을 제어할 수 있는 방법들과 장치들 |
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CN104751777B (zh) * | 2013-12-31 | 2017-10-17 | 昆山工研院新型平板显示技术中心有限公司 | 像素电路、像素及包括该像素的amoled显示装置及其驱动方法 |
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EP2033178B1 (en) | 2011-08-17 |
US7636074B2 (en) | 2009-12-22 |
EP2033178A2 (en) | 2009-03-11 |
WO2008002422A2 (en) | 2008-01-03 |
JP5313888B2 (ja) | 2013-10-09 |
US20080001854A1 (en) | 2008-01-03 |
WO2008002422A3 (en) | 2008-03-13 |
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