JP2009540681A - データ通信フロー制御の装置および方法 - Google Patents

データ通信フロー制御の装置および方法 Download PDF

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Publication number
JP2009540681A
JP2009540681A JP2009514434A JP2009514434A JP2009540681A JP 2009540681 A JP2009540681 A JP 2009540681A JP 2009514434 A JP2009514434 A JP 2009514434A JP 2009514434 A JP2009514434 A JP 2009514434A JP 2009540681 A JP2009540681 A JP 2009540681A
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Japan
Prior art keywords
buffer
data
value
integrated circuit
buffer descriptor
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Pending
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JP2009514434A
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English (en)
Japanese (ja)
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JP2009540681A5 (enExample
Inventor
イー． イニス、ジェームズ
アハメド、イフテカー
ジョセフ テイラー、マシュー
ダブリュ． トッド、デイビット
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NXP USA Inc
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NXP USA Inc
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Publication of JP2009540681A publication Critical patent/JP2009540681A/ja
Publication of JP2009540681A5 publication Critical patent/JP2009540681A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/126—Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
JP2009514434A 2006-06-05 2007-04-05 データ通信フロー制御の装置および方法 Pending JP2009540681A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/446,891 US7457892B2 (en) 2006-06-05 2006-06-05 Data communication flow control device and methods thereof
PCT/US2007/066013 WO2007146479A2 (en) 2006-06-05 2007-04-05 Data communication flow control device and methods thereof

Publications (2)

Publication Number Publication Date
JP2009540681A true JP2009540681A (ja) 2009-11-19
JP2009540681A5 JP2009540681A5 (enExample) 2010-05-20

Family

ID=38832592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009514434A Pending JP2009540681A (ja) 2006-06-05 2007-04-05 データ通信フロー制御の装置および方法

Country Status (5)

Country Link
US (1) US7457892B2 (enExample)
EP (1) EP2030096B1 (enExample)
JP (1) JP2009540681A (enExample)
CN (1) CN101460912B (enExample)
WO (1) WO2007146479A2 (enExample)

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US9367495B1 (en) * 2008-09-30 2016-06-14 Lattice Semiconductor Corporation High speed integrated circuit interface
US8412866B2 (en) * 2008-11-24 2013-04-02 Via Technologies, Inc. System and method of dynamically switching queue threshold
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US8190794B2 (en) * 2009-10-21 2012-05-29 Texas Instruments Incorporated Control function for memory based buffers
US9037810B2 (en) * 2010-03-02 2015-05-19 Marvell Israel (M.I.S.L.) Ltd. Pre-fetching of data packets
US20110228674A1 (en) * 2010-03-18 2011-09-22 Alon Pais Packet processing optimization
US9069489B1 (en) 2010-03-29 2015-06-30 Marvell Israel (M.I.S.L) Ltd. Dynamic random access memory front end
US8327047B2 (en) * 2010-03-18 2012-12-04 Marvell World Trade Ltd. Buffer manager and methods for managing memory
US9098203B1 (en) 2011-03-01 2015-08-04 Marvell Israel (M.I.S.L) Ltd. Multi-input memory command prioritization
CN102209042B (zh) * 2011-07-21 2014-04-16 迈普通信技术股份有限公司 一种避免先入先出队列溢出的方法及设备
JP5734788B2 (ja) * 2011-08-19 2015-06-17 株式会社東芝 通信装置及びプログラム
US10229072B2 (en) * 2014-03-19 2019-03-12 Avago Technologies International Sales Pte. Limited System and method for despreader memory management
US10210089B2 (en) 2015-06-18 2019-02-19 Nxp Usa, Inc. Shared buffer management for variable length encoded data
US11284301B2 (en) * 2017-04-17 2022-03-22 Qualcomm Incorporated Flow control for wireless devices
JP6992295B2 (ja) * 2017-07-11 2022-01-13 富士フイルムビジネスイノベーション株式会社 電子装置
CN110221911B (zh) * 2018-03-02 2021-09-28 大唐移动通信设备有限公司 一种以太网数据保护方法和装置
EP3857386B1 (en) * 2018-09-27 2023-07-12 INTEL Corporation Data stored or free space based fifo buffer
JP7131357B2 (ja) * 2018-12-12 2022-09-06 富士通株式会社 通信装置、通信方法、および通信プログラム
US11888753B2 (en) * 2021-08-10 2024-01-30 Mellanox Technologies, Ltd. Ethernet pause aggregation for a relay device
CN115361345B (zh) * 2022-10-24 2023-01-24 北京智芯微电子科技有限公司 一种基于单总线信息传输的数据流控方法、装置及通信系统
CN116132532A (zh) * 2023-02-13 2023-05-16 苏州盛科通信股份有限公司 一种报文处理方法、装置及电子设备
CN116208574B (zh) * 2023-03-13 2025-09-30 苏州盛科通信股份有限公司 报文处理方法、装置、电子设备及计算机可读存储介质

Citations (10)

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JPH06276194A (ja) * 1993-03-18 1994-09-30 Hitachi Ltd ブリッジ装置および記憶手段管理方法
JPH0787133A (ja) * 1993-09-16 1995-03-31 Hitachi Ltd データ通信ノードのバッファ制御方法
JPH10276224A (ja) * 1997-03-28 1998-10-13 Hitachi Cable Ltd スイッチングハブ
JP2000259551A (ja) * 1999-03-10 2000-09-22 Nec Corp バス制御装置ならびに同装置を持つ情報処理システム
JP2001094613A (ja) * 1999-09-21 2001-04-06 Canon Inc 通信制御装置、方法および記録媒体
JP2001203705A (ja) * 2000-01-19 2001-07-27 Nec Corp フロー制御回路及びフロー制御方法並びにフロー制御プログラムを記録した記憶媒体
JP2003152761A (ja) * 2001-11-14 2003-05-23 Nec Miyagi Ltd Ｌａｎ中継装置及びそれに用いる適応型フロー制御方法並びにそのプログラム
JP2003169072A (ja) * 2001-11-30 2003-06-13 Ando Electric Co Ltd 伝送速度変換方法およびインタフェース変換装置
JP2003258828A (ja) * 2002-02-28 2003-09-12 Ando Electric Co Ltd 回線接続装置及び当該装置の輻輳状態監視方法
US7089380B1 (en) * 2003-05-07 2006-08-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system to compute a status for a circular queue within a memory device

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US6084856A (en) * 1997-12-18 2000-07-04 Advanced Micro Devices, Inc. Method and apparatus for adjusting overflow buffers and flow control watermark levels
US6570850B1 (en) * 1998-04-23 2003-05-27 Giganet, Inc. System and method for regulating message flow in a digital data network
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JPH11339464A (ja) * 1998-05-28 1999-12-10 Sony Corp Ｆｉｆｏ記憶回路
US6252849B1 (en) * 1998-06-30 2001-06-26 Sun Microsystems, Inc. Flow control using output port buffer allocation
US6405258B1 (en) * 1999-05-05 2002-06-11 Advanced Micro Devices Inc. Method and apparatus for controlling the flow of data frames through a network switch on a port-by-port basis
US7065582B1 (en) * 1999-12-21 2006-06-20 Advanced Micro Devices, Inc. Automatic generation of flow control frames
US7155542B2 (en) * 2001-06-27 2006-12-26 Intel Corporation Dynamic network interface with zero-copy frames
US6779084B2 (en) * 2002-01-23 2004-08-17 Intel Corporation Enqueue operations for multi-buffer packets
US6851008B2 (en) * 2002-03-06 2005-02-01 Broadcom Corporation Adaptive flow control method and apparatus
US6892285B1 (en) * 2002-04-30 2005-05-10 Cisco Technology, Inc. System and method for operating a packet buffer
US7564785B2 (en) * 2004-05-21 2009-07-21 Intel Corporation Dynamic flow control support

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06276194A (ja) * 1993-03-18 1994-09-30 Hitachi Ltd ブリッジ装置および記憶手段管理方法
JPH0787133A (ja) * 1993-09-16 1995-03-31 Hitachi Ltd データ通信ノードのバッファ制御方法
JPH10276224A (ja) * 1997-03-28 1998-10-13 Hitachi Cable Ltd スイッチングハブ
JP2000259551A (ja) * 1999-03-10 2000-09-22 Nec Corp バス制御装置ならびに同装置を持つ情報処理システム
JP2001094613A (ja) * 1999-09-21 2001-04-06 Canon Inc 通信制御装置、方法および記録媒体
JP2001203705A (ja) * 2000-01-19 2001-07-27 Nec Corp フロー制御回路及びフロー制御方法並びにフロー制御プログラムを記録した記憶媒体
JP2003152761A (ja) * 2001-11-14 2003-05-23 Nec Miyagi Ltd Ｌａｎ中継装置及びそれに用いる適応型フロー制御方法並びにそのプログラム
JP2003169072A (ja) * 2001-11-30 2003-06-13 Ando Electric Co Ltd 伝送速度変換方法およびインタフェース変換装置
JP2003258828A (ja) * 2002-02-28 2003-09-12 Ando Electric Co Ltd 回線接続装置及び当該装置の輻輳状態監視方法
US7089380B1 (en) * 2003-05-07 2006-08-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system to compute a status for a circular queue within a memory device

Also Published As

Publication number Publication date
EP2030096A2 (en) 2009-03-04
EP2030096A4 (en) 2011-07-20
US20080005405A1 (en) 2008-01-03
CN101460912A (zh) 2009-06-17
WO2007146479A3 (en) 2008-01-17
CN101460912B (zh) 2012-09-05
EP2030096B1 (en) 2012-11-07
US7457892B2 (en) 2008-11-25
WO2007146479A2 (en) 2007-12-21

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