JP2009540409A - Temperature compensated current generator for 1V-10V interface - Google Patents

Temperature compensated current generator for 1V-10V interface Download PDF

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JP2009540409A
JP2009540409A JP2009513661A JP2009513661A JP2009540409A JP 2009540409 A JP2009540409 A JP 2009540409A JP 2009513661 A JP2009513661 A JP 2009513661A JP 2009513661 A JP2009513661 A JP 2009513661A JP 2009540409 A JP2009540409 A JP 2009540409A
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フェロ アルベルト
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G05F3/222Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/225Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage producing a current or voltage as a predetermined function of the temperature

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Abstract

本発明は、ベース‐エミッタ接合領域を備えた少なくとも1つのトランジスタおよび当該のトランジスタに結合された抵抗回路網が設けられており、温度ドリフトに曝される前記ベース‐エミッタ接合領域での電圧降下と前記抵抗回路網の抵抗値とに基づいて出力電流の電流強度が定められる、入力電圧から出力電流を形成する装置に関する。本発明によれば、前記抵抗回路網はその抵抗値が温度にともなって変化する少なくとも1つの抵抗素子を含んでおり、前記出力電流の前記電流強度は前記ベース‐エミッタ接合領域での前記電圧降下の温度ドリフトから独立に一定に保持される。  The present invention includes at least one transistor having a base-emitter junction region and a resistor network coupled to the transistor, the voltage drop at the base-emitter junction region subject to temperature drift, and The present invention relates to an apparatus for forming an output current from an input voltage, wherein a current intensity of an output current is determined based on a resistance value of the resistance network. According to the present invention, the resistor network includes at least one resistance element whose resistance value varies with temperature, and the current intensity of the output current is the voltage drop in the base-emitter junction region. Is kept constant independently of temperature drift.

Description

本発明は通常1V〜10Vインタフェースと称されるインタフェースでの温度補償技術に関する。   The present invention relates to a temperature compensation technique at an interface commonly referred to as a 1V-10V interface.

関連技術の説明
こんにち1V〜10Vインタフェースは種々の産業分野において電子デバイスを制御するデファクトスタンダードとなっている。光デバイスの分野では、1V〜10Vインタフェースは例えば単純なポテンショメータまたは外部の電子制御回路を介した光源強度の調光に用いられる。一般に、光デバイスはインタフェースの電圧によって制御される。
Description of Related Art Today, the 1V-10V interface has become the de facto standard for controlling electronic devices in various industrial fields. In the field of optical devices, the 1V to 10V interface is used for dimming light source intensity via, for example, a simple potentiometer or external electronic control circuit. In general, an optical device is controlled by an interface voltage.

外部の抵抗、例えばポテンショメータの抵抗の値に比例する電圧を得る最良の手段は、インタフェース内に電流発生器を設けることである。このようにすれば、インタフェースでの電圧がオームの法則によって抵抗値に応じて定められる。単純で安価な電流発生器はトランジスタから成り、電流値は基準となるトランジスタの接合領域電圧によって定められる。ただし当該の基準電圧は温度によって大きく変動する。たいていの場合、負の影響を有する当該の温度依存性を補償しなければならない。   The best way to obtain a voltage proportional to the value of the external resistance, for example the resistance of the potentiometer, is to provide a current generator in the interface. In this way, the voltage at the interface is determined according to the resistance value according to Ohm's law. A simple and inexpensive current generator consists of a transistor whose current value is determined by the junction region voltage of the reference transistor. However, the reference voltage varies greatly with temperature. In most cases, the temperature dependence with negative effects must be compensated.

本発明の概要
本発明の課題は、前述した問題を解決する効果的な手段を提供することである。
SUMMARY OF THE INVENTION The object of the present invention is to provide an effective means for solving the above-mentioned problems.

この課題は、本発明により、請求項1の特徴を有する装置により解決される。本発明の有利な実施形態は従属請求項に記載されている。また本発明の特徴は明細書、特許請求の範囲および図面の全てから得られ、単独でも任意に組み合わせても本発明の対象となりうる。   This object is achieved according to the invention by a device having the features of claim 1. Advantageous embodiments of the invention are described in the dependent claims. The features of the present invention can be obtained from the entire specification, claims, and drawings, and can be the subject of the present invention alone or in any combination.

図面の簡単な説明
以下に本発明を実施例に則して詳細に説明する。図1には本発明の装置の第1の実施例のブロック図が示されている。図2には本発明の装置の第2の実施例のブロック図が示されている。
BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be described in detail below with reference to examples. FIG. 1 shows a block diagram of a first embodiment of the device according to the invention. FIG. 2 shows a block diagram of a second embodiment of the device according to the invention.

本発明の実施例の詳細な説明
図1,図2には本発明の電流発生器の第1の実施例および第2の実施例が示されている。
DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION FIGS. 1 and 2 show a first embodiment and a second embodiment of the current generator of the present invention.

本発明の装置では、入力電圧としての第1の実施例のDC電圧V1またはDC電圧V2から温度に対して安定な出力電流を形成し、出力端子10で利用できるようにすることを重要な目的としている。ここで、本発明の装置は外部の可変抵抗に接続されて用いられる温度安定型の電流発生器であり、ここで設定された可変の抵抗値に比例する電圧が得られる。外部の可変抵抗は例えば図示されていないポテンショメータである。当該の電圧の調整により、1V〜10Vインタフェースにおいても1V〜10Vの範囲を超える電圧を形成することができる。   In the apparatus of the present invention, it is important to form a stable output current with respect to temperature from the DC voltage V1 or the DC voltage V2 of the first embodiment as an input voltage so that it can be used at the output terminal 10. It is said. Here, the device of the present invention is a temperature-stable current generator used by being connected to an external variable resistor, and a voltage proportional to the variable resistance value set here is obtained. The external variable resistor is, for example, a potentiometer (not shown). By adjusting the voltage, a voltage exceeding the range of 1V to 10V can be formed even in the 1V to 10V interface.

2つの実施例の双方において、本発明の装置はバイポーラpnpの第1のトランジスタQ1;Q2を有しており、これらのトランジスタのコレクタを介して接続された出力端子10の一方の端子へ出力電流が送出される。出力端子10の他方の端子はグラウンドGへ接続されている。   In both embodiments, the device of the present invention comprises a bipolar pnp first transistor Q1; Q2, and the output current to one terminal of the output terminal 10 connected via the collector of these transistors. Is sent out. The other terminal of the output terminal 10 is connected to the ground G.

図1では、トランジスタQ1のベースが抵抗回路網を介して入力電圧V1へ接続されており、当該の抵抗回路網の全抵抗は単一の抵抗値Req1として示されている。 In FIG. 1, the base of the transistor Q1 is connected to the input voltage V1 via a resistor network, and the total resistance of the resistor network is shown as a single resistance value R eq1 .

当該の抵抗回路網は、実際には、第1の抵抗R1、第1のNTC抵抗(負の温度係数を有する抵抗)NTC1、ならびに、第2の抵抗R2および第2のNTC抵抗NTC2の並列部を直列に接続した回路から成る。   The resistor network actually includes a first resistor R1, a first NTC resistor (a resistor having a negative temperature coefficient) NTC1, and a parallel portion of the second resistor R2 and the second NTC resistor NTC2. It consists of a circuit connected in series.

また、第1のトランジスタQ1のベースは抵抗R4を介してグラウンドGへ接続されている。   The base of the first transistor Q1 is connected to the ground G through a resistor R4.

図2の装置はバイポーラpnpの第2のトランジスタQ3を有しており、第1のトランジスタQ2のエミッタおよび第2のトランジスタQ3のベースは抵抗回路網を介して入力電圧V2へ接続されており、当該の抵抗回路網の全抵抗は単一の抵抗値Req2として示されている。 The device of FIG. 2 has a bipolar pnp second transistor Q3, the emitter of the first transistor Q2 and the base of the second transistor Q3 being connected to the input voltage V2 via a resistor network, The total resistance of the resistor network is shown as a single resistance value R eq2 .

当該の抵抗回路網は、実際には、第1の抵抗R5、第1のNTC抵抗NTC3、ならびに、第2の抵抗R6および第2のNTC抵抗NTC4の並列部を直列に接続した回路から成る。   The resistor network actually includes a circuit in which a first resistor R5, a first NTC resistor NTC3, and a parallel portion of a second resistor R6 and a second NTC resistor NTC4 are connected in series.

図示されているように、第1のトランジスタQ2のエミッタは第2のトランジスタQ3のベースに接続されており、第2のトランジスタQ3のコレクタは第1のトランジスタQ2のベースに接続されている。第2のトランジスタQ3のエミッタは入力電圧V2に接続されており、第1のトランジスタQ2のベースおよびこれに接続された第2のトランジスタQ3のコレクタは抵抗R7を介してグラウンドGに接続されている。   As shown, the emitter of the first transistor Q2 is connected to the base of the second transistor Q3, and the collector of the second transistor Q3 is connected to the base of the first transistor Q2. The emitter of the second transistor Q3 is connected to the input voltage V2, and the base of the first transistor Q2 and the collector of the second transistor Q3 connected thereto are connected to the ground G through the resistor R7. .

わかりやすくするために、2つの実施例では第1のトランジスタQ1;Q2のベース電流および第2のトランジスタQ3のベース電流を無視できるものとしている。   For the sake of clarity, the two embodiments assume that the base current of the first transistor Q1; Q2 and the base current of the second transistor Q3 are negligible.

図1の装置に戻って、第1のトランジスタQ1のベース電流を無視できるとすると、抵抗R4を介した電圧は、抵抗R4,Req1の接続部の電流に抵抗R4の抵抗値を乗算した値と等しくなる。この電流は、給電電圧V1を抵抗R4,Req1の和で除算した値に等しい。言い換えると、第1のトランジスタQ1のベース電圧は入力電圧V1を分圧器R4,Req1によって分圧した値によって表すことができる。 Returning to the apparatus of FIG. 1, assuming that the base current of the first transistor Q1 can be ignored, the voltage through the resistor R4 is obtained by multiplying the current at the connection of the resistors R4 and Req1 by the resistance value of the resistor R4. Is equal to This current is equal to the value obtained by dividing the power supply voltage V1 by the sum of the resistors R4 and Req1 . In other words, the base voltage of the first transistor Q1 can be expressed by a value obtained by dividing the input voltage V1 by the voltage dividers R4 and Req1 .

抵抗R3を介した電圧は、給電電圧V1から第1のトランジスタQ1のベース‐エミッタ接合領域の電圧および抵抗R4を介した電圧を差し引いたものに等しい。第1のトランジスタQ1のコレクタからの出力電流は抵抗R3を介した電圧を抵抗R3の抵抗値で除算した値に等しく、つまり、第1のトランジスタQ1のベース‐エミッタ接合領域の電圧降下および抵抗Req1の抵抗値の関数によって表される。 The voltage through the resistor R3 is equal to the power supply voltage V1 minus the voltage at the base-emitter junction region of the first transistor Q1 and the voltage through the resistor R4. The output current from the collector of the first transistor Q1 is equal to the voltage across the resistor R3 divided by the resistance value of the resistor R3, that is, the voltage drop in the base-emitter junction region of the first transistor Q1 and the resistance R It is represented by a function of the resistance value of eq1 .

温度が上昇すると、第1のトランジスタQ1のベース‐エミッタ接合領域での電圧は低下し、インタフェース電流は増大する。同時に、温度上昇により2つのNTC抵抗(NTC1,NTC2)の抵抗値が低下し、その結果、抵抗回路網Req1の抵抗が低下して、抵抗R4を介した電圧、すなわち第1のトランジスタQ1のベース電圧が増大する。これにより第1のトランジスタQ1のエミッタ電圧は一定に保持される。よって抵抗R3を介した電圧、ひいては、第1のトランジスタQ1のコレクタからの出力電流が一定に保持される。 As the temperature increases, the voltage at the base-emitter junction region of the first transistor Q1 decreases and the interface current increases. At the same time, the resistance value of the two NTC resistors (NTC1, NTC2) decreases due to the temperature rise, and as a result, the resistance of the resistor network Req1 decreases, and the voltage across the resistor R4, that is, the first transistor Q1 The base voltage increases. As a result, the emitter voltage of the first transistor Q1 is kept constant. Therefore, the voltage via the resistor R3, and hence the output current from the collector of the first transistor Q1, is held constant.

この効果は唯一のNTC、特にNTC1を用いるのみで達成可能である。ただし、2つの固定値抵抗R1,R2と対応する2つのNTC抵抗NTC1,NTC2とを用いて、抵抗回路網Req1を形成する全ての素子の抵抗値およびNTC温度係数を適切に選択することにより、温度ドリフトの補償効果をいっそう向上させることができる。なお固定値抵抗R2はNTC抵抗NTC2に接続されている。 This effect can be achieved by using only one NTC, especially NTC1. However, by using the two fixed value resistors R1 and R2 and the corresponding two NTC resistors NTC1 and NTC2, by appropriately selecting the resistance values and NTC temperature coefficients of all elements forming the resistor network R eq1 Thus, the compensation effect of temperature drift can be further improved. The fixed value resistor R2 is connected to the NTC resistor NTC2.

図2の実施例では、第1のトランジスタQ2および第2のトランジスタQ3のベース電流を無視できるものとして、第1のトランジスタQ2のコレクタからの出力電流は同じ第1のトランジスタQ2がエミッタを介して抵抗回路網Req2から受け取る電流に等しい。当該の電流は第2のトランジスタQ3のベース‐エミッタ接合領域の電圧を抵抗回路網Req2の抵抗値で除算した値にほぼ等しい。つまり、第1のトランジスタQ2のコレクタからの出力電流は、第2のトランジスタQ3のベース‐エミッタ接合領域での電圧降下と抵抗回路網Req2の抵抗値との関数である。抵抗R7を介した電流はバイポーラの第1のトランジスタQ2および第2のトランジスタQ3を分極化するのに必要な電流である。 In the embodiment of FIG. 2, it is assumed that the base currents of the first transistor Q2 and the second transistor Q3 are negligible, and the output current from the collector of the first transistor Q2 is the same through the emitter of the first transistor Q2. Equal to the current received from the resistor network R eq2 . The current is approximately equal to the value obtained by dividing the voltage at the base-emitter junction region of the second transistor Q3 by the resistance value of the resistor network Req2 . That is, the output current from the collector of the first transistor Q2 is a function of the voltage drop at the base-emitter junction region of the second transistor Q3 and the resistance value of the resistor network R eq2 . The current through the resistor R7 is a current necessary to polarize the bipolar first transistor Q2 and the second transistor Q3.

温度が上昇すると、第2のトランジスタQ3のベース‐エミッタ接合領域での電圧降下、ひいては、抵抗回路網Req2の抵抗値が低下し、これにより出力電流は一定に保持される。 As the temperature rises, the voltage drop in the base-emitter junction region of the second transistor Q3, and hence the resistance value of the resistance network Req2 , decreases, and thereby the output current is kept constant.

この効果は唯一のNTC、例えばNTC3を用いるのみで達成可能である。ただし、2つの固定値抵抗R5,R6と対応する2つのNTC抵抗NTC3,NTC4とを用いて、抵抗回路網Req1を形成する全ての素子の抵抗値およびNTC温度係数を適切に選択することにより、温度ドリフトの補償効果をいっそう向上させることができる。なお固定値抵抗R6はNTC抵抗NTC4に接続されている。 This effect can be achieved by using only one NTC, for example NTC3. However, by using the two fixed value resistors R5 and R6 and the corresponding two NTC resistors NTC3 and NTC4, by appropriately selecting the resistance values and NTC temperature coefficients of all elements forming the resistor network Req1 Thus, the compensation effect of temperature drift can be further improved. The fixed value resistor R6 is connected to the NTC resistor NTC4.

図1の実施例に対する図2の実施例の主な利点は、出力電流が供給電圧V2によって変化しないということである。   The main advantage of the embodiment of FIG. 2 over the embodiment of FIG. 1 is that the output current does not vary with the supply voltage V2.

本発明を幾つかの実施例に則して説明したが、本発明はこれらの実施例に限定されるものではない。したがって、本発明の範囲から離れることなく、明細書、特許請求の範囲および図面に規定された本発明の種々の特徴を変更することができる。   Although the present invention has been described with reference to several embodiments, the present invention is not limited to these embodiments. Accordingly, various features of the invention may be changed which are defined in the specification, claims and drawings without departing from the scope of the invention.

本発明の装置の第1の実施例のブロック図である。1 is a block diagram of a first embodiment of an apparatus of the present invention. 本発明の装置の第2の実施例のブロック図である。FIG. 3 is a block diagram of a second embodiment of the apparatus of the present invention.

Claims (12)

ベース‐エミッタ接合領域を備えた少なくとも1つのトランジスタおよび該トランジスタに結合された抵抗回路網が設けられており、温度ドリフトに曝される前記ベース‐エミッタ接合領域での電圧降下と前記抵抗回路網の抵抗値とに基づいて出力電流の電流強度が定められる、
入力電圧から出力電流を形成する装置において、
前記抵抗回路網はその抵抗値が温度にともなって変化する少なくとも1つの抵抗素子を含んでおり、前記出力電流の前記電流強度は前記ベース‐エミッタ接合領域での前記電圧降下の温度ドリフトから独立に一定に保持される
ことを特徴とする入力電圧から出力電流を形成する装置。
At least one transistor having a base-emitter junction region and a resistor network coupled to the transistor are provided, the voltage drop in the base-emitter junction region subject to temperature drift and the resistance network The current intensity of the output current is determined based on the resistance value,
In a device that forms an output current from an input voltage,
The resistor network includes at least one resistance element whose resistance value varies with temperature, and the current intensity of the output current is independent of a temperature drift of the voltage drop in the base-emitter junction region. A device for generating an output current from an input voltage, characterized by being held constant.
前記抵抗回路網はその抵抗値が温度にともなって変化する少なくとも1つの第1の抵抗素子および少なくとも1つの第2の抵抗素子を含む、請求項1記載の装置。   The apparatus of claim 1, wherein the resistive network includes at least one first resistive element and at least one second resistive element, the resistance value of which varies with temperature. 前記少なくとも1つの第1の抵抗素子および前記少なくとも1つの第2の抵抗素子はそれぞれ固定値抵抗に対応する、請求項2記載の装置。   The apparatus of claim 2, wherein the at least one first resistive element and the at least one second resistive element each correspond to a fixed value resistor. 前記少なくとも1つの第1の抵抗素子は直列に接続された固定値抵抗に対応する、請求項3記載の装置。   4. The apparatus of claim 3, wherein the at least one first resistive element corresponds to a fixed value resistor connected in series. 前記少なくとも1つの第2の抵抗素子は並列に接続された固定値抵抗に対応する、請求項3または4記載の装置。   The device according to claim 3 or 4, wherein the at least one second resistive element corresponds to a fixed value resistor connected in parallel. 前記少なくとも1つの第1の抵抗素子および前記少なくとも1つの第2の抵抗素子はそれぞれ負の温度係数を有する抵抗素子である、請求項1から5までのいずれか1項記載の装置。   The device according to claim 1, wherein the at least one first resistance element and the at least one second resistance element are resistance elements each having a negative temperature coefficient. 前記抵抗回路網は前記少なくとも1つのトランジスタのベース電圧を設定する分圧器を含み、前記少なくとも1つの抵抗素子の抵抗変化により前記少なくとも1つのトランジスタのベース電圧が変更されて前記ベース‐エミッタ接合領域での前記電圧降下の温度ドリフトが補償される、請求項1から6までのいずれか1項記載の装置。   The resistor network includes a voltage divider that sets a base voltage of the at least one transistor, and a base voltage of the at least one transistor is changed by a resistance change of the at least one resistor element, so that the base-emitter junction region is changed. The device according to claim 1, wherein a temperature drift of the voltage drop is compensated. 前記少なくとも1つのトランジスタのエミッタは固定値抵抗を介して入力電圧へ接続されている、請求項1から7までのいずれか1項記載の装置。   The device according to claim 1, wherein the emitter of the at least one transistor is connected to an input voltage via a fixed value resistor. 前記抵抗回路網は前記少なくとも1つのトランジスタの前記ベース‐エミッタ接合領域のあいだに接続されており、前記抵抗回路網は前記ベース‐エミッタ接合領域での前記電圧降下と前記抵抗回路網の抵抗値との比によって定められる電流により調整され、前記少なくとも1つの抵抗素子の抵抗の変化により前記比が保持され、前記ベース‐エミッタ接合領域での前記電圧降下の温度ドリフトが補償される、請求項1から6までのいずれか1項記載の装置。   The resistor network is connected between the base-emitter junction region of the at least one transistor, the resistor network including the voltage drop at the base-emitter junction region and the resistance value of the resistor network. The current ratio is adjusted by a current defined by the ratio of the at least one resistive element, the ratio is maintained by a change in resistance of the at least one resistive element, and the temperature drift of the voltage drop at the base-emitter junction region is compensated. The apparatus according to any one of 6 to 6. さらに第2のトランジスタが設けられており、該第2のトランジスタに前記抵抗回路網を調整する電流が供給される、請求項9記載の装置。   10. The apparatus of claim 9, further comprising a second transistor, wherein the second transistor is supplied with a current that regulates the resistive network. 前記第2のトランジスタは、そのエミッタおよびコレクタを介して、前記抵抗回路網を調整する電流を受け取り、出力電流を出力する、請求項10記載の装置。   The apparatus of claim 10, wherein the second transistor receives, via its emitter and collector, a current that regulates the resistor network and outputs an output current. 請求項1から11までのいずれか1項記載の入力電圧から出力電流を形成する装置を1V〜10Vインタフェース用の温度補償電流発生器として用いることを特徴とする入力電圧から出力電流を形成する装置の使用。   12. An apparatus for forming an output current from an input voltage, wherein the apparatus for forming an output current from an input voltage according to any one of claims 1 to 11 is used as a temperature compensated current generator for a 1V to 10V interface. Use of.
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101783330B1 (en) * 2009-06-26 2017-09-29 더 리젠츠 오브 더 유니버시티 오브 미시건 Reference voltage generator having a two transistor design
TWI405068B (en) * 2010-04-08 2013-08-11 Princeton Technology Corp Voltage and current generator with an approximately zero temperature coefficient
CN103875120B (en) * 2011-09-30 2016-05-25 株式会社村田制作所 Battery outer structure
DE102014220753A1 (en) 2014-10-14 2016-04-14 Tridonic Gmbh & Co Kg Sensor for a control gear for bulbs
KR102662446B1 (en) * 2019-03-19 2024-04-30 삼성전기주식회사 Bias circuit and amplifying device having temperature compensation function
JP2021069080A (en) * 2019-10-28 2021-04-30 株式会社三社電機製作所 Gate drive circuit
US11636322B2 (en) * 2020-01-03 2023-04-25 Silicon Storage Technology, Inc. Precise data tuning method and apparatus for analog neural memory in an artificial neural network

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5465355A (en) * 1977-11-01 1979-05-25 Toshiba Corp Constant current circuit
JPS5617519A (en) * 1979-07-24 1981-02-19 Toshiba Corp Frequency modulator
JPS62231322A (en) * 1986-03-31 1987-10-09 Toshiba Corp Constant current circuit
JPH0266613A (en) * 1988-08-31 1990-03-06 Sharp Corp Constant current circuit
JPH0334708A (en) * 1989-06-30 1991-02-14 Nippon Dempa Kogyo Co Ltd Compensation voltage generating circuit for temperature compensation oscillator
JPH0526207B2 (en) * 1980-04-08 1993-04-15 Sony Corp
JPH0543131B2 (en) * 1986-12-19 1993-06-30 Matsushita Electric Ind Co Ltd
JPH0685563A (en) * 1992-09-04 1994-03-25 Nec Kansai Ltd Constant current circuit
JPH0784658A (en) * 1993-08-13 1995-03-31 Tektronix Inc Current source
JPH082738Y2 (en) * 1990-08-05 1996-01-29 新日本無線株式会社 Constant current circuit
JP2000124744A (en) * 1998-10-12 2000-04-28 Texas Instr Japan Ltd Constant voltage generation circuit
JP2002116831A (en) * 2000-10-05 2002-04-19 Sharp Corp Constant current generating circuit
JP2004234477A (en) * 2003-01-31 2004-08-19 Fujitsu Ltd Semiconductor device and temperature compensated oscillator

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3148337A (en) * 1962-10-01 1964-09-08 Hewlett Packard Co Temperature compensated signal-controlled current source
US3956661A (en) * 1973-11-20 1976-05-11 Tokyo Sanyo Electric Co., Ltd. D.C. power source with temperature compensation
JPS5492094A (en) * 1977-12-29 1979-07-20 Seiko Epson Corp Power supply method for liquid crystal display substance
EP0521175B1 (en) * 1991-06-28 1993-04-21 Siemens Aktiengesellschaft Circuit arrangement for temperature compensation of coil quality factor
US6023185A (en) * 1996-04-19 2000-02-08 Cherry Semiconductor Corporation Temperature compensated current reference
CN1154032C (en) * 1999-09-02 2004-06-16 深圳赛意法微电子有限公司 Band-gap reference circuit
JP4240691B2 (en) * 1999-11-01 2009-03-18 株式会社デンソー Constant current circuit
US6865150B1 (en) * 2000-04-06 2005-03-08 Cisco Technology, Inc. System and method for controlling admission of voice communications in a packet network
US6407621B1 (en) * 2000-10-11 2002-06-18 Intersil Americas Inc. Mechanism for generating precision user-programmable parameters in analog integrated circuit
US6556082B1 (en) * 2001-10-12 2003-04-29 Eic Corporation Temperature compensated current mirror
KR100654646B1 (en) * 2004-10-11 2006-12-08 아바고테크놀로지스코리아 주식회사 A temperature compensated bias circuit for a power amplifier

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5465355A (en) * 1977-11-01 1979-05-25 Toshiba Corp Constant current circuit
JPS5617519A (en) * 1979-07-24 1981-02-19 Toshiba Corp Frequency modulator
JPH0526207B2 (en) * 1980-04-08 1993-04-15 Sony Corp
JPS62231322A (en) * 1986-03-31 1987-10-09 Toshiba Corp Constant current circuit
JPH0543131B2 (en) * 1986-12-19 1993-06-30 Matsushita Electric Ind Co Ltd
JPH0266613A (en) * 1988-08-31 1990-03-06 Sharp Corp Constant current circuit
JPH0334708A (en) * 1989-06-30 1991-02-14 Nippon Dempa Kogyo Co Ltd Compensation voltage generating circuit for temperature compensation oscillator
JPH082738Y2 (en) * 1990-08-05 1996-01-29 新日本無線株式会社 Constant current circuit
JPH0685563A (en) * 1992-09-04 1994-03-25 Nec Kansai Ltd Constant current circuit
JPH0784658A (en) * 1993-08-13 1995-03-31 Tektronix Inc Current source
JP2000124744A (en) * 1998-10-12 2000-04-28 Texas Instr Japan Ltd Constant voltage generation circuit
JP2002116831A (en) * 2000-10-05 2002-04-19 Sharp Corp Constant current generating circuit
JP2004234477A (en) * 2003-01-31 2004-08-19 Fujitsu Ltd Semiconductor device and temperature compensated oscillator

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