JP5437110B2 - Automatic bias adjustment circuit for FET - Google Patents

Description

  The present invention relates to an FET automatic bias adjustment circuit, and more particularly to a configuration of an automatic bias adjustment circuit that realizes supply of a drain current having an arbitrary gradient with high linearity with respect to temperature.

  In general, the gain of a GaAs FET (field effect transistor) used in a high frequency circuit such as a microwave increases at a low temperature due to an increase in gm (transconductance). On the other hand, gm is a drain current (Id) of the FET. The larger the value, the more it tends to increase. Therefore, the drain current and the gain are often directly proportional except for special conditions such as near the pinch-off voltage (Vp) and near the drain saturation current (Idss). As a compensation to suppress, for example, a method of changing the drain current with temperature, that is, a method of controlling the drain current in a positive gradient proportional to the temperature is employed.

FIG. 7 shows a basic circuit for realizing temperature compensation. In FIG. 7 , a negative power source 3 is connected to the gate of an N-channel depletion type FET 1 via a temperature sensitive control circuit 2, and A positive power supply 4 for supplying a drain voltage is connected to the drain. The temperature sensitive control circuit 2 is provided with a temperature sensitive element such as a thermistor whose characteristics change with temperature. In such a bias adjustment circuit, a drain current having a desired temperature characteristic can be obtained by variably adjusting the gate voltage applied to the FET 1 from the negative power supply 3 via the temperature sensing control circuit 2.

FIG. 8 shows a configuration of a conventional FET automatic bias adjustment circuit. In FIG. 8 , a PNP transistor Q1 having a collector connected to the gate of FET1 and an emitter connected to the drain, and the transistor Q1 are shown. A temperature-sensitive control circuit 2 connected to the base, a resistor (unit) R ₄ for detecting drain current, and a resistor R ₅ are provided on the negative power supply side. In such a bias adjustment circuit, a change in the drain current of the FET 1 is detected by the transistor Q 1 via the resistor R _4, and an adjustment current for the transistor Q 1 to perform temperature compensation via the temperature sensing control circuit 2. Is given to the gate of the FET 1, a drain current having a desired temperature characteristic can be obtained.

Japanese Patent Laid-Open No. 10-341142

However, in the bias adjustment circuit as shown in FIG. 7 described above, the gate voltage for setting a desired drain current differs depending on the static characteristics of the element itself used. Even if it is set to, it is expected that other elements will not be in good condition and is not suitable for mass production.

On the other hand, the bias adjustment circuit of FIG. 8 has the advantage that individual differences between elements are eliminated because the gate voltage is adjusted so as to obtain a desired drain current. Since a thermistor is generally used as the temperature element, it has the following drawbacks.
That is, this thermistor
1. Since the resistance value of a single unit is proportional to the logarithm of the reciprocal of absolute temperature, the resistance value of a single unit is not linear with respect to temperature. To obtain good linearity, it is necessary to combine multiple thermistors and resistors. Yes, the circuit becomes complicated. 2. Specifications (specifications) are not finely divided like general resistors. 3. Expensive compared to resistors. Due to the above problems, there is a disadvantage that the desired characteristics cannot be easily changed.

Therefore, conventionally, a bias adjustment circuit of FIG. 9 as shown in Patent Document 1 has been proposed as one that does not use a thermistor.
The circuit of FIG. 9 eliminates the temperature-sensitive control circuit 2 of FIG. 8 , connects the first resistor R ₁ between the base of the transistor Q 1 and the ground, and connects the second resistor between the base and the positive power source 4. connect the R _2, so that achieve the adjustment of the drain current by utilizing the temperature characteristics of the transistor Q1.

That is, when the voltage applied from the positive power supply 4 to _{V 1, (V 1 - (} V 1 × (R 1 / (R 1 + R 2)) + Vbe1)) / R 4 [Vbe1: the base of the transistor Q1 - emitter during _{voltage, R 1, R 2, R} 4: to be a drain current Id is expressed by equation of each resistor value, the collector current Ic1 of the transistor Q1 is changed, the collector current Ic1 to the negative power supply 3 Since the current flows, the gate voltage Vg of the FET 1 is controlled, and an equilibrium state is reached with the drain current Id. Therefore, by utilizing the temperature characteristic of the base voltage Vb1 of the transistor Q1 and selecting the circuit specifications so that the drain current characteristic has a desired temperature characteristic, a stable operation with gain compensated for temperature can be obtained.

However, when the gain temperature variation of the FET 1 is compensated by the drain current (Id) as in the circuit of FIG. 9 , if the operating temperature range is about 120 ° C. (for example, −40 ° C. to + 80 ° C.), the high temperature the drain current for achievable with variation of 2 times the drain current at a low temperature, when the when the voltage drop at the resistor R ₄ is small resulting in a balanced condition, there is a disadvantage that the variation of the drain current is too large when . That is, in order to make the fluctuation range of the drain current and the desired level, the resistance (vessel) to increase the R _4, it is necessary to increase the voltage drop at the resistor R _4, as a result, the resistor R ₄ There is a problem that the power consumption increases and the voltage applied to the drain of the FET 1 also varies greatly with temperature.

  The present invention has been made in view of the above problems, and an object of the present invention is to achieve a desired temperature compensation with a simple circuit without using a thermistor and to prevent an increase in power consumption at a resistor. It is an object of the present invention to provide an automatic bias adjustment circuit for FET that can arbitrarily change and adjust compensation characteristics only by changing resistance specifications.

In order to achieve the above object, the invention of claim 1 is a FET automatic bias adjustment circuit for driving an FET, wherein the first transistor is connected to the gate or source of the FET and controls the gate voltage or source voltage. A drain current detecting resistor for detecting a drain current of the FET, a first resistor connected between the first transistor and the ground, and a ground-side terminal of the first transistor and a power source. A connected second resistor, a temperature sensing element comprising a diode or a transistor connected in parallel with the second resistor between a ground side terminal of the first transistor and a power source, and a ground side terminal of the first transistor any and is connected in series with the temperature sensitive device between the power source, in combination with the second resistor nonzero temperature gradient of the drain current of the FET Third resistor for setting the gradient, a provided, said temperature sensitive element, by controlling the base voltage of the first transistor based on the second resistor and the third resistor, the drain current of any temperature gradients Thus, the gain temperature compensation of the FET is performed.
The invention of claim 2, between the source and the first transistor of the upper Symbol FET, connects the second transistor for controlling the source voltage of the FET, and adjust the drain current through the second transistor, The FET is configured to be driven by a single power source.

  According to the configuration of the automatic bias adjustment circuit for FET of claim 1, the temperature of the drain current is changed by changing the combination of the values of the third resistor and the second resistor in series with the temperature sensing element of the diode or transistor. The gradient can be arbitrarily set, and thus desired temperature compensation can be realized.

According to the automatic bias adjustment circuit for FET of the present invention, along with the desired temperature compensation with a simple circuit without using a thermistor can be achieved, any temperature gradient by the combination of the third resistor value with respect to the second resistance value Therefore, the drain current detection resistor (unit) is made small, and the power consumption at the resistor is not increased.
In addition, there is an effect that it is possible to arbitrarily change or adjust the temperature compensation characteristics only by changing the specification and type (specifications) of the resistor.
Further, according to the second aspect of the present invention, even when driven by a single power source, there is an effect that desired temperature compensation can be performed without setting a bias condition corresponding to variations in individual characteristics of the FET.

1 is a circuit diagram showing a configuration of an FET automatic bias adjustment circuit according to a first embodiment of the present invention; FIG. It is a graph which shows the drain current characteristic with respect to temperature when the specification of a 1st Example circuit is changed. It is a graph which shows the linearity of the drain current with respect to temperature when the specification of a 1st Example circuit is changed. FIG. 4 is a table showing the circuit specifications of FIGS. 2 and 3. It is a circuit diagram at the time of using a single power supply configuration in the automatic bias adjustment circuit of the second embodiment. It is a circuit diagram at the time of using a transistor instead of a diode in the automatic bias adjustment circuit of the third embodiment. It is a circuit diagram which shows the basic composition for temperature compensation in the conventional FET. It is a circuit diagram which shows the structure of the automatic bias adjustment circuit for FET which performs temperature compensation conventionally. It is a circuit diagram which shows the specific structure of the automatic bias adjustment circuit for FET which performs temperature compensation conventionally.

FIG. 1 shows an FET automatic bias adjustment circuit according to a first embodiment of the present invention. The circuit of the first embodiment is used for a microwave amplifier, for example, and its basic configuration is shown in FIG. It will be the same.
In FIG. 1, a PNP first transistor Q1 having a collector connected to the gate of an N-channel (N-ch) depletion type FET1 and an emitter connected to the drain is provided. The gate of FET1 and the collector of the first transistor Q1 are provided. resistance (vessel) negative (electrode) power source 3 is connected via a R _5. Further, the drain and the emitter of the first transistor Q1 of the FET1, the positive through the resistor R ₄ for detecting the drain current of FET1 (pole) power source 4 is disposed between the base and the ground of the first transistor Q1 A first resistor R ₁ is connected in between, and a second resistor R ₂ for setting the base voltage of the first transistor Q 1 is connected between the base and the positive power source 4.

Then, in the first embodiment, the base of the first transistor Q1 (ground-side terminal) between the positive power supply 4, is a diode D1 connected in series the third resistor R _3, and parallel to the said second resistor The diode D1 functions as a temperature-sensitive element that gives a voltage variation with respect to the temperature.

The first embodiment is configured as described above, and the drain current Id of the FET 1 in this automatic bias adjustment circuit can be expressed by the following formula 1.
[Equation 1]
Id = (V ₁ − ((R ₂ · V ₁ + R ₃ · V ₁ −R ₂ · V _fD ) / (R ₁ · R ₂ + R ₁ · R ₃ + R ₂ · R ₃ ) × R ₁ + Vbe1)) / R ₄
V ₁ : voltage applied from the positive power source 4, V _fD : forward voltage of the diode D 1, Vbe 1: base-emitter voltage of the transistor Q ₁ , R ₁ , R ₂ , R ₃ , R ₄ : resistance of each resistor Value.

In the above formula 1, the drain current Id at a desired temperature can be calculated by adding the forward voltage temperature fluctuation (variation coefficient: about −2 mV / ° C.) of the PN junction to V _fD and Vbe1 at room temperature. Can be sought. However, since V _fD and Vbe1 fluctuate depending on the forward current, it is necessary to accurately take this point into consideration in the above equation, and realistic design should be optimized by simulation using the Spice model or the like. Is desirable.

Hereinafter, a simple operation of this circuit will be described.
If there is no the diode D1 and the third resistor R ₃ with the addition in the first embodiment, i.e., the circuit of Figure 10, the base of the first transistor Q1 - drain current Id of the temperature variation thus FET1 emitter voltage Vbe1 fluctuates However, the slope and magnitude of the fluctuation is that the drain current Id is a positive slope with respect to the temperature because Vbe1 is a negative slope with respect to the temperature, and the fluctuation width is the voltage drop V ₁ at V ₁ and R _{4. DE,} i.e. _{V DE = V 1 - (V} 1 × (R 1 / (R 1 + R 2)) + Vbe1) difference large as becomes smaller the a, if indicated by the equation, the voltage drop _{V DE} cold when _{R 4} Is ΔVR4, and the temperature fluctuation width of the base-emitter voltage of the first transistor Q1 is ΔVbe1, the drain current Id at a high temperature is ((ΔVbe1 / ΔVR4) +1) times.

Therefore, it is possible to realize a desired temperature fluctuation characteristic of the drain current Id using this characteristic. However, as described above, when the gain temperature fluctuation of the FET 1 is compensated by the drain current Id, the operating temperature range is used. Is about 120 ° C., the Id at high temperature can be achieved with a fluctuation of about twice the Id at low temperature. Therefore, assuming that the voltage drop at the resistor R ₄ is small, the drain current Id variation becomes too large, there is a disadvantage that the drain current Id voltage drop increase results in the resistor R ₄ the fluctuation band to a desired level, power consumption at the resistor R ₄ increases.

In the first embodiment, since the connecting diode D1 and the resistor R ₃ and a resistor R ₂ in parallel, when the resistance R ₂ is infinite, the variation of the diode voltage V _fD is the base of the first transistor Q1 - emitter voltage Vbe1 since the temperature change of the same slope of, but acts in a direction to suppress the temperature fluctuation of the drain current Id, the base voltage Vb1 resistance R ₃ from the positive supply voltages V ₁ in series of the first transistor _Q1, a diode D1 (V _fD ), since the voltage applied to the resistor R ₁ connected state by the resistor R _1, it is smaller than the temperature variation of the diode voltage V _fD. Here, considering the case where R _{4 is set} to a very small value, since R ₃ may also be a small value, the fluctuations of Vbe1 and Vb1 are almost the same, and the drain current Id is related to the temperature (change). Almost no change.

Therefore, when a diode D1 is added to the third resistor R _3, even a resistance R ₄ for the drain current detection value smaller, by the combination of the third resistor R ₃ second resistor R ₂ values, the temperature of the drain current Id It is possible to control the fluctuation gradient from near zero to a very large gradient. That is, since the resistance R ₄ can be made small, so-called reactive power consumed by other than the FET 1 can be greatly reduced.

FIG. 2 shows an example of calculation using the Spice model under the various conditions of FIG. 4 in the circuit of the first embodiment. Here, as shown in FIG. 4, the resistance R _{4 is set} to 0.5Ω, the first resistor _{R 1} 3000 ohms, the positive source voltages _{V 1} and 5V, when there is no diode D1 third resistor _{R 3,} the case of the second resistor _{R 2} is infinity, the drain current Id at low temperatures as 100 mA, The temperature characteristics of the drain current Id when the drain current Id at high temperature is optimized to be 400 mA, 300 mA, 200 mA, and 150 mA by changing the respective values of the second resistor R ₂ and the third resistor R _3. Indicates. As can be seen from FIG. 2, according to the circuit of the first embodiment, it is possible to generate a temperature fluctuation characteristic of the drain current having an arbitrary gradient (positive gradient) desired.

  FIG. 3 shows the linearity of the drain current under the various conditions of FIG. 4, and it can be seen from FIG. 3 that the linearity of the drain current obtained by the example circuit is very excellent.

FIG. 5 shows the configuration of the second embodiment. This second embodiment is a single power supply automatic bias adjustment circuit using a positive power supply 4 as a single power supply without using a negative power supply.
In this second embodiment, a collector is connected to the source of the FET 1, an NPN second transistor Q2 for controlling the source voltage of the FET is provided, the emitter of the second transistor Q2 is grounded, and a resistor R _{6 is connected to the} base. By connecting the collector of the first transistor Q1 through the circuit, a single power source can be driven. Then, for temperature compensation, as in the first embodiment, the diode D1 and the third resistor R ₃ is connected in parallel with the second resistor R _2.

According to the second embodiment, when the temperature is constant, the change in drain current Id detected by the drain current detection resistor R ₄ (e.g. increase) the collector current of the first transistor Q1 (Ic1) As a result of the change (decrease) and the change (decrease) in the base current (Ib2) of the second transistor Q2, the collector-emitter voltage (Vce2) of the second transistor Q2 changes (increases), thereby causing the source of the FET1 As a result of the voltage being controlled, the drain current changes (decreases) and is kept constant. That is, when the negative power source 3 is provided as in the first embodiment, the gate voltage can be adjusted so that the bias conditions according to the individual characteristics of the FET 1 are satisfied. Cannot make such adjustments. On the other hand, in the second embodiment, there is an advantage that a stable drain current can be obtained by the above operation even when individual characteristics of the FET 1 vary. When the temperature changes, in addition to this, the presence of the diode D1 and the third resistor R _3, temperature compensation can be performed as described above.

FIG. 6 shows a configuration of a third embodiment in which a third transistor is used instead of the diode of the first embodiment.
As shown in FIG. 6, in the third embodiment, a PNP third transistor Q3 in which the collector and base are short-circuited is provided in place of the diode D1. As described in the first embodiment, the base voltage Vb1 of the first transistor Q1 and the base-emitter voltage Vbe1 have almost the same variation, and the drain current Id hardly varies with temperature change. In order to obtain a high accuracy, it is necessary that the temperature characteristics of the voltage of the temperature sensing element and the voltage Vbe1 of the first transistor Q1 are aligned.

  In the third embodiment, a PNP third transistor Q3 having the same characteristics as the first transistor Q1 is used in place of the diode D1 as the temperature sensitive element, and the base-emitter in a state where the base and collector of the third transistor Q3 are short-circuited. By using the inter-voltage Vbe1, accurate temperature compensation can be realized.

In the second embodiment, the PNP third transistor Q3 of the third embodiment may be used in place of the diode D1 as the temperature sensitive element, or the first resistor R ₁ may be used as in the fourth embodiment. in parallel with the diode D1 (or third transistor Q3) and the third may be a resistor R ₃ connected.

  Since it is possible to generate a drain current characteristic having any positive or negative temperature gradient with a simple circuit, in addition to the microwave amplifier mentioned in the embodiment, the oscillation frequency and variable attenuation of an oscillator using an FET It can be used to control the temperature characteristics of the attenuation of the vessel.

1 ... N-ch depletion type FET (field effect transistor),
3 ... Negative power supply, 4 ... Positive power supply,
Q1 ... first (PNP) transistor,
Q2 ... second (NPN) transistor,
Q3 ... third (PNP) transistor (temperature sensing element),
D1 ... diode (temperature sensing element),
R ₁ ... 1st resistance, R ₂ ... 2nd resistance,
R ₃ ... third resistance, R ₄ ... drain current detection resistance.

Claims (2)

In the automatic bias adjustment circuit for FET that drives the FET,
A first transistor connected to the gate or source of the FET and controlling the gate voltage or source voltage;
A drain current detection resistor for detecting the drain current of the FET;
A first resistor connected between the first transistor and ground;
A second resistor connected between the ground-side terminal of the first transistor and a power source;
A temperature-sensitive element that is connected in parallel with the second resistor between the ground-side terminal of the first transistor and a power source, and is a diode or a transistor;
The temperature sensing element is connected in series between the ground-side terminal of the first transistor and the power source, and the temperature gradient of the drain current of the FET is set to an arbitrary gradient other than zero by combination with the second resistor. A third resistor for providing
By controlling the base voltage of the first transistor based on the temperature sensitive element, the second resistance, and the third resistance, the gain temperature compensation of the FET is performed with a drain current having an arbitrary temperature gradient. Automatic bias adjustment circuit for FET. A second transistor for controlling the source voltage of the FET is connected between the source of the FET and the first transistor, the drain current is adjusted via the second transistor, and the FET is driven by a single power source. 2. The FET automatic bias adjustment circuit according to claim 1, wherein the FET automatic bias adjustment circuit is configured as described above .

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