JP2009537080A - Clock signal generation method and apparatus for quadrature sampling - Google Patents

Abstract

  The present invention provides a quadrature sampling clock signal generation method and apparatus used in a receiver. The apparatus first determines an initial clock signal whose frequency is less than twice the carrier frequency of the input signal, then divides the frequency of this initial clock signal by 2 to determine two quadrature intermediate clock signals, Finally, the frequency of the two intermediate clock signals is divided, and two quadrature sampling clock signals are output. The clock signal generation method and apparatus of the present invention can operate the VCO at a relatively low frequency that not only reduces the cost of the VCO but also reduces its power consumption.

Description

Disclosure details

(Field of the Invention)
The present invention relates to a receiver used in the field of wireless communication, and more particularly to a clock signal generation method and apparatus used in a quadrature sampling receiver.

[Background of the Invention]
In a conventional wireless communication receiver, an RF signal received from an antenna is generally subjected to a series of processes to become a baseband or low intermediate frequency signal in advance and then converted to a digital signal. Further, the received RF analog signal typically passes through a series of filters to filter out out-of-band interference waves and to remove noise. A configuration of such a type of receiver has good performance and the requirements imposed on each functional module by a receiver of such configuration are simple. This is because the interference wave is filtered for each stage during signal processing. At the same time, however, this type of receiver is costly due to the low integration level of the elements.

  Recently, another type of receiver configuration has received much attention in the art. Such types of receivers use RF sampling techniques, where the signal received from the antenna is sampled immediately after limited filtering and amplification with respect to the RF band, and then the sampled signal is processed in the discrete domain. As a result, it is possible to use more advanced techniques for discrete signal processing. This type of receiver eliminates many analog circuits and is therefore more flexible in circuit design and more suitable for multimode communication. In addition, during manufacture, the analog and digital circuits of such receivers can utilize the same semiconductor process, thus achieving high integration levels and low costs.

FIG. 1 shows the configuration of an RF sampling receiver employing a quadrature sampling technique. In this case, after processing an RF signal received from an antenna by an RF filter 10 and a low noise amplifier 20, the RF signal is discretely processed. Sampling is performed in two paths each for conversion to a target area. Both sampling frequencies f _s in these two paths are 1 / N of the RF signal carrier frequency f _c , but there is a constant relative delay τ between the _two sampling clock signals CLK ₁ and CLK _2. Therefore, the phase of the carrier at the sampling point of the clock signal in these two paths differs from each other by 90 °. In the discrete domain, out-of-band interference waves and noise in the sampled signal are removed by discrete filters 31 and 32, respectively. Next, the sampled signals are converted into digital signals by analog-digital converters 41 and 42, respectively. Finally, these digital signals are sent to the digital signal processing unit 60 through the digital filters 51 and 52 for baseband signal processing.

The receiver configuration shown in FIG. 1 is attractive because its sampling frequency is relatively low. However, this type of receiver needs to give a 90 ° phase shift to the two clock signals in order to be able to sample the RF signal respectively. In practice, these two clock signals are typically obtained by a device that generates the clock signal shown in FIG. Frequency of the initial clock signal from the voltage-controlled oscillator (VCO) (not shown) is 2f _c. Although having the same frequency as f _c an initial clock signal through the 1/2 divider 700 is divided into two intermediate clock signal having a phase shift of 90 °. As a result, these two intermediate clock signals pass through two 1 / N dividers 701 and 702, respectively, and finally two sampling clock signals required by the receiver are obtained, ie, two The sampling clock signal has a frequency of f _s = f _c / N.

The disadvantage of the above solution is that it is necessary to generate an initial clock signal with a high frequency. Taking the Bluetooth (Bluetooth) system as an example, its carrier frequency _{f c,} is about 2.4GHz. As a result, the VCO must be able to generate an initial clock signal with a frequency of 2f _c , ie about 4.8 GHz. However, VCOs operating at such high frequencies are not only costly but also very power consuming, so it is not economical for a receiver to use such types of VCOs.

[Summary of Invention]
One of the objects of the present invention is a method and apparatus for generating a clock signal for quadrature sampling used in a receiver, which uses an initial clock signal having a relatively low frequency and the cost of the VCO and It is an object of the present invention to provide a method and apparatus for reducing power consumption.

A clock signal generation method for quadrature sampling of the present invention used in a receiver is as follows:
Obtaining an initial clock signal whose frequency is lower than a predetermined multiple of the carrier frequency of the input signal;
Dividing the frequency of the initial clock signal by 2 to obtain two quadrature intermediate clock signals;
-Dividing the frequency of each of the two intermediate clock signals and outputting two quadrature sampling clock signals.

The quadrature sampling clock signal generator of the present invention used in the receiver is
An initial clock signal generator for generating an initial clock signal whose frequency is lower than a predetermined multiple of the carrier frequency of the input signal;
A first frequency divider for receiving an initial clock signal and dividing the frequency of the initial clock signal by 2 to obtain two quadrature intermediate clock signals;
-Each having two intermediate clock signals, and two second frequency dividers for dividing the frequencies of the two intermediate clock signals and outputting two quadrature sampling clock signals.

  In addition, in the above-described method and apparatus for generating a clock signal for quadrature sampling of the present invention, the receiver sampling factor for the input signal is N and the frequency of the two intermediate clock signals is divided by α. In this case, the frequency of the initial clock signal is 1 / p of a predetermined multiple of the carrier frequency of the input signal, where p is an odd number and pα = N.

  The frequency of the initial clock signal used by the method and apparatus for generating a clock signal for quadrature sampling proposed by the present invention is only 1 / p of the frequency required in the conventional clock signal generator. Therefore, in the clock signal generation method and apparatus of the present invention, it is possible to operate the VCO at a relatively low frequency that can reduce not only the cost of the VCO but also its power consumption.

  Other objects and advantages will become apparent and understood by referring to the following description and claims taken in conjunction with the accompanying drawings, together with a more thorough understanding of the present invention.

  The present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

  Throughout the drawings, the same reference numerals indicate similar or corresponding features or functions.

Detailed Description of the Invention
For a quadrature sampling receiver, it is necessary to provide two clock signals with a phase shift of 90 ° to perform quadrature sampling on the received RF signal respectively. The frequency of the initial clock signal of the conventional clock signal generator shown in FIG. 2 in a state where the two clock signals obtained by dividing the frequency of the initial clock signal maintain a 90 ° phase shift at the carrier frequency. Therefore, the present invention proposes a novel solution for generating a clock signal, which will be described in detail with reference to FIG.

In a quadrature sampling receiver, if the carrier frequency of the signal is f _c and the subsampling factor is N, the sampling frequency will be f _c = f _s / N. Since N is an integer, N can be expressed as the product of two numbers, ie, N = αp, where p is the largest odd number, p ≦ N, and α is an integer. .

FIG. 3 is a block diagram showing the overall configuration of a clock signal generator for quadrature sampling according to the present invention. The frequency of the initial clock signal is 2f _c / p, and the initial clock signal is divided into two intermediate clock signals having the same frequency of f _{s, 1} = f _c / p by the 1/2 divider 700. Next, these two intermediate clock signals pass through two 1 / α dividers 703 and 704, respectively, and finally become two sampling clock signals of frequency f _s = f _c / αp = f _c / N. Become.

The time shift between the two intermediate clock signals described above is as follows: τ = (90 ° / 360 °) T _{s, 1} = T _s, 1/4 = pT _c / 4, _here, it is _{T s, 1 = 1 / f} s, 1 and _{T c} = 1 / _f c. After the frequency of these two intermediate clock signals is divided by the two 1 / α dividers 703 and 704, respectively, these frequencies become lower, but the time shift between these two intermediate clock signals remains unchanged. Remains. Therefore, the time shift between the two sampling clock signals whose resulting frequency is f _s = f _c / αp = f _c = N is also τ. The time shift τ is equivalent to a phase shift of (pT _c / 4) / T _c × 360 ° = p90 ° at the carrier frequency.

  Since p is an odd number, it can be expressed as p = 4m ± 1 (in this equation, m is an integer), so the above-described phase shift p90 ° = m (360 °) ± 90 °. Thus, it can be seen that the two clock signals output from the clock signal generator of FIG. 3 have a phase shift of m (360 °) ± 90 °, which meets the requirements for quadrature sampling. For quadrature sampling receivers, the time shift effect on receiver performance is negligible as long as the time shift τ satisfies τ << 1 / B (where B is the bandwidth of the RF signal). .

The frequency of the initial clock signal output by the clock signal generator of the present invention shown in FIG. 3 is only 2f _c / p, which is the initial clock required by the conventional clock signal generator shown in FIG. 1 / p of the frequency of the signal. Taking a Bluetooth system as an example, the system carrier frequency is about 2.4 GHz, and in a conventional clock signal generator, a VCO can generate an initial clock signal of about 4.8 GHz. It is necessary. However, in the case of the clock signal generator of the present invention, when the sub-sampling factors N are 12, 13, and 14 and p is 3, 13, and 7, respectively, the corresponding frequency of the initial clock signal is , About 0.8 GHz, about 0.185 GHz, and about 0.343 GHz, respectively, which is much lower than the conventionally required 4.8 GHz. Therefore, in the clock signal generation method and apparatus of the present invention, it is possible to operate the VCO at a relatively low frequency that can reduce not only the cost of the VCO but also its power consumption.

  Further, in certain cases, for example, when N is an odd number and p = N, the clock signal generator of FIG. 3 can be simplified to the form shown in FIG. Units 703 and 304 are not required, which further reduces cost and power consumption. Therefore, when designing a receiver, it is preferred that N is an odd number so that good effects are achieved by the present invention, while extreme cases where N should be an integer of 2 should be avoided. . This is because this does not bring the advantages of the present invention.

The above-described embodiments are primarily aimed at providing a zero IF (intermediate frequency) quadrature sampling receiver, ie, f _s = f _c / N. Regardless of whether quadrature sampling is performed on the IF or RF signal, not only can the clock signal generation method and apparatus proposed by the present invention be utilized in a zero IF quadrature sampling receiver, Obviously, it can be used for other similar quadrature sampling receivers. For example, in a low IF quadrature sampling receiver, ie, f _s = (f _c ± f _IF ) / N, N can also be expressed as the product of two numbers, ie, N = αp, where , P is the largest odd number, p ≦ N, and α is an integer. Thereafter, by utilizing the clock signal generation method and apparatus of the present invention, the quadrature sampling clock signal required by the receiver is obtained.

  It should be understood by those skilled in the art that many modifications can be made to the clock signal generation method and apparatus disclosed herein without departing from the subject matter of the present invention. Therefore, the scope of the present invention should be determined based on the description of the claims.

It is a block diagram which shows the form of a quadrature RF sampling receiver. FIG. 2 is a block diagram illustrating a configuration of a conventional clock signal generator for quadrature sampling. 1 is a block diagram showing an overall configuration of a clock signal generator for quadrature sampling according to the present invention. FIG. 2 is a block diagram illustrating a simplified form of a clock signal generator for quadrature sampling of the present invention.

Claims (12)

A clock signal generation method for quadrature sampling used in a receiver,
Obtaining an initial clock signal whose frequency is lower than a predetermined multiple of the carrier frequency of the input signal;
Dividing the frequency of the initial clock signal by 2 to obtain two quadrature intermediate clock signals;
-Dividing the frequencies of the two intermediate clock signals, respectively, and outputting two quadrature sampling clock signals.   If the sampling factor of the receiver for the input signal is N and the frequency of the two intermediate clock signals is divided by α, the frequency of the initial clock signal is the predetermined frequency of the carrier frequency of the input signal. The method of claim 1, wherein the multiple is 1 / p, where p is an odd number and pα = N.   The method according to claim 1 or 2, wherein the predetermined multiple is twice.   4. The method of claim 3, wherein p is the largest odd number that can be obtained for the determined sampling factor N. A quadrature sampling clock signal generator used in a receiver,
An initial clock signal generator for generating an initial clock signal whose frequency is lower than a predetermined multiple of the carrier frequency of the input signal;
A first frequency divider for receiving the initial clock signal and dividing the frequency of the initial clock signal by 2 to obtain two quadrature intermediate clock signals;
An apparatus comprising two second frequency dividers for receiving the two intermediate clock signals respectively and dividing the frequency of the two intermediate clock signals to output two quadrature sampling clock signals;   When the receiver sampling factor for the input signal is N and the frequency of the two intermediate clock signals is divided by α, the frequency of the initial clock signal is the predetermined frequency of the carrier frequency of the input signal. 6. The apparatus of claim 5, wherein 1 / p of a multiple, where p is an odd number and pα = N.   The apparatus according to claim 5 or 6, wherein the predetermined multiple is twice.   8. The apparatus of claim 7, wherein p is the largest odd number that can be obtained for the determined sampling factor N. A receiver,
A sampling device that performs quadrature sampling on the received signal;
A clock signal generator for providing a sampling clock signal to the sampling device, the clock signal generator comprising:
An initial clock signal generator for generating an initial clock signal whose frequency is lower than a predetermined multiple of the carrier frequency of the input signal;
A first frequency divider for receiving the initial clock signal and dividing the frequency of the initial clock signal by 2 to obtain two quadrature intermediate clock signals;
A receiver having two second frequency dividers for respectively receiving the two intermediate clock signals and dividing the frequency of the two intermediate clock signals to output two quadrature sampling clock signals .   When the receiver sampling factor for the input signal is N and the frequency of the two intermediate clock signals is divided by α, the frequency of the initial clock signal is the predetermined frequency of the carrier frequency of the input signal. The receiver of claim 9, wherein 1 / p of a multiple, where p is an odd number and pα = N.   The receiver according to claim 9 or 10, wherein the predetermined multiple is twice.   12. A receiver according to claim 11, wherein p is the largest odd number that can be obtained for the determined sampling factor N.

Images