JPH09149091A - Demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale when an orthogonal modulation signal is demodulated by digital processing. SOLUTION: The circuit is provided with a band pass filter 1 receiving an orthogonal modulation signal with a carrier frequency Fc, an A/D converter 2 converting an output signal of the band pass filter 1 into a digital signal, an oscillator 3 providing an output of a signal with a frequency Fs to provide the conversion timing of the A/D converter 2, a sign converter 4 converting a sign of the output signal of the A/D converter 2, and a changeover section 5 selecting the output signal of the sign converter 4 alternately into two systems of signals to provide outputs of demodulation signals Ich, Qch of the orthogonal components. The relation between the carrier frequency Fc and the oscillated frequency Fs of the oscillator 3 is selected to be Fs=4Fc/(4k+1) or Fs=4Fc/(4k+3), where k is a natural number.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation circuit for demodulating a quadrature modulated signal by digital processing. A method of demodulating a quadrature modulation signal such as a quadrature phase modulation signal or a quadrature amplitude modulation signal is, for example, to generate a regenerated carrier wave synchronized with a carrier wave phase of a reception quadrature modulated signal by controlling a voltage controlled oscillator, and receive the regenerated carrier wave by this regenerated carrier wave. A synchronous detection method for detecting a quadrature modulation signal and a quasi-synchronous detection method for detecting a reception quadrature modulation signal by generating a signal having a carrier frequency of the reception quadrature modulation signal from a fixed oscillator are known. In such a synchronous detection system and a quasi-synchronous detection system, an analog circuit is used.

[0002]

2. Description of the Related Art FIG. 15 is an explanatory view of a conventional example, showing a main part when a quasi-coherent detection method is applied, 101 is a bandpass filter (BPF), 102 and 103 are mixers, and 1 is a mixer.
04 and 105 are low-pass filters (LPF), 106 and
107 is an AD converter (A / D), 108 is a hybrid circuit of π / 2, 109 is an oscillator having the same oscillation frequency as the input signal frequency Fc, 110 is an identification processing unit, and 111 is a voltage controlled oscillator.

A quadrature modulation signal of frequency Fc is applied to mixers 102 and 103 via a bandpass filter 101, and a signal from an oscillator 109 of oscillation frequency Fc is fed by a hybrid circuit 108 into two systems with a phase difference of π / 2. The signal is branched and added to the mixers 102 and 103, respectively, and mixed, and the low-frequency component is added to the AD converters 106 and 107 via the low-pass filters 104 and 105, and the timing of the output signal of the voltage controlled oscillator 111. Is AD-converted and added to the identification processing unit 110, and the I-channel data Ich and the Q-channel data Qch are output. Also, the carrier phase of the quadrature modulation signal and the oscillator 1
09 voltage control oscillator 11 corresponding to the output signal phase and difference
1 to control the AD conversion timing so as to match the bit timing.

Further, in the case of the synchronous detection system, the oscillator 109 is a voltage controlled oscillator, the phase error component is obtained by baseband processing in the discrimination processing unit, and the voltage error controlled oscillator becomes a direction in which the phase error component becomes zero. The phase is controlled, and the mixers 102 and 103 synchronously detect and output the phase modulation component.

[0005]

In the demodulation circuit of the conventional example, the received quadrature modulated signal is supplied to the band pass filter 101.
After the unnecessary band component is removed by, the signal is branched into two systems, and the output signal of the oscillator 109 is also branched into two signals with a phase difference of π / 2 by the hybrid circuit 108, and the signals are added to the mixers 102 and 103 respectively and mixed. Then, the low-frequency component is output via the low-pass filters 104 and 105. In both the quasi-coherent detection method and the coherent detection method, the circuit configuration in the preceding stages of the AD converters 106 and 107 is not limited to the above. Since it is configured by an analog circuit, it is difficult to reduce the circuit scale, and it is not easy to adjust each part and there is a problem in stability. Also, the AD converters 106, 1
07 is also required for two systems of I and Q channels.

In the quasi-synchronous detection system, the fixed oscillator 109 and the voltage-controlled oscillator 111 for controlling the AD conversion timing are required, so that the circuit configuration becomes complicated. In addition, two systems of AD converter 1
It is conceivable that an AD converter is provided at the subsequent stage of the bandpass filter 101 so that the signals 06 and 107 can be omitted, and thereafter, digital processing is performed. However, if the carrier frequency of the quadrature modulation signal is, for example, 50 MHz, it is necessary to sample the reception quadrature modulation signal at at least 100 MHz, and it is not easy to realize such a high-speed AD converter, and at the subsequent stage. It is difficult to realize even in the mixer etc. because it needs to operate at 100 MHz. An object of the present invention is to demodulate a quadrature modulated signal by digital processing with a relatively simple structure.

[0007]

The demodulation circuit of the present invention comprises:
(1) To provide a bandpass filter 1 for inputting a quadrature modulation signal having a carrier frequency Fc, an AD converter 2 for converting an output signal of the bandpass filter 1 into a digital signal, and a conversion timing of the AD converter 2. Frequency Fs
, A code converter 4 for converting the sign of the output signal of the AD converter, and an output signal of the code converter 4 are alternately switched between two systems of signals to obtain a demodulated signal of orthogonal components. The switching unit 5 outputs Ich and Qch, and the carrier frequency Fc and the oscillation frequency Fs of the oscillator 3 are set to Fs.
= 4Fc / (4k + 1) or Fs = 4Fc / (4k +)
3) (However, k = natural number).

(2) Further, the switching unit 5 is connected to the AD converter 2, and the output signal of the AD converter 2 is alternately made into two-system signals by the switching unit 5, and the two-system signals are respectively coded. First and second code converters for conversion can be connected.

(3) Further, a bandpass filter 1 for inputting a quadrature modulation signal having a carrier frequency Fc, an AD converter 2 for converting an output signal of the bandpass filter 1 into a digital signal in a complementary expression, and this AD converter. Oscillator 3 that outputs a signal of frequency Fs for giving the conversion timing of 2
And a code converter 4 including an exclusive OR circuit for converting a code by adding a complemented output signal of the AD converter 2 and a signal obtained by dividing the output signal of the oscillator 3 into 1/4, and the code conversion. The output signal of the oscillator and the output signal of the oscillator 3 are halved and latched at the rising and falling timings of the signal respectively, and a switching unit 5 including first and second filters, and a carrier frequency Fc and the oscillation frequency Fs of the oscillator 3 can be selected in the relationship of Fs = 4Fc / (4k + 1).

(4) Further, a bandpass filter 1 for inputting a quadrature modulation signal having a carrier frequency Fc, an AD converter 2 for converting an output signal of the bandpass filter 1 into a digital signal in a complementary representation, and this AD converter. Oscillator 3 that outputs a signal of frequency Fs for giving the conversion timing of 2
And a first and second flip-flop for latching the output signal of the AD converter at the rising and falling timings of the signal obtained by dividing the output signal of the oscillator by 1/2. And a first and second exclusive exclusive use for converting the sign by adding the output signals of the first and second flip-flops of the switching unit 5 and the signal obtained by dividing the output signal of the oscillator 3 into 1/4. The carrier frequency Fc and the oscillation frequency Fs of the oscillator 3 are Fs = 4Fc / (4k + 1) or Fs = 4Fc.
/ (4k + 3) (where k = natural number) can be set.

(5) Further, it has a variable-tap-coefficient filter for adding two systems of signals alternately switched and output by the switching section 5, and a timing control section for controlling the variable-tap-coefficient filter. The control unit has a configuration for controlling the tap coefficient and the output timing of the variable tap coefficient filter in accordance with the ratio of the conversion cycle and the bit cycle in the AD converter.

(6) Further, it has a variable tap coefficient filter for adding signals of two systems which are alternately switched by the switching section 5 and a timing control section for controlling the variable tap coefficient filter. The control unit is configured to control the tap coefficient and the output timing of the variable tap coefficient filter according to the ratio between the conversion cycle and the bit cycle in the AD converter and according to the timing correction signal from the bit timing reproduction circuit. I have.

(7) Further, the carrier frequency is set as the center frequency, and the center frequency is switched, and the oscillation frequency Fs of the oscillator and the carrier frequency Fc are Fs = 4Fc /
A bandpass filter selected to maintain the relationship of (4k + 1) or Fs = 4Fc / (4k + 3) can be provided.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of a main part of a first embodiment of the present invention, in which 1 is a bandpass filter (BPF) and 2 is A.
D converter (A / D), 3 is an oscillator, 4 is a code converter, 5
Is a switching unit for switching between Ich and Qch alternately. The bandpass filter 1 has a carrier frequency Fc of a quadrature modulation signal.
The carrier frequency Fc in this case can be a reception frequency or a frequency-converted intermediate frequency.

The oscillation frequency Fs of the oscillator 3 is selected as Fs = 4Fc / (4k + 1) (1) or Fs = 4Fc / (4k + 3) (2) where k is a natural number. That is, the oscillation frequency Fs is lower than the carrier frequency Fc of the quadrature modulation signal and has an odd ratio relationship.
In addition, 2Bw <Fs. Further, k is selected so that the oscillation frequency Fs does not become a frequency lower than twice the symbol rate.

The output signal of the oscillator 3 is converted into an AD converter 2
Is added as a sampling timing signal, to the code converter 4 as a + or − code conversion timing signal, and to the switching unit 5 as a switching control signal. Therefore, the quadrature modulated signal can be digitized by one AD converter 2 according to the frequency Fs lower than the carrier frequency Fc of the quadrature modulated signal, and the demodulated signals Ich and Qch of the quadrature component can be output from the switching unit 5.

FIG. 2 shows a first equivalent circuit of the first embodiment of the present invention. The oscillation frequency Fs of the oscillator 3 in FIG.
Shows an equivalent circuit when Fs = 4Fc / (4k + 1) is selected. In the figure, 2a and 2b are AD converters (A / D), 3a and 3b are oscillators, 4a and 4b are code converters, and the AD converter 2, oscillator 3 and code converter 4 of FIG. Is an equivalent circuit when the two are separated into two systems, where I (t) is the I-channel data of the quadrature component and Q (t) is the Q-channel data, the input quadrature modulation signal is Re [ U (t) exp {j (2πFc · t + φ)}] (3) U (t) = I (t) + jQ (t) (4) Such an expression format is already well known. Note that Re indicates that the part in [] is the real number part, and φ indicates the phase difference of the carrier wave.

In the present invention, as described above, the sampling is performed at the timing of the oscillation frequency Fs having the odd ratio to the carrier frequency Fc of the quadrature modulation signal and digitization is performed. Oscillators 3a, 3b
Is the oscillation frequency F of the oscillator 3 in FIG.
In the case where s is selected to Fs = 4Fc / (4k + 1) as described above, and since the oscillator 3 is divided into two, it can be expressed as fs / 2 = 2Fc / m. In addition,
m = 4k + 1, k is a natural number, and m is an odd number. The sample time in one AD converter 2a is n
= 0, 1, 2, ..., nm / 2Fc,
The sampling time in the other AD converter 2b is nm / 2Fc + having a time difference of 1 / Fs = m / 4Fc from this.
It becomes m / 4Fc. In the code converters 4a and 4b, by multiplying by (-1) ⁿ , +1 and -1 are alternately multiplied to perform code conversion.

Therefore, in the above equation (3), t = nm / 2F
substituting c, and (-1) Multiplying ^n, (-1) ⁿ Re [U {nm / 2Fc} exp { nmπ + φ} j ] = Re [U {nm / 2Fc} exp { n (m + 1) π + φ } J] = Re [U {nm / 2Fc} exp {φ} j] (5).

In the above equation (4), t = nm / 2Fc + m
/ 4Fc substitutes, and (-1) Multiplying ^n, (-1) ⁿ Re [U {nm / (2Fc) + 1 / fs} exp {nmπ + mπ / 2 + φ} j ] = Re [U {nm / (2Fc) + 1 / fs} exp {n (m + 1) π + π / 2 + φ} j] = Re [U {nm / (2Fc) + 1 / fs} exp {π / 2 + φ} j] (6)

Therefore, the demodulated signals Ich and Qch are
From equations (5) and (6), Ich = Re [U {nm / (2Fc)} exp {j (φ)}] Qch = Re [U {nm / (2Fc) + 1 / fs} exp {j (π / 2 + φ)}].

That is, it can be seen that the code converters 4a and 4b can output the demodulated signals Ich and Qch having a phase difference of π / 2. In this way, the quadrature-converted signal is sampled by the single AD converter 2 at a sampling timing that is an odd fraction of the carrier frequency Fc of the quadrature-modulated signal and converted into a digital signal, which is then converted into a positive or negative signal by the code converter 2. By performing the code conversion, the demodulated signal Ic of the digital orthogonal component is obtained.
It is possible to obtain h and Qch. This is the AD converter 2
Since the quadrature detection circuit is constituted by the code converter 4 and the switching unit 5, the demodulation signals Ich and Qch obtained by demodulating the quadrature modulation signal are level-identified in a bit timing reproduction circuit or the like (not shown). The data is reproduced by the above.

FIG. 3 shows a second equivalent circuit of the first embodiment of the present invention. The oscillation frequency Fs of the oscillator 3 in FIG.
Shows an equivalent circuit when Fs = 4Fc / (4k + 3) is selected. The same reference numerals as those in FIG. 2 indicate the same parts, and m =
By setting 4k + 3, the code converter 4b has (-
1) It will be multiplied by ^{n + 1} .

Then, in the above equation (3), t = nm / 2F
Substituting c and multiplying by (-1) ⁿ yields equation (5). Further, in the above equation (4), t = nm / 2Fc + m /
Substituting 4Fc, and (-1) Multiplying ^{n + 1, (-1) n} + 1 Re [U {nm / (2Fc) + 1 / fs} exp {nmπ + mπ / 2 + φ} j ] = -Re [U {Nm / (2Fc) + 1 / fs} exp {n (m + 1) π + 3π / 2 + φ} j] = Re [U {nm / (2Fc) + 1 / fs} exp {π / 2 + φ} j] (7), It becomes similar to the above-mentioned equation (6). The code converters 4a and 4a have the same relationships as the expressions (5) and (6).
It can be seen that demodulated signals Ich and Qch with a phase difference of π / 2 are obtained from b.

FIG. 4 is an explanatory view of the essential parts of the second embodiment of the present invention. The same reference numerals as those in FIG.
4-1 and 4-2 are code converters. This example is
The case where the first and second code converters 4-1 and 4-2 which respectively add signals of two systems alternately switched by the switching unit 5 is provided is shown, and the oscillation frequency Fs of the oscillator 3 is the same as that of the above-described embodiment. Similar to the example, Fs = 4Fc / (4k + 1) or Fs =
4Fc / (4k + 3) can be selected. Further, in the code converters 4-1 and 4-2, compared with the case in FIG. 1, since the digital signals alternately switched by the switching unit 5 are input, the code conversion can be performed at a low speed. it can. In this case, although two code converters 4-1 and 4-2 are required, a low-speed operation configuration is sufficient, integration into an integrated circuit is facilitated, and an economical configuration is possible depending on the number of bits of a digital signal. Becomes

FIG. 5 is a block diagram of the first embodiment of the present invention, showing a specific configuration of the configuration shown in FIG. 1, 11 is a bandpass filter (BPF), and 12 is an AD.
A converter (A / D), 13 is an oscillator, 14a to 14d are exclusive OR circuits (EOR) constituting a code converter, 15
Reference numerals a and 15b are first and second flip-flops (DFF) that form a switching unit, and 16 is a frequency divider.

As mentioned above, the oscillation frequency Fs of the oscillator 13 is Fs with respect to the carrier frequency Fc of the quadrature modulation signal.
= 4Fc / (4k + 1) is selected, the quadrature modulation signal is applied to the AD converter 12 via the bandpass filter 11 having the bandwidth Bw, and the frequency F from the oscillator 13 is supplied.
It is sampled by the timing signal of s, converted into a digital signal of a 4-bit complement expression, and each bit is input to the exclusive OR circuits 14a to 14d.

The frequency divider 16 is reset by the reset signal RST, the initial value 0 is set, and the oscillator 1
The frequency-divided output signal fa obtained by dividing the signal of the frequency Fs from 3 into 1/4 is added to the exclusive OR circuits 14a to 14d, and 1/2 is also added.
The divided output signal fb is set to the flip-flops 15a, 1a.
5b clock terminal CK. This one flip-flop 15a shows the rising set and the other flip-flop 15b shows the falling set, and sets 4 bits of the output signals of the exclusive OR circuits 14a to 14d. Therefore, the exclusive OR circuits 14a to 14a constituting the code converter 2
The output signal of 14d can be alternately switched and output by the flip-flops 15a and 15b.

The quadrature modulation signal passed through the band pass filter 11 is sampled at the timing of the frequency Fs, and A
From the D converter 12 to a1, a2, a3, a4, a5, a
, A7, a8, ... Complementary digital signals are sequentially output, exclusive OR circuits 14a to 14
Since the sign of the digital signal can be inverted by setting the frequency-divided output signal fa added to d to "1", the frequency-divided output signal fa with the frequency Fs signal being ¼
Is "0", "0", "1", "1", "0", "0",
Since "1", ..., a1, a2, -a3, -a
Code conversion can be performed as in 4, a5, a6, -a7, -a8, ....

.. are latched in the flip-flop 15a by the frequency-divided output signal fb obtained by halving the signal of the frequency Fs, and demodulation of the I channel is performed. The signal Ich is output to the flip-flop 15b as a2, -a4, a6, -a.
.. are latched and the demodulated signal Qc of the Q channel is latched.
It is output as h. That is, the exclusive OR circuits 14a-1
4d is converted by the code converters 4a and 4b shown in FIG.
1) It shows the equivalent structure to the case of multiplying ⁿ .
It is possible to obtain demodulated signals Ich and Qch of orthogonal components. The number of bits of the digital signal can of course be larger than the above-mentioned 4 bits.

FIG. 6 is a block diagram of the second embodiment of the present invention, showing a specific configuration of the configuration shown in FIG. 4, 21 is a bandpass filter (BPF), and 22 is an AD.
A converter (A / D), 23 is an oscillator, and 24a to 24f are exclusive OR circuits (EO) constituting the first and second code converters.
R), 25a and 25b are first and second flip-flops (DFF) that constitute a switching unit, 26 is a frequency divider, and 27 is a flip-flop (DFF).

The flip-flops 25a and 25b correspond to the switching unit 5 in FIG. 4, the exclusive OR circuits 24a to 24c are in the first code converter 4-1 in FIG. 4, and the exclusive OR circuit 24 is in the exclusive OR circuit 24.
d to 24f correspond to the second code converter 4-2 in FIG. The oscillation frequency Fs of the oscillator 23 is Fs = 4Fc /
When (4k + 1) is selected, the frequency divider 26 is reset by the reset signal RST to set the initial value 0, and when Fs = 4Fc / (4k + 3) is selected, the frequency divider 26 is reset signal. Initial value 1 is set by resetting at RST.

Further, the AD converter 22 shows a case where the quadrature modulation signal passed through the band pass filter 21 is sampled at the frequency Fs and converted into a digital signal of the complement representation of the 3-bit structure. The flip-flop 25a outputs the digital signal to 1/2 of the frequency divider 26.
The divided output signal fb is set at the rising edge of the divided output signal fb, and the flip-flop 25b is set at the falling edge of the divided output signal fb to alternately switch the digital signal to two systems.

Further, a quarter frequency division output signal fa of the frequency divider 26
Is added to the exclusive OR circuits 24a to 24c, and the divided output signal fa is delayed by 1 / Fs by the flip-flop 27 to be added to the exclusive OR circuits 24d to 24f to be added to the output signal phases of the flip-flops 25a and 25b. In addition, the code converters 4a and 4b for multiplying (-1) ⁿ in FIG.
By an operation equivalent to, it is possible to alternately perform code conversion on a 3-bit digital signal. Therefore, the demodulated signal I having a 3-bit structure is output from the exclusive OR circuits 24a to 24c.
ch, and the exclusive OR circuits 24d to 24f output a demodulated signal Qch having a 3-bit structure.

When Fs = 4Fc / (4k + 3) is selected, the frequency division output signal fa is reset by the reset signal RST of the frequency divider 26 to set the initial value to 1.
"0", "1", "1", "0", "0", "1",
“1”, ..., and the output signal of the AD converter 22 becomes a
1, a2, a3, a4, a5, a6, a7, a8, ...
.. is switched by the flip-flops 25a and 25b to add a1, a3, a5, a7, ... To the exclusive OR circuits 24a to 24c, and a2, a4, a
6, a8, ... Are added to the exclusive OR circuits 24d to 24f. Therefore, code-converted a1, -a3, a
5, -a7, ... Demodulated signal Ich and -a2, a4
Demodulated signals Qch of -a6, a8, ... Are output.

Therefore, as in the case shown in FIG. 3, in the exclusive OR circuits 24a to 24c, it is equivalent to the multiplication of (-1) ⁿ , and the exclusive OR circuits 24d to 2d.
In 4f, it is equivalent to performing multiplication by (-1) ^{n + 1} , and demodulated signals Ich and Qch can be obtained respectively.

FIG. 7 is a block diagram of the third embodiment of the present invention, in which 31 is a bandpass filter (BPF), 32 is an AD converter (A / D), 33 is an oscillator, and 34a to 34d.
Is an exclusive OR circuit (EOR) that constitutes a code converter, 3
5a and 35b are flip-flops (D
FF), 36 is a frequency divider, and 37 is an adder. This embodiment shows a case where a two's complement representation is used, and as shown in FIG. 1, a flip-flop 35 is provided at the subsequent stage of the code converter.
The case where the switching unit composed of a and 35b is arranged and the oscillation frequency Fs of the oscillator 33 is selected as Fs = 4Fc / (4k + 3) with respect to the carrier frequency Fc of the quadrature modulation signal is shown.

Therefore, the frequency divider 36 determines that the reset signal RS
The reset value is set by T to set the initial value 1, and the flip-flop 35a is Fs / 2 of the frequency divider 36.
Of the frequency division output signal fb, the flip-flop 35b is set at the rise of the frequency division output signal fb, and the Fs / 4 frequency division output signal fa of the frequency divider 36 is set to the exclusive OR circuit 34a. The output signals of .about.34d are added by the adder 37 and added to the flip-flops 35a and 35b as a 5-bit digital signal.

Therefore, the code converter including the exclusive OR circuits 34a to 34d performs code conversion by multiplying the digital signal on the demodulated signal Ich side by (-1) ⁿ , as in the case shown in FIG. However, the digital signal on the demodulation signal Qch side is equivalent to a code conversion by multiplying by (−1) ^{n + 1} , and the flip-flops 35a and 35b alternately switch to the demodulation signals Ich and Qch. You can

FIG. 8 is an explanatory view of the essential portions of the fourth embodiment of the present invention, in which the same reference numerals as those in FIG. 1 designate the same parts, and 6a and 6b.
Is a variable tap coefficient filter (ADF), and 7a and 7b are timing control units (TC). In this embodiment, a quadrature modulation signal with a carrier frequency Fc is Fs = 4Fc / (4k +
1) or the frequency F in the relationship of Fs = 4Fc / (4k + 3)
s, the AD converter 3 samples and converts into a digital signal, the code converter 4 converts the code, and the switching unit 5 alternately switches and outputs the digital demodulated signal. The tap coefficient variable filter 6a, Waveform shaping by 6b, demodulated signal I matched with bit timing
It outputs ch and Qch.

The timing of sampling the orthogonal modulation signal of the carrier frequency Fc and converting it into a digital signal is different from the bit timing, but the bit frequency R
The relationship between s and the sampling frequency fs = 4Fc / m is known in advance, and the timing required for bit reproduction is 1 / R.
Since it is an integer multiple of s, the tap coefficients of the variable tap coefficient filters 6a and 6b are controlled by the timing control units 7a and 7b, and the demodulated signal Ic matched to the identification timing is obtained.
It outputs h and Qch.

FIG. 9 is an explanatory diagram of the variable tap coefficient filter. FIG. 9 shows an example of the variable tap coefficient filters 6a and 6b shown in FIG. 8. 41 _{1 to} 41 ₅ , 42 _{1 to} 42 ₅ are flip-flops, and 43 ₁ to 43 ₅ multipliers, 44 _{1-44 5}
Is a tap coefficient memory (ROM), and 45 is an adder.
Further, Din is an input digital signal which is alternately switched by the switching unit 5 and is input, CLK is a clock signal indicating the timing of the input digital signal, LT is a load timing signal for the flip-flops 42 _{1 to} 42 ₅ , and TA
D is the tap coefficient addresses for the tap coefficient memory 44 ₁ ~44 _5, Dout indicates an output digital signal which corresponds to the demodulated signal Ich, Qch.

[0043] The tap coefficient memory 44 _{1-44 5} is constituted by a read only memory for storing the tap coefficients and the tap coefficients read out is applied to the multiplier 43 ₁ to 43 ₅ in accordance with the tap coefficients address TAD, flip-flop 42 _{1-42 5} is multiplied to the latched digital signals, are added by the adder 45 becomes the output digital signal Dout. Such a variable tap coefficient filter can apply various known structures, and can further increase the number of taps.

FIG. 10 is an explanatory diagram of a timing control unit according to the fourth embodiment of the present invention, and the timing control unit 7 of FIG.
The structure of a and 7b is shown. In the figure, 51 is an adder,
52 is a subtractor, 53 is a selector, 54, 56 to 58 are flip-flops (DFF), 55 is a comparator, 59 is an AND circuit (AND), and 60 is a tap coefficient memory (ROM).
It is. Also, CK of the flip-flop is a clock terminal, Q
Indicates an output terminal.

The tap coefficient memory 60, which corresponds to the tap coefficient memory 44 _{1-44 5} tap coefficients variable filter in FIG. 9, the tap coefficients address TAD 9 is output from the subtracter 52, and flip-flop From 58,
Tap coefficient data TPD added to the multiplier 43 ₁ to 43 ₅ of FIG. 9 is output. Also from the flip-flop 56 to FIG.
The load timing signal LT applied to the flip-flops 42 _{1 to} 42 ₅ is output. The clock signal CLK is the same as the clock signal CLK applied to the flip-flops 41 _{1 to} 41 ₅ of FIG. Also, X and Y are X: Y = 1 /
Rs: 2 / fs. In this case, 4Fc /
Since the bit frequency Rx is lower than the sampling frequency in the relation of m = fs, the relation of X> Y is established.

Further, the selector 53 selects the initial value by the reset signal * RST, and thereafter selects the output signal of the adder 51 and adds it to the flip-flop 54. Also subtractor 52
Is an AND circuit 5 from the output signal of the flip-flop 54.
The output signal of 9 is subtracted. Further, the comparator 55 compares the latch output signal with X to the flip-flop 54, and outputs "1" when the latch output signal becomes large.

If the output signal of the adder 51 is selected by the selector 53 and the output signal of the comparator 55 is "0" at that time, the output signal of the subtractor 52 is Y at the timing of the next clock signal CLK. Therefore, the output signal of the adder 51 is 2Y. Similarly, the clock signal CL
Accumulation of Y is performed at every K timing. Then, the comparator 55 compares ΣY and X, and when ΣY> X, the comparison output signal becomes “1”, and X is added to the subtractor 52 via the AND circuit 59, so that the subtractor At 52, the subtraction of ΣY−X is performed.

Further, the comparison output signal "1" is set to the clock signal C.
The flip-flop 41 ₁ is latched by the flip-flop 56 at the timing of LK and used as the load timing signal LT to be added to the flip-flops 42 _{1 to} 42 ₅ in FIG.
To 41 input digital signal Din held sequentially shifted by ₅ is latched in the flip-flop 42 _{1-42 5.} Also, "1" of the comparison output signal is latched in the flip-flop 57, the latch output signal is added to the clock terminal CK of the flip-flop 58, and the output signal of the subtractor 52 is used as an address to read the tap coefficient data from the tap coefficient memory 60. Is latched, and the multipliers 43 ₁ to 4 in FIG.
The tap coefficient data TPD added to 3 ₅ is used.

The initial value added to the above-mentioned selector 53 is
The values are shifted by Y / 2 on the I channel side and the Q channel side. Also OQPSK (Offset Qua
Y / 2 in the case of drature phase shift shifting
The value is shifted by + X / 2. By controlling the variable tap coefficient filters 6a and 6b by the timing control units 7a and 7b having such a configuration, it is possible to output the digital demodulated signals Ich and Qch at the timing corresponding to the bit period (1 / Rs). it can.

FIG. 11 is an explanatory view of the essential parts of the fifth embodiment of the present invention, in which the same reference numerals as those in FIG.
B is a timing control unit. In this embodiment, demodulated signals Ich and Q from the variable tap coefficient filters 6a and 6b are used.
A timing correction signal BT is added to the timing control units 7A and 7B from a bit timing reproduction circuit (not shown) that identifies the channel and reproduces the bit timing so that the digital demodulated signals Ich and Qch are matched with the identification timing. To control.

FIG. 12 is an explanatory diagram of the timing control section of the fifth embodiment of the present invention. The same reference numerals as in FIG. 10 indicate the same parts, and 61 is an adder. The adder 61 adds the above-mentioned X and the timing correction signal BT from the bit timing reproduction circuit (not shown), and adds it to the comparator 55 and the AND circuit 59.

When the timing correction signal BT from the bit timing reproduction circuit advances the bit timing,
By setting BT and outputting X-BT by the adder 61, the timing at which the comparison output signal of the comparator 55 becomes "1" becomes faster, and as a result, the load timing signal added to the variable tap coefficient filters 6a, 6b. LT becomes faster. On the contrary, when the timing correction signal BT is set to + BT and X + BT is output by the adder 61, the comparator 5
The timing at which the comparison output signal of 5 becomes "1" is delayed, whereby the tap coefficient variable filters 6a, 6
The load timing signal LT added to b is delayed.

Therefore, by controlling the load timing signal LT and the tap coefficient, the bit period (1 / R
s) and a digital demodulation signal I controlled so as to have an optimum timing for identifying bits in a cycle corresponding to
It is possible to output ch and Qch.

FIG. 13 is an explanatory view of the essential parts of the sixth embodiment of the present invention, in which the same reference numerals as those in FIG. 1 designate the same parts, and 1A shows the passage of Sw <Bw when the orthogonal modulation signal band is Sw. Variable center frequency band pass filter having band Bw, 8
Is a selection control unit.

In this embodiment, the reception frequency is switched by switching the center frequency of the bandpass filter 1A by the selection control section 8, and even in this case, the oscillation frequency Fs of the oscillator 3 is the reception quadrature modulation. For the carrier frequency Fc of the signal, Fs = 4Fc / (4k +
1) or Fs = 4Fc / (4k + 3), the AD converter 2 converts the signal into a digital signal and the code converter 4 performs the code conversion as in the above-described embodiments. By alternately switching by the switching unit 5, it is possible to obtain demodulated signals Ich and Qch of orthogonal components. Further, as shown in FIG. 4, the digital signal converted by the AD converter 2 is alternately switched by the switching unit 5 to 2
The present invention can be applied to the case where the system signals are used and the code conversion is performed by the code converters 4-1 and 4-2, respectively.

FIG. 14 is an explanatory view of the main part of the channel selection section of the sixth embodiment of the present invention, in which 71 _{1 to} 71 ₃ are band pass filters (BPF1 to BPF) having different center frequencies.
PF3), 72 is a selector (SEL), 73 is an AD converter (A / D), and 74 is an oscillator. In the cross modulation signal of a carrier frequency of Fc1～Fc3, bandpass filter 71 ₁ to 71 _3, respectively the carrier frequency Fc1~
It has a center frequency of Fc3 and a bandwidth of Sw> Bw.

The selector 72 is controlled by the selection signal,
Channels can be selected by selectively connecting the bandpass filters 71 _{1 to} 71 ₃ to the AD converter 73. That is, this is a configuration corresponding to the channel selection unit including the center frequency variable bandpass filter 1A and the selection control unit 8 in FIG. In that case, the oscillator 74
For the oscillation frequency Fs of, the carrier frequencies Fc1 to Fc3 are selected so that the relationship of Fs = 4Fc / (4k + 1) or Fs = 4Fc / (4k + 3) can be maintained.

For example, 4 (Fc1) / 9,4 (Fc2)
/ 17,4 (Fc3) / 25 carrier frequency, that is, Fc1 = Fs9 / 4 = 2.25Fs, Fc2
= Fs17 / 4 = 4.25Fs, Fc3 = Fs25 / 4
= 6.25 Fs, the oscillation frequency Fs of the oscillator 74 is fixed, and the selector 72 is controlled to select and receive the quadrature modulated signals of the carrier frequencies Fc1 to Fc3, and the AD converter 73 converts the quadrature modulated signals into digital signals. A quadrature component demodulated signal can be obtained by converting and performing code conversion in the same manner as in the above-described embodiment and then alternately switching, or by alternately performing code conversion. The relationship described above is further extended to Fc4 = Fs33 /
It is also possible to select 4, Fc5 = Fs41 / 4.

The present invention is not limited to the above-mentioned embodiments, but can be variously added and changed. For example, the oscillation frequency Fs of the oscillator is divided to obtain a desired sampling timing signal. Alternatively, the code converter can be configured to perform code conversion by the same processing as that of the signed arithmetic circuit.

[0060]

As described above, according to the present invention, the oscillation frequency Fs of the oscillator 3 is set to the carrier frequency Fc of the received signal or the frequency-converted intermediate frequency signal in the wireless communication system or the wired communication system. Fs = 4Fc / (4
k + 1) or Fs = 4Fc / (4k + 3), sampling is performed in the AD converter 2 by this frequency Fs and converted into a digital signal, code conversion is performed by the code converter 4, and the switching unit 5 outputs 2 It is possible to obtain demodulated signals Ich and Qch of orthogonal components by distributing to the signals of the system or by distributing to the signals of the two systems by the switching unit 5 and then performing code conversion by the code converter. All the subsequent stages of the pass filter 1 can be configured by digital circuits.

Therefore, the operation can be stabilized and the integrated circuit can be easily formed. Further, only one AD converter 2 is required, and the oscillator 3 can be a fixed oscillator, and unlike the quasi-synchronous detection method, it is not necessary to provide an oscillator with a bit period. Has the advantage that it can be significantly reduced.

Further, it is possible to output the demodulated signals Ich and Qch at a timing at which an identification error does not occur by adding the demodulated signal of the quadrature component to the variable tap coefficient filter and correcting the relationship between the sampling period and the bit period. There is. Further, the use of the timing correction signal from the bit timing reproduction circuit has an advantage that a more stable demodulation circuit can be realized. Further, the carrier frequency Fc of the quadrature modulation signal and the oscillator 3
When the relationship of the odd number ratio with the oscillation frequency Fs can be maintained as described above, there is an advantage that the channel switching configuration can be easily realized by switching the center frequency of the bandpass filter 1.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a main part of a first embodiment of the present invention.

FIG. 2 is a first equivalent circuit of the first embodiment of the present invention.

FIG. 3 is a second equivalent circuit of the first embodiment of the present invention.

FIG. 4 is an explanatory view of a main part of a second embodiment of the present invention.

FIG. 5 is a block diagram of a first embodiment of the present invention.

FIG. 6 is a block diagram of a second embodiment of the present invention.

FIG. 7 is a block diagram of a third embodiment of the present invention.

FIG. 8 is an explanatory view of a main part of a fourth embodiment of the present invention.

FIG. 9 is an explanatory diagram of a variable tap coefficient filter.

FIG. 10 is an explanatory diagram of a timing control unit according to the fourth embodiment of the present invention.

FIG. 11 is an explanatory view of a main part of a fifth embodiment of the present invention.

FIG. 12 is an explanatory diagram of a timing control unit according to the fifth embodiment of the present invention.

FIG. 13 is an explanatory view of a main part of a sixth embodiment of the present invention.

FIG. 14 is an explanatory diagram of a channel selector according to a sixth embodiment of the present invention.

FIG. 15 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 1 band pass filter (BPF) 2 AD converter (A / D) 3 oscillator 4 code converter 5 switching unit

Claims (7)

[Claims] 1. A bandpass filter for inputting a quadrature modulation signal having a carrier frequency Fc, an AD converter for converting an output signal of the bandpass filter into a digital signal, and a frequency for giving a conversion timing of the AD converter. Fs
, A code converter for converting the sign of the output signal of the AD converter, and an output signal of the code converter are alternately switched to signals of two systems, and a demodulated signal of orthogonal components is output. The carrier frequency Fc and the oscillation frequency Fs of the oscillator are Fs = 4Fc / (4k + 1) (where k = natural number) or Fs = 4Fc / (4k + 3) (where k = natural number). ) A demodulator circuit characterized by being selected according to the relationship. 2. The switching unit is connected to the AD converter,
The output signal of the AD converter is alternately made into a signal of two systems by the switching unit, and first and second code converters for respectively performing code conversion on the signals of the two systems are connected. The demodulation circuit according to Item 1. 3. A bandpass filter for inputting a quadrature modulation signal having a carrier frequency Fc, an AD converter for converting an output signal of the bandpass filter into a digital signal in a complementary representation, and a conversion timing of the AD converter. Frequency Fs for
, A code converter including an exclusive OR circuit for converting a code by adding a complemented output signal of the AD converter and a signal obtained by dividing the output signal of the oscillator by 1/4. And the output signal of the code converter is 1 /
A switching unit formed of first and second flip-flops that latch at the rising and falling timings of the signal divided by 2, respectively, and the carrier frequency Fc and the oscillation frequency Fs of the oscillator are = 4Fc / (4k + 1) (where k = natural number). 4. A bandpass filter for inputting a quadrature modulation signal having a carrier frequency Fc, an AD converter for converting an output signal of the bandpass filter into a digital signal in a complementary representation, and a conversion timing of the AD converter. Frequency Fs for
And a first and a second flip-flop for latching the output signal of the AD converter at the rising and falling timings of a signal obtained by dividing the output signal of the oscillator by 1/2. And a first and second conversion unit for converting the sign by adding an output signal of the first and second flip-flops of the switching unit and a signal obtained by dividing the output signal of the oscillator by 1/4. 2 is a code converter including an exclusive OR circuit, and the carrier frequency Fc and the oscillation frequency Fs of the oscillator are Fs = 4Fc / (4k + 1) (where k = natural number) or Fs = 4Fc / ( 4k + 3) (where, k = natural number) is selected as a demodulation circuit. 5. A tap coefficient variable filter for adding signals of two systems alternately output by the switching unit, and a timing control unit for controlling the tap coefficient variable filter, the timing control unit Is configured to control the tap coefficient and the output timing of the variable tap coefficient filter in accordance with the ratio between the conversion cycle and the bit cycle in the AD converter.
5. The demodulation circuit according to any one of 4 to 4. 6. A tap coefficient variable filter for adding signals of two systems alternately switched and output by the switching unit, and a timing control unit for controlling the tap coefficient variable filter, and the timing control unit. Is configured to control the tap coefficient and the output timing of the variable tap coefficient filter according to the ratio of the conversion cycle and the bit cycle in the AD converter and according to the timing correction signal from the bit timing reproduction circuit. The demodulation circuit according to any one of claims 1 to 4, further comprising: 7. The carrier frequency is set as a center frequency, and the center frequency is switched, and the oscillation frequency Fs of the oscillator and the carrier frequency Fc are Fs = 4.
7. The demodulation circuit according to claim 1, further comprising a bandpass filter selected so as to maintain a relationship of Fc / (4k + 1) or Fs = 4Fc / (4k + 3).