JP2009529740A5 - - Google Patents

Download PDF

Info

Publication number
JP2009529740A5
JP2009529740A5 JP2008558761A JP2008558761A JP2009529740A5 JP 2009529740 A5 JP2009529740 A5 JP 2009529740A5 JP 2008558761 A JP2008558761 A JP 2008558761A JP 2008558761 A JP2008558761 A JP 2008558761A JP 2009529740 A5 JP2009529740 A5 JP 2009529740A5
Authority
JP
Japan
Prior art keywords
memory location
reservation
load operation
cacheable memory
cacheable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008558761A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009529740A (ja
JP4566264B2 (ja
Filing date
Publication date
Priority claimed from US11/377,505 external-priority patent/US9390015B2/en
Application filed filed Critical
Publication of JP2009529740A publication Critical patent/JP2009529740A/ja
Publication of JP2009529740A5 publication Critical patent/JP2009529740A5/ja
Application granted granted Critical
Publication of JP4566264B2 publication Critical patent/JP4566264B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2008558761A 2006-03-16 2007-02-26 格納および予約命令を利用して関連アプリケーションと相互参照してキャッシュライン・ポーリングを行う方法、システム、装置、およびプログラム Active JP4566264B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/377,505 US9390015B2 (en) 2006-03-16 2006-03-16 Method for performing cacheline polling utilizing a store and reserve instruction
PCT/EP2007/051810 WO2007104638A2 (en) 2006-03-16 2007-02-26 Method, system, apparatus, and article of manufacture for performing cacheline polling utilizing a store and reserve instruction

Publications (3)

Publication Number Publication Date
JP2009529740A JP2009529740A (ja) 2009-08-20
JP2009529740A5 true JP2009529740A5 (enExample) 2010-06-03
JP4566264B2 JP4566264B2 (ja) 2010-10-20

Family

ID=38509831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008558761A Active JP4566264B2 (ja) 2006-03-16 2007-02-26 格納および予約命令を利用して関連アプリケーションと相互参照してキャッシュライン・ポーリングを行う方法、システム、装置、およびプログラム

Country Status (5)

Country Link
US (1) US9390015B2 (enExample)
EP (1) EP1994469B1 (enExample)
JP (1) JP4566264B2 (enExample)
CN (1) CN101401071B (enExample)
WO (1) WO2007104638A2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8219763B2 (en) * 2006-03-16 2012-07-10 International Business Machines Corporation Structure for performing cacheline polling utilizing a store and reserve instruction
US9983874B2 (en) * 2006-03-16 2018-05-29 International Business Machines Corporation Structure for a circuit function that implements a load when reservation lost instruction to perform cacheline polling
CN101510177B (zh) * 2009-03-06 2012-04-18 成都市华为赛门铁克科技有限公司 一种存储方法和存储系统
CN102739788B (zh) * 2012-06-25 2015-08-19 广州复旦奥特科技股份有限公司 一种基于eib协议的现场设备通信方法
KR101691756B1 (ko) * 2012-10-22 2016-12-30 인텔 코포레이션 코히어런스 프로토콜 테이블
JP6052406B2 (ja) * 2013-05-31 2016-12-27 日本電気株式会社 分散処理システム、分散処理装置、分散処理方法および分散処理プログラム
EP2840503A1 (de) * 2013-08-22 2015-02-25 Continental Automotive GmbH Verfahren zum Betreiben eines Pufferspeichers einer Datenverarbeitungsanlage und Datenverarbeitungsanlage
CN103760855B (zh) * 2014-01-09 2017-01-18 厦门立林科技有限公司 自组式模块化家居控制系统
GB2524063B (en) 2014-03-13 2020-07-01 Advanced Risc Mach Ltd Data processing apparatus for executing an access instruction for N threads
US11086672B2 (en) 2019-05-07 2021-08-10 International Business Machines Corporation Low latency management of processor core wait state
CN119248353B (zh) * 2024-09-28 2025-04-15 北京工商大学 一种探针处理器

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380798A (en) * 1980-09-15 1983-04-19 Motorola, Inc. Semaphore register including ownership bits
US5669002A (en) * 1990-06-28 1997-09-16 Digital Equipment Corp. Multi-processor resource locking mechanism with a lock register corresponding to each resource stored in common memory
US5574922A (en) * 1994-06-17 1996-11-12 Apple Computer, Inc. Processor with sequences of processor instructions for locked memory updates
JP2507235B2 (ja) 1994-06-24 1996-06-12 インターナショナル・ビジネス・マシーンズ・コーポレイション クライアント・サ―バ・コンピュ―タ・システム、及びそのクライアント・コンピュ―タ、サ―バ・コンピュ―タ、並びにオブジェクト更新方法
US5611074A (en) * 1994-12-14 1997-03-11 International Business Machines Corporation Efficient polling technique using cache coherent protocol
JPH10149285A (ja) * 1996-11-18 1998-06-02 Hitachi Ltd 命令実行制御方法および情報処理装置
US6141734A (en) * 1998-02-03 2000-10-31 Compaq Computer Corporation Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol
WO2001050241A2 (en) 1999-12-30 2001-07-12 Koninklijke Philips Electronics N.V. Multi-tasking software architecture
US20030115476A1 (en) * 2001-10-31 2003-06-19 Mckee Bret Hardware-enforced control of access to memory within a computer using hardware-enforced semaphores and other similar, hardware-enforced serialization and sequencing mechanisms
US6904504B2 (en) * 2001-11-14 2005-06-07 Intel Corporation Method and apparatus for software selection of protected register settings
US7080209B2 (en) * 2002-12-24 2006-07-18 Intel Corporation Method and apparatus for processing a load-lock instruction using a relaxed lock protocol
US20050120185A1 (en) * 2003-12-01 2005-06-02 Sony Computer Entertainment Inc. Methods and apparatus for efficient multi-tasking
US7516306B2 (en) * 2004-10-05 2009-04-07 International Business Machines Corporation Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies
US7581067B2 (en) * 2006-03-16 2009-08-25 International Business Machines Corporation Load when reservation lost instruction for performing cacheline polling
US8219763B2 (en) 2006-03-16 2012-07-10 International Business Machines Corporation Structure for performing cacheline polling utilizing a store and reserve instruction
US7600076B2 (en) * 2006-03-16 2009-10-06 International Business Machines Corporation Method, system, apparatus, and article of manufacture for performing cacheline polling utilizing store with reserve and load when reservation lost instructions
US8117389B2 (en) 2006-03-16 2012-02-14 International Business Machines Corporation Design structure for performing cacheline polling utilizing store with reserve and load when reservation lost instructions

Similar Documents

Publication Publication Date Title
JP2009529740A5 (enExample)
JP2017513116A5 (enExample)
JP2005339561A5 (enExample)
JP2014527249A5 (enExample)
JP2009134771A5 (enExample)
US20180059987A1 (en) Method for reducing read buffer size requirements in nvme based solid state drives
JP2013504127A5 (enExample)
US9606923B2 (en) Information processing device with shared memory, memory order guarantee method using counters fence instructions in relation to cache-oriented requests, and recording medium storing program
JP6137582B2 (ja) 電子デバイス、メモリコントローラ、装置
JP2015513715A5 (enExample)
JP2010191717A5 (enExample)
JP2007156824A5 (enExample)
JP2011508296A5 (enExample)
WO2007104638A3 (en) Method, system, apparatus, and article of manufacture for performing cacheline polling utilizing a store and reserve instruction
JP2008522264A5 (enExample)
CN105474183A (zh) 存储器管理
JP2017527027A5 (enExample)
JP5499987B2 (ja) 共有キャッシュメモリ装置
US20170062023A1 (en) Systems and methods to rejuvenate nonvolatile memory using timestamps
JP6017171B2 (ja) 処理パイプラインの制御
JP2008139916A5 (enExample)
US9501332B2 (en) System and method to reset a lock indication
JP6963552B2 (ja) ブロックアトミック実行モデルを利用するプロセッサベースシステムにおける部分的に実行された命令ブロックのリプレイ
US10095637B2 (en) Speculative retirement of post-lock instructions
JP2014186675A5 (enExample)