CN101401071B - 利用存储和预留指令执行高速缓存线轮询操作的方法、系统、设备和产品 - Google Patents

利用存储和预留指令执行高速缓存线轮询操作的方法、系统、设备和产品 Download PDF

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CN101401071B
CN101401071B CN2007800089935A CN200780008993A CN101401071B CN 101401071 B CN101401071 B CN 101401071B CN 2007800089935 A CN2007800089935 A CN 2007800089935A CN 200780008993 A CN200780008993 A CN 200780008993A CN 101401071 B CN101401071 B CN 101401071B
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reservation
data
storage area
memory
load operation
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CN101401071A (zh
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C·R·约翰斯
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN2007800089935A 2006-03-16 2007-02-26 利用存储和预留指令执行高速缓存线轮询操作的方法、系统、设备和产品 Active CN101401071B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/377,505 2006-03-16
US11/377,505 US9390015B2 (en) 2006-03-16 2006-03-16 Method for performing cacheline polling utilizing a store and reserve instruction
PCT/EP2007/051810 WO2007104638A2 (en) 2006-03-16 2007-02-26 Method, system, apparatus, and article of manufacture for performing cacheline polling utilizing a store and reserve instruction

Publications (2)

Publication Number Publication Date
CN101401071A CN101401071A (zh) 2009-04-01
CN101401071B true CN101401071B (zh) 2012-06-20

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CN2007800089935A Active CN101401071B (zh) 2006-03-16 2007-02-26 利用存储和预留指令执行高速缓存线轮询操作的方法、系统、设备和产品

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Country Link
US (1) US9390015B2 (enExample)
EP (1) EP1994469B1 (enExample)
JP (1) JP4566264B2 (enExample)
CN (1) CN101401071B (enExample)
WO (1) WO2007104638A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11086672B2 (en) 2019-05-07 2021-08-10 International Business Machines Corporation Low latency management of processor core wait state

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9983874B2 (en) * 2006-03-16 2018-05-29 International Business Machines Corporation Structure for a circuit function that implements a load when reservation lost instruction to perform cacheline polling
US8219763B2 (en) * 2006-03-16 2012-07-10 International Business Machines Corporation Structure for performing cacheline polling utilizing a store and reserve instruction
CN101510177B (zh) * 2009-03-06 2012-04-18 成都市华为赛门铁克科技有限公司 一种存储方法和存储系统
CN102739788B (zh) * 2012-06-25 2015-08-19 广州复旦奥特科技股份有限公司 一种基于eib协议的现场设备通信方法
CN108055214B (zh) * 2012-10-22 2021-04-13 英特尔公司 用于对数据进行通信的装置和系统
JP6052406B2 (ja) * 2013-05-31 2016-12-27 日本電気株式会社 分散処理システム、分散処理装置、分散処理方法および分散処理プログラム
EP2840503A1 (de) * 2013-08-22 2015-02-25 Continental Automotive GmbH Verfahren zum Betreiben eines Pufferspeichers einer Datenverarbeitungsanlage und Datenverarbeitungsanlage
CN103760855B (zh) * 2014-01-09 2017-01-18 厦门立林科技有限公司 自组式模块化家居控制系统
GB2524063B (en) 2014-03-13 2020-07-01 Advanced Risc Mach Ltd Data processing apparatus for executing an access instruction for N threads
CN119248353B (zh) * 2024-09-28 2025-04-15 北京工商大学 一种探针处理器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5611074A (en) * 1994-12-14 1997-03-11 International Business Machines Corporation Efficient polling technique using cache coherent protocol
US5734898A (en) * 1994-06-24 1998-03-31 International Business Machines Corporation Client-server computer system and method for updating the client, server, and objects
CN1360696A (zh) * 1999-12-30 2002-07-24 皇家菲利浦电子有限公司 多任务处理软件体系结构

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380798A (en) * 1980-09-15 1983-04-19 Motorola, Inc. Semaphore register including ownership bits
US5669002A (en) * 1990-06-28 1997-09-16 Digital Equipment Corp. Multi-processor resource locking mechanism with a lock register corresponding to each resource stored in common memory
US5574922A (en) * 1994-06-17 1996-11-12 Apple Computer, Inc. Processor with sequences of processor instructions for locked memory updates
JPH10149285A (ja) * 1996-11-18 1998-06-02 Hitachi Ltd 命令実行制御方法および情報処理装置
US6141734A (en) * 1998-02-03 2000-10-31 Compaq Computer Corporation Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol
US20030115476A1 (en) * 2001-10-31 2003-06-19 Mckee Bret Hardware-enforced control of access to memory within a computer using hardware-enforced semaphores and other similar, hardware-enforced serialization and sequencing mechanisms
US6904504B2 (en) * 2001-11-14 2005-06-07 Intel Corporation Method and apparatus for software selection of protected register settings
US7080209B2 (en) * 2002-12-24 2006-07-18 Intel Corporation Method and apparatus for processing a load-lock instruction using a relaxed lock protocol
US20050120185A1 (en) * 2003-12-01 2005-06-02 Sony Computer Entertainment Inc. Methods and apparatus for efficient multi-tasking
US7516306B2 (en) * 2004-10-05 2009-04-07 International Business Machines Corporation Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies
US7581067B2 (en) * 2006-03-16 2009-08-25 International Business Machines Corporation Load when reservation lost instruction for performing cacheline polling
US7600076B2 (en) * 2006-03-16 2009-10-06 International Business Machines Corporation Method, system, apparatus, and article of manufacture for performing cacheline polling utilizing store with reserve and load when reservation lost instructions
US8219763B2 (en) 2006-03-16 2012-07-10 International Business Machines Corporation Structure for performing cacheline polling utilizing a store and reserve instruction
US8117389B2 (en) 2006-03-16 2012-02-14 International Business Machines Corporation Design structure for performing cacheline polling utilizing store with reserve and load when reservation lost instructions

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734898A (en) * 1994-06-24 1998-03-31 International Business Machines Corporation Client-server computer system and method for updating the client, server, and objects
US5611074A (en) * 1994-12-14 1997-03-11 International Business Machines Corporation Efficient polling technique using cache coherent protocol
CN1360696A (zh) * 1999-12-30 2002-07-24 皇家菲利浦电子有限公司 多任务处理软件体系结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11086672B2 (en) 2019-05-07 2021-08-10 International Business Machines Corporation Low latency management of processor core wait state

Also Published As

Publication number Publication date
WO2007104638A3 (en) 2007-12-13
EP1994469B1 (en) 2016-06-08
JP2009529740A (ja) 2009-08-20
CN101401071A (zh) 2009-04-01
EP1994469A2 (en) 2008-11-26
US9390015B2 (en) 2016-07-12
US20070220212A1 (en) 2007-09-20
JP4566264B2 (ja) 2010-10-20
WO2007104638A2 (en) 2007-09-20

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